Macros
#define	ADC_MULTIMODE_SUPPORT
#define	ADC_SR_AWD_Pos (0U)
#define	ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
#define	ADC_SR_AWD ADC_SR_AWD_Msk
#define	ADC_SR_EOC_Pos (1U)
#define	ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
#define	ADC_SR_EOC ADC_SR_EOC_Msk
#define	ADC_SR_JEOC_Pos (2U)
#define	ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
#define	ADC_SR_JEOC ADC_SR_JEOC_Msk
#define	ADC_SR_JSTRT_Pos (3U)
#define	ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
#define	ADC_SR_JSTRT ADC_SR_JSTRT_Msk
#define	ADC_SR_STRT_Pos (4U)
#define	ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
#define	ADC_SR_STRT ADC_SR_STRT_Msk
#define	ADC_SR_OVR_Pos (5U)
#define	ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
#define	ADC_SR_OVR ADC_SR_OVR_Msk
#define	ADC_CR1_AWDCH_Pos (0U)
#define	ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
#define	ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
#define	ADC_CR1_EOCIE_Pos (5U)
#define	ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
#define	ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
#define	ADC_CR1_AWDIE_Pos (6U)
#define	ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
#define	ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
#define	ADC_CR1_JEOCIE_Pos (7U)
#define	ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
#define	ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
#define	ADC_CR1_SCAN_Pos (8U)
#define	ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
#define	ADC_CR1_SCAN ADC_CR1_SCAN_Msk
#define	ADC_CR1_AWDSGL_Pos (9U)
#define	ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
#define	ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
#define	ADC_CR1_JAUTO_Pos (10U)
#define	ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
#define	ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
#define	ADC_CR1_DISCEN_Pos (11U)
#define	ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
#define	ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
#define	ADC_CR1_JDISCEN_Pos (12U)
#define	ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
#define	ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
#define	ADC_CR1_DISCNUM_Pos (13U)
#define	ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
#define	ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
#define	ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
#define	ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
#define	ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
#define	ADC_CR1_JAWDEN_Pos (22U)
#define	ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
#define	ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
#define	ADC_CR1_AWDEN_Pos (23U)
#define	ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
#define	ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
#define	ADC_CR1_RES_Pos (24U)
#define	ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
#define	ADC_CR1_RES ADC_CR1_RES_Msk
#define	ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
#define	ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
#define	ADC_CR1_OVRIE_Pos (26U)
#define	ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
#define	ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
#define	ADC_CR2_ADON_Pos (0U)
#define	ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
#define	ADC_CR2_ADON ADC_CR2_ADON_Msk
#define	ADC_CR2_CONT_Pos (1U)
#define	ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
#define	ADC_CR2_CONT ADC_CR2_CONT_Msk
#define	ADC_CR2_DMA_Pos (8U)
#define	ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
#define	ADC_CR2_DMA ADC_CR2_DMA_Msk
#define	ADC_CR2_DDS_Pos (9U)
#define	ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
#define	ADC_CR2_DDS ADC_CR2_DDS_Msk
#define	ADC_CR2_EOCS_Pos (10U)
#define	ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
#define	ADC_CR2_EOCS ADC_CR2_EOCS_Msk
#define	ADC_CR2_ALIGN_Pos (11U)
#define	ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
#define	ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
#define	ADC_CR2_JEXTSEL_Pos (16U)
#define	ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
#define	ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
#define	ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
#define	ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
#define	ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
#define	ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
#define	ADC_CR2_JEXTEN_Pos (20U)
#define	ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
#define	ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
#define	ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
#define	ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
#define	ADC_CR2_JSWSTART_Pos (22U)
#define	ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
#define	ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
#define	ADC_CR2_EXTSEL_Pos (24U)
#define	ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
#define	ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
#define	ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
#define	ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
#define	ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
#define	ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
#define	ADC_CR2_EXTEN_Pos (28U)
#define	ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
#define	ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
#define	ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
#define	ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
#define	ADC_CR2_SWSTART_Pos (30U)
#define	ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
#define	ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
#define	ADC_SMPR1_SMP10_Pos (0U)
#define	ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
#define	ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
#define	ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
#define	ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
#define	ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
#define	ADC_SMPR1_SMP11_Pos (3U)
#define	ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
#define	ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
#define	ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
#define	ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
#define	ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
#define	ADC_SMPR1_SMP12_Pos (6U)
#define	ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
#define	ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
#define	ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
#define	ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
#define	ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
#define	ADC_SMPR1_SMP13_Pos (9U)
#define	ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
#define	ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
#define	ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
#define	ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
#define	ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
#define	ADC_SMPR1_SMP14_Pos (12U)
#define	ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
#define	ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
#define	ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
#define	ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
#define	ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
#define	ADC_SMPR1_SMP15_Pos (15U)
#define	ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
#define	ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
#define	ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
#define	ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
#define	ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
#define	ADC_SMPR1_SMP16_Pos (18U)
#define	ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
#define	ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
#define	ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
#define	ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
#define	ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
#define	ADC_SMPR1_SMP17_Pos (21U)
#define	ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
#define	ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
#define	ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
#define	ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
#define	ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
#define	ADC_SMPR1_SMP18_Pos (24U)
#define	ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
#define	ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
#define	ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
#define	ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
#define	ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
#define	ADC_SMPR2_SMP0_Pos (0U)
#define	ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
#define	ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
#define	ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
#define	ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
#define	ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
#define	ADC_SMPR2_SMP1_Pos (3U)
#define	ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
#define	ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
#define	ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
#define	ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
#define	ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
#define	ADC_SMPR2_SMP2_Pos (6U)
#define	ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
#define	ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
#define	ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
#define	ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
#define	ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
#define	ADC_SMPR2_SMP3_Pos (9U)
#define	ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
#define	ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
#define	ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
#define	ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
#define	ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
#define	ADC_SMPR2_SMP4_Pos (12U)
#define	ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
#define	ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
#define	ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
#define	ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
#define	ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
#define	ADC_SMPR2_SMP5_Pos (15U)
#define	ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
#define	ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
#define	ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
#define	ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
#define	ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
#define	ADC_SMPR2_SMP6_Pos (18U)
#define	ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
#define	ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
#define	ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
#define	ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
#define	ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
#define	ADC_SMPR2_SMP7_Pos (21U)
#define	ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
#define	ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
#define	ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
#define	ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
#define	ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
#define	ADC_SMPR2_SMP8_Pos (24U)
#define	ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
#define	ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
#define	ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
#define	ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
#define	ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
#define	ADC_SMPR2_SMP9_Pos (27U)
#define	ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
#define	ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
#define	ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
#define	ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
#define	ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
#define	ADC_JOFR1_JOFFSET1_Pos (0U)
#define	ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
#define	ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
#define	ADC_JOFR2_JOFFSET2_Pos (0U)
#define	ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
#define	ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
#define	ADC_JOFR3_JOFFSET3_Pos (0U)
#define	ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
#define	ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
#define	ADC_JOFR4_JOFFSET4_Pos (0U)
#define	ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
#define	ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
#define	ADC_HTR_HT_Pos (0U)
#define	ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
#define	ADC_HTR_HT ADC_HTR_HT_Msk
#define	ADC_LTR_LT_Pos (0U)
#define	ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
#define	ADC_LTR_LT ADC_LTR_LT_Msk
#define	ADC_SQR1_SQ13_Pos (0U)
#define	ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
#define	ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
#define	ADC_SQR1_SQ14_Pos (5U)
#define	ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
#define	ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
#define	ADC_SQR1_SQ15_Pos (10U)
#define	ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
#define	ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
#define	ADC_SQR1_SQ16_Pos (15U)
#define	ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
#define	ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
#define	ADC_SQR1_L_Pos (20U)
#define	ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
#define	ADC_SQR1_L ADC_SQR1_L_Msk
#define	ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
#define	ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
#define	ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
#define	ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
#define	ADC_SQR2_SQ7_Pos (0U)
#define	ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
#define	ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
#define	ADC_SQR2_SQ8_Pos (5U)
#define	ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
#define	ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
#define	ADC_SQR2_SQ9_Pos (10U)
#define	ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
#define	ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
#define	ADC_SQR2_SQ10_Pos (15U)
#define	ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
#define	ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
#define	ADC_SQR2_SQ11_Pos (20U)
#define	ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
#define	ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
#define	ADC_SQR2_SQ12_Pos (25U)
#define	ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
#define	ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
#define	ADC_SQR3_SQ1_Pos (0U)
#define	ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
#define	ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
#define	ADC_SQR3_SQ2_Pos (5U)
#define	ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
#define	ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
#define	ADC_SQR3_SQ3_Pos (10U)
#define	ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
#define	ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
#define	ADC_SQR3_SQ4_Pos (15U)
#define	ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
#define	ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
#define	ADC_SQR3_SQ5_Pos (20U)
#define	ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
#define	ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
#define	ADC_SQR3_SQ6_Pos (25U)
#define	ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
#define	ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
#define	ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
#define	ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
#define	ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
#define	ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
#define	ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
#define	ADC_JSQR_JSQ1_Pos (0U)
#define	ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
#define	ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
#define	ADC_JSQR_JSQ2_Pos (5U)
#define	ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
#define	ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
#define	ADC_JSQR_JSQ3_Pos (10U)
#define	ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
#define	ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
#define	ADC_JSQR_JSQ4_Pos (15U)
#define	ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
#define	ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
#define	ADC_JSQR_JL_Pos (20U)
#define	ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
#define	ADC_JSQR_JL ADC_JSQR_JL_Msk
#define	ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
#define	ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
#define	ADC_JDR1_JDATA_Pos (0U)
#define	ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
#define	ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
#define	ADC_JDR2_JDATA_Pos (0U)
#define	ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
#define	ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
#define	ADC_JDR3_JDATA_Pos (0U)
#define	ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
#define	ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
#define	ADC_JDR4_JDATA_Pos (0U)
#define	ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
#define	ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
#define	ADC_DR_DATA_Pos (0U)
#define	ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
#define	ADC_DR_DATA ADC_DR_DATA_Msk
#define	ADC_DR_ADC2DATA_Pos (16U)
#define	ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
#define	ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
#define	ADC_CSR_AWD1_Pos (0U)
#define	ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
#define	ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
#define	ADC_CSR_EOC1_Pos (1U)
#define	ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
#define	ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
#define	ADC_CSR_JEOC1_Pos (2U)
#define	ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
#define	ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
#define	ADC_CSR_JSTRT1_Pos (3U)
#define	ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
#define	ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
#define	ADC_CSR_STRT1_Pos (4U)
#define	ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
#define	ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
#define	ADC_CSR_OVR1_Pos (5U)
#define	ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
#define	ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
#define	ADC_CSR_AWD2_Pos (8U)
#define	ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
#define	ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
#define	ADC_CSR_EOC2_Pos (9U)
#define	ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
#define	ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
#define	ADC_CSR_JEOC2_Pos (10U)
#define	ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
#define	ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
#define	ADC_CSR_JSTRT2_Pos (11U)
#define	ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
#define	ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
#define	ADC_CSR_STRT2_Pos (12U)
#define	ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
#define	ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
#define	ADC_CSR_OVR2_Pos (13U)
#define	ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
#define	ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
#define	ADC_CSR_AWD3_Pos (16U)
#define	ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
#define	ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
#define	ADC_CSR_EOC3_Pos (17U)
#define	ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
#define	ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
#define	ADC_CSR_JEOC3_Pos (18U)
#define	ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
#define	ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
#define	ADC_CSR_JSTRT3_Pos (19U)
#define	ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
#define	ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
#define	ADC_CSR_STRT3_Pos (20U)
#define	ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
#define	ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
#define	ADC_CSR_OVR3_Pos (21U)
#define	ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
#define	ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
#define	ADC_CSR_DOVR1 ADC_CSR_OVR1
#define	ADC_CSR_DOVR2 ADC_CSR_OVR2
#define	ADC_CSR_DOVR3 ADC_CSR_OVR3
#define	ADC_CCR_MULTI_Pos (0U)
#define	ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_MULTI ADC_CCR_MULTI_Msk
#define	ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
#define	ADC_CCR_DELAY_Pos (8U)
#define	ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
#define	ADC_CCR_DELAY ADC_CCR_DELAY_Msk
#define	ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
#define	ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
#define	ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
#define	ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
#define	ADC_CCR_DDS_Pos (13U)
#define	ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
#define	ADC_CCR_DDS ADC_CCR_DDS_Msk
#define	ADC_CCR_DMA_Pos (14U)
#define	ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
#define	ADC_CCR_DMA ADC_CCR_DMA_Msk
#define	ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
#define	ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
#define	ADC_CCR_ADCPRE_Pos (16U)
#define	ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
#define	ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
#define	ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
#define	ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
#define	ADC_CCR_VBATE_Pos (22U)
#define	ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
#define	ADC_CCR_VBATE ADC_CCR_VBATE_Msk
#define	ADC_CCR_TSVREFE_Pos (23U)
#define	ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
#define	ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
#define	ADC_CDR_DATA1_Pos (0U)
#define	ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
#define	ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
#define	ADC_CDR_DATA2_Pos (16U)
#define	ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
#define	ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
#define	ADC_CDR_RDATA_MST ADC_CDR_DATA1
#define	ADC_CDR_RDATA_SLV ADC_CDR_DATA2
#define	CAN_MCR_INRQ_Pos (0U)
#define	CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
#define	CAN_MCR_INRQ CAN_MCR_INRQ_Msk
#define	CAN_MCR_SLEEP_Pos (1U)
#define	CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
#define	CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
#define	CAN_MCR_TXFP_Pos (2U)
#define	CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
#define	CAN_MCR_TXFP CAN_MCR_TXFP_Msk
#define	CAN_MCR_RFLM_Pos (3U)
#define	CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
#define	CAN_MCR_RFLM CAN_MCR_RFLM_Msk
#define	CAN_MCR_NART_Pos (4U)
#define	CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
#define	CAN_MCR_NART CAN_MCR_NART_Msk
#define	CAN_MCR_AWUM_Pos (5U)
#define	CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
#define	CAN_MCR_AWUM CAN_MCR_AWUM_Msk
#define	CAN_MCR_ABOM_Pos (6U)
#define	CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
#define	CAN_MCR_ABOM CAN_MCR_ABOM_Msk
#define	CAN_MCR_TTCM_Pos (7U)
#define	CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
#define	CAN_MCR_TTCM CAN_MCR_TTCM_Msk
#define	CAN_MCR_RESET_Pos (15U)
#define	CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
#define	CAN_MCR_RESET CAN_MCR_RESET_Msk
#define	CAN_MCR_DBF_Pos (16U)
#define	CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
#define	CAN_MCR_DBF CAN_MCR_DBF_Msk
#define	CAN_MSR_INAK_Pos (0U)
#define	CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
#define	CAN_MSR_INAK CAN_MSR_INAK_Msk
#define	CAN_MSR_SLAK_Pos (1U)
#define	CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
#define	CAN_MSR_SLAK CAN_MSR_SLAK_Msk
#define	CAN_MSR_ERRI_Pos (2U)
#define	CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
#define	CAN_MSR_ERRI CAN_MSR_ERRI_Msk
#define	CAN_MSR_WKUI_Pos (3U)
#define	CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
#define	CAN_MSR_WKUI CAN_MSR_WKUI_Msk
#define	CAN_MSR_SLAKI_Pos (4U)
#define	CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
#define	CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
#define	CAN_MSR_TXM_Pos (8U)
#define	CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
#define	CAN_MSR_TXM CAN_MSR_TXM_Msk
#define	CAN_MSR_RXM_Pos (9U)
#define	CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
#define	CAN_MSR_RXM CAN_MSR_RXM_Msk
#define	CAN_MSR_SAMP_Pos (10U)
#define	CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
#define	CAN_MSR_SAMP CAN_MSR_SAMP_Msk
#define	CAN_MSR_RX_Pos (11U)
#define	CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
#define	CAN_MSR_RX CAN_MSR_RX_Msk
#define	CAN_TSR_RQCP0_Pos (0U)
#define	CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
#define	CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
#define	CAN_TSR_TXOK0_Pos (1U)
#define	CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
#define	CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
#define	CAN_TSR_ALST0_Pos (2U)
#define	CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
#define	CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
#define	CAN_TSR_TERR0_Pos (3U)
#define	CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
#define	CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
#define	CAN_TSR_ABRQ0_Pos (7U)
#define	CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
#define	CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
#define	CAN_TSR_RQCP1_Pos (8U)
#define	CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
#define	CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
#define	CAN_TSR_TXOK1_Pos (9U)
#define	CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
#define	CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
#define	CAN_TSR_ALST1_Pos (10U)
#define	CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
#define	CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
#define	CAN_TSR_TERR1_Pos (11U)
#define	CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
#define	CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
#define	CAN_TSR_ABRQ1_Pos (15U)
#define	CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
#define	CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
#define	CAN_TSR_RQCP2_Pos (16U)
#define	CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
#define	CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
#define	CAN_TSR_TXOK2_Pos (17U)
#define	CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
#define	CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
#define	CAN_TSR_ALST2_Pos (18U)
#define	CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
#define	CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
#define	CAN_TSR_TERR2_Pos (19U)
#define	CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
#define	CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
#define	CAN_TSR_ABRQ2_Pos (23U)
#define	CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
#define	CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
#define	CAN_TSR_CODE_Pos (24U)
#define	CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
#define	CAN_TSR_CODE CAN_TSR_CODE_Msk
#define	CAN_TSR_TME_Pos (26U)
#define	CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
#define	CAN_TSR_TME CAN_TSR_TME_Msk
#define	CAN_TSR_TME0_Pos (26U)
#define	CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
#define	CAN_TSR_TME0 CAN_TSR_TME0_Msk
#define	CAN_TSR_TME1_Pos (27U)
#define	CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
#define	CAN_TSR_TME1 CAN_TSR_TME1_Msk
#define	CAN_TSR_TME2_Pos (28U)
#define	CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
#define	CAN_TSR_TME2 CAN_TSR_TME2_Msk
#define	CAN_TSR_LOW_Pos (29U)
#define	CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
#define	CAN_TSR_LOW CAN_TSR_LOW_Msk
#define	CAN_TSR_LOW0_Pos (29U)
#define	CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
#define	CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
#define	CAN_TSR_LOW1_Pos (30U)
#define	CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
#define	CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
#define	CAN_TSR_LOW2_Pos (31U)
#define	CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
#define	CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
#define	CAN_RF0R_FMP0_Pos (0U)
#define	CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
#define	CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
#define	CAN_RF0R_FULL0_Pos (3U)
#define	CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
#define	CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
#define	CAN_RF0R_FOVR0_Pos (4U)
#define	CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
#define	CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
#define	CAN_RF0R_RFOM0_Pos (5U)
#define	CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
#define	CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
#define	CAN_RF1R_FMP1_Pos (0U)
#define	CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
#define	CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
#define	CAN_RF1R_FULL1_Pos (3U)
#define	CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
#define	CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
#define	CAN_RF1R_FOVR1_Pos (4U)
#define	CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
#define	CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
#define	CAN_RF1R_RFOM1_Pos (5U)
#define	CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
#define	CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
#define	CAN_IER_TMEIE_Pos (0U)
#define	CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
#define	CAN_IER_TMEIE CAN_IER_TMEIE_Msk
#define	CAN_IER_FMPIE0_Pos (1U)
#define	CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
#define	CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
#define	CAN_IER_FFIE0_Pos (2U)
#define	CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
#define	CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
#define	CAN_IER_FOVIE0_Pos (3U)
#define	CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
#define	CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
#define	CAN_IER_FMPIE1_Pos (4U)
#define	CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
#define	CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
#define	CAN_IER_FFIE1_Pos (5U)
#define	CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
#define	CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
#define	CAN_IER_FOVIE1_Pos (6U)
#define	CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
#define	CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
#define	CAN_IER_EWGIE_Pos (8U)
#define	CAN_IER_EWGIE_Pos (8U)
#define	CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
#define	CAN_IER_EWGIE CAN_IER_EWGIE_Msk
#define	CAN_IER_EPVIE_Pos (9U)
#define	CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
#define	CAN_IER_EPVIE CAN_IER_EPVIE_Msk
#define	CAN_IER_BOFIE_Pos (10U)
#define	CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
#define	CAN_IER_BOFIE CAN_IER_BOFIE_Msk
#define	CAN_IER_LECIE_Pos (11U)
#define	CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
#define	CAN_IER_LECIE CAN_IER_LECIE_Msk
#define	CAN_IER_ERRIE_Pos (15U)
#define	CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
#define	CAN_IER_ERRIE CAN_IER_ERRIE_Msk
#define	CAN_IER_WKUIE_Pos (16U)
#define	CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
#define	CAN_IER_WKUIE CAN_IER_WKUIE_Msk
#define	CAN_IER_SLKIE_Pos (17U)
#define	CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
#define	CAN_IER_SLKIE CAN_IER_SLKIE_Msk
#define	CAN_ESR_EWGF_Pos (0U)
#define	CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
#define	CAN_ESR_EWGF CAN_ESR_EWGF_Msk
#define	CAN_ESR_EPVF_Pos (1U)
#define	CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
#define	CAN_ESR_EPVF CAN_ESR_EPVF_Msk
#define	CAN_ESR_BOFF_Pos (2U)
#define	CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
#define	CAN_ESR_BOFF CAN_ESR_BOFF_Msk
#define	CAN_ESR_LEC_Pos (4U)
#define	CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
#define	CAN_ESR_LEC CAN_ESR_LEC_Msk
#define	CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
#define	CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
#define	CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
#define	CAN_ESR_TEC_Pos (16U)
#define	CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
#define	CAN_ESR_TEC CAN_ESR_TEC_Msk
#define	CAN_ESR_REC_Pos (24U)
#define	CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
#define	CAN_ESR_REC CAN_ESR_REC_Msk
#define	CAN_BTR_BRP_Pos (0U)
#define	CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
#define	CAN_BTR_BRP CAN_BTR_BRP_Msk
#define	CAN_BTR_TS1_Pos (16U)
#define	CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
#define	CAN_BTR_TS1 CAN_BTR_TS1_Msk
#define	CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
#define	CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
#define	CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
#define	CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
#define	CAN_BTR_TS2_Pos (20U)
#define	CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
#define	CAN_BTR_TS2 CAN_BTR_TS2_Msk
#define	CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
#define	CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
#define	CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
#define	CAN_BTR_SJW_Pos (24U)
#define	CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
#define	CAN_BTR_SJW CAN_BTR_SJW_Msk
#define	CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
#define	CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
#define	CAN_BTR_LBKM_Pos (30U)
#define	CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
#define	CAN_BTR_LBKM CAN_BTR_LBKM_Msk
#define	CAN_BTR_SILM_Pos (31U)
#define	CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
#define	CAN_BTR_SILM CAN_BTR_SILM_Msk
#define	CAN_TI0R_TXRQ_Pos (0U)
#define	CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
#define	CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
#define	CAN_TI0R_RTR_Pos (1U)
#define	CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
#define	CAN_TI0R_RTR CAN_TI0R_RTR_Msk
#define	CAN_TI0R_IDE_Pos (2U)
#define	CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
#define	CAN_TI0R_IDE CAN_TI0R_IDE_Msk
#define	CAN_TI0R_EXID_Pos (3U)
#define	CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
#define	CAN_TI0R_EXID CAN_TI0R_EXID_Msk
#define	CAN_TI0R_STID_Pos (21U)
#define	CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
#define	CAN_TI0R_STID CAN_TI0R_STID_Msk
#define	CAN_TDT0R_DLC_Pos (0U)
#define	CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
#define	CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
#define	CAN_TDT0R_TGT_Pos (8U)
#define	CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
#define	CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
#define	CAN_TDT0R_TIME_Pos (16U)
#define	CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
#define	CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
#define	CAN_TDL0R_DATA0_Pos (0U)
#define	CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
#define	CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
#define	CAN_TDL0R_DATA1_Pos (8U)
#define	CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
#define	CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
#define	CAN_TDL0R_DATA2_Pos (16U)
#define	CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
#define	CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
#define	CAN_TDL0R_DATA3_Pos (24U)
#define	CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
#define	CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
#define	CAN_TDH0R_DATA4_Pos (0U)
#define	CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
#define	CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
#define	CAN_TDH0R_DATA5_Pos (8U)
#define	CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
#define	CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
#define	CAN_TDH0R_DATA6_Pos (16U)
#define	CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
#define	CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
#define	CAN_TDH0R_DATA7_Pos (24U)
#define	CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
#define	CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
#define	CAN_TI1R_TXRQ_Pos (0U)
#define	CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
#define	CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
#define	CAN_TI1R_RTR_Pos (1U)
#define	CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
#define	CAN_TI1R_RTR CAN_TI1R_RTR_Msk
#define	CAN_TI1R_IDE_Pos (2U)
#define	CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
#define	CAN_TI1R_IDE CAN_TI1R_IDE_Msk
#define	CAN_TI1R_EXID_Pos (3U)
#define	CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
#define	CAN_TI1R_EXID CAN_TI1R_EXID_Msk
#define	CAN_TI1R_STID_Pos (21U)
#define	CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
#define	CAN_TI1R_STID CAN_TI1R_STID_Msk
#define	CAN_TDT1R_DLC_Pos (0U)
#define	CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
#define	CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
#define	CAN_TDT1R_TGT_Pos (8U)
#define	CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
#define	CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
#define	CAN_TDT1R_TIME_Pos (16U)
#define	CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
#define	CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
#define	CAN_TDL1R_DATA0_Pos (0U)
#define	CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
#define	CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
#define	CAN_TDL1R_DATA1_Pos (8U)
#define	CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
#define	CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
#define	CAN_TDL1R_DATA2_Pos (16U)
#define	CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
#define	CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
#define	CAN_TDL1R_DATA3_Pos (24U)
#define	CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
#define	CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
#define	CAN_TDH1R_DATA4_Pos (0U)
#define	CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
#define	CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
#define	CAN_TDH1R_DATA5_Pos (8U)
#define	CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
#define	CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
#define	CAN_TDH1R_DATA6_Pos (16U)
#define	CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
#define	CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
#define	CAN_TDH1R_DATA7_Pos (24U)
#define	CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
#define	CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
#define	CAN_TI2R_TXRQ_Pos (0U)
#define	CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
#define	CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
#define	CAN_TI2R_RTR_Pos (1U)
#define	CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
#define	CAN_TI2R_RTR CAN_TI2R_RTR_Msk
#define	CAN_TI2R_IDE_Pos (2U)
#define	CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
#define	CAN_TI2R_IDE CAN_TI2R_IDE_Msk
#define	CAN_TI2R_EXID_Pos (3U)
#define	CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
#define	CAN_TI2R_EXID CAN_TI2R_EXID_Msk
#define	CAN_TI2R_STID_Pos (21U)
#define	CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
#define	CAN_TI2R_STID CAN_TI2R_STID_Msk
#define	CAN_TDT2R_DLC_Pos (0U)
#define	CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
#define	CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
#define	CAN_TDT2R_TGT_Pos (8U)
#define	CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
#define	CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
#define	CAN_TDT2R_TIME_Pos (16U)
#define	CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
#define	CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
#define	CAN_TDL2R_DATA0_Pos (0U)
#define	CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
#define	CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
#define	CAN_TDL2R_DATA1_Pos (8U)
#define	CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
#define	CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
#define	CAN_TDL2R_DATA2_Pos (16U)
#define	CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
#define	CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
#define	CAN_TDL2R_DATA3_Pos (24U)
#define	CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
#define	CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
#define	CAN_TDH2R_DATA4_Pos (0U)
#define	CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
#define	CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
#define	CAN_TDH2R_DATA5_Pos (8U)
#define	CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
#define	CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
#define	CAN_TDH2R_DATA6_Pos (16U)
#define	CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
#define	CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
#define	CAN_TDH2R_DATA7_Pos (24U)
#define	CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
#define	CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
#define	CAN_RI0R_RTR_Pos (1U)
#define	CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
#define	CAN_RI0R_RTR CAN_RI0R_RTR_Msk
#define	CAN_RI0R_IDE_Pos (2U)
#define	CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
#define	CAN_RI0R_IDE CAN_RI0R_IDE_Msk
#define	CAN_RI0R_EXID_Pos (3U)
#define	CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
#define	CAN_RI0R_EXID CAN_RI0R_EXID_Msk
#define	CAN_RI0R_STID_Pos (21U)
#define	CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
#define	CAN_RI0R_STID CAN_RI0R_STID_Msk
#define	CAN_RDT0R_DLC_Pos (0U)
#define	CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
#define	CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
#define	CAN_RDT0R_FMI_Pos (8U)
#define	CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
#define	CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
#define	CAN_RDT0R_TIME_Pos (16U)
#define	CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
#define	CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
#define	CAN_RDL0R_DATA0_Pos (0U)
#define	CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
#define	CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
#define	CAN_RDL0R_DATA1_Pos (8U)
#define	CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
#define	CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
#define	CAN_RDL0R_DATA2_Pos (16U)
#define	CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
#define	CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
#define	CAN_RDL0R_DATA3_Pos (24U)
#define	CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
#define	CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
#define	CAN_RDH0R_DATA4_Pos (0U)
#define	CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
#define	CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
#define	CAN_RDH0R_DATA5_Pos (8U)
#define	CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
#define	CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
#define	CAN_RDH0R_DATA6_Pos (16U)
#define	CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
#define	CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
#define	CAN_RDH0R_DATA7_Pos (24U)
#define	CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
#define	CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
#define	CAN_RI1R_RTR_Pos (1U)
#define	CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
#define	CAN_RI1R_RTR CAN_RI1R_RTR_Msk
#define	CAN_RI1R_IDE_Pos (2U)
#define	CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
#define	CAN_RI1R_IDE CAN_RI1R_IDE_Msk
#define	CAN_RI1R_EXID_Pos (3U)
#define	CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
#define	CAN_RI1R_EXID CAN_RI1R_EXID_Msk
#define	CAN_RI1R_STID_Pos (21U)
#define	CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
#define	CAN_RI1R_STID CAN_RI1R_STID_Msk
#define	CAN_RDT1R_DLC_Pos (0U)
#define	CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
#define	CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
#define	CAN_RDT1R_FMI_Pos (8U)
#define	CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
#define	CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
#define	CAN_RDT1R_TIME_Pos (16U)
#define	CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
#define	CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
#define	CAN_RDL1R_DATA0_Pos (0U)
#define	CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
#define	CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
#define	CAN_RDL1R_DATA1_Pos (8U)
#define	CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
#define	CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
#define	CAN_RDL1R_DATA2_Pos (16U)
#define	CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
#define	CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
#define	CAN_RDL1R_DATA3_Pos (24U)
#define	CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
#define	CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
#define	CAN_RDH1R_DATA4_Pos (0U)
#define	CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
#define	CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
#define	CAN_RDH1R_DATA5_Pos (8U)
#define	CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
#define	CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
#define	CAN_RDH1R_DATA6_Pos (16U)
#define	CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
#define	CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
#define	CAN_RDH1R_DATA7_Pos (24U)
#define	CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
#define	CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
#define	CAN_FMR_FINIT_Pos (0U)
#define	CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
#define	CAN_FMR_FINIT CAN_FMR_FINIT_Msk
#define	CAN_FMR_CAN2SB_Pos (8U)
#define	CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
#define	CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
#define	CAN_FM1R_FBM_Pos (0U)
#define	CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
#define	CAN_FM1R_FBM CAN_FM1R_FBM_Msk
#define	CAN_FM1R_FBM0_Pos (0U)
#define	CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
#define	CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
#define	CAN_FM1R_FBM1_Pos (1U)
#define	CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
#define	CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
#define	CAN_FM1R_FBM2_Pos (2U)
#define	CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
#define	CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
#define	CAN_FM1R_FBM3_Pos (3U)
#define	CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
#define	CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
#define	CAN_FM1R_FBM4_Pos (4U)
#define	CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
#define	CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
#define	CAN_FM1R_FBM5_Pos (5U)
#define	CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
#define	CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
#define	CAN_FM1R_FBM6_Pos (6U)
#define	CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
#define	CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
#define	CAN_FM1R_FBM7_Pos (7U)
#define	CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
#define	CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
#define	CAN_FM1R_FBM8_Pos (8U)
#define	CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
#define	CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
#define	CAN_FM1R_FBM9_Pos (9U)
#define	CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
#define	CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
#define	CAN_FM1R_FBM10_Pos (10U)
#define	CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
#define	CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
#define	CAN_FM1R_FBM11_Pos (11U)
#define	CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
#define	CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
#define	CAN_FM1R_FBM12_Pos (12U)
#define	CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
#define	CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
#define	CAN_FM1R_FBM13_Pos (13U)
#define	CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
#define	CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
#define	CAN_FM1R_FBM14_Pos (14U)
#define	CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
#define	CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
#define	CAN_FM1R_FBM15_Pos (15U)
#define	CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
#define	CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
#define	CAN_FM1R_FBM16_Pos (16U)
#define	CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
#define	CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
#define	CAN_FM1R_FBM17_Pos (17U)
#define	CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
#define	CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
#define	CAN_FM1R_FBM18_Pos (18U)
#define	CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
#define	CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
#define	CAN_FM1R_FBM19_Pos (19U)
#define	CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
#define	CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
#define	CAN_FM1R_FBM20_Pos (20U)
#define	CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
#define	CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
#define	CAN_FM1R_FBM21_Pos (21U)
#define	CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
#define	CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
#define	CAN_FM1R_FBM22_Pos (22U)
#define	CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
#define	CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
#define	CAN_FM1R_FBM23_Pos (23U)
#define	CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
#define	CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
#define	CAN_FM1R_FBM24_Pos (24U)
#define	CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
#define	CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
#define	CAN_FM1R_FBM25_Pos (25U)
#define	CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
#define	CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
#define	CAN_FM1R_FBM26_Pos (26U)
#define	CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
#define	CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
#define	CAN_FM1R_FBM27_Pos (27U)
#define	CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
#define	CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
#define	CAN_FS1R_FSC_Pos (0U)
#define	CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
#define	CAN_FS1R_FSC CAN_FS1R_FSC_Msk
#define	CAN_FS1R_FSC0_Pos (0U)
#define	CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
#define	CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
#define	CAN_FS1R_FSC1_Pos (1U)
#define	CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
#define	CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
#define	CAN_FS1R_FSC2_Pos (2U)
#define	CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
#define	CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
#define	CAN_FS1R_FSC3_Pos (3U)
#define	CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
#define	CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
#define	CAN_FS1R_FSC4_Pos (4U)
#define	CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
#define	CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
#define	CAN_FS1R_FSC5_Pos (5U)
#define	CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
#define	CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
#define	CAN_FS1R_FSC6_Pos (6U)
#define	CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
#define	CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
#define	CAN_FS1R_FSC7_Pos (7U)
#define	CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
#define	CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
#define	CAN_FS1R_FSC8_Pos (8U)
#define	CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
#define	CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
#define	CAN_FS1R_FSC9_Pos (9U)
#define	CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
#define	CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
#define	CAN_FS1R_FSC10_Pos (10U)
#define	CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
#define	CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
#define	CAN_FS1R_FSC11_Pos (11U)
#define	CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
#define	CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
#define	CAN_FS1R_FSC12_Pos (12U)
#define	CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
#define	CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
#define	CAN_FS1R_FSC13_Pos (13U)
#define	CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
#define	CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
#define	CAN_FS1R_FSC14_Pos (14U)
#define	CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
#define	CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
#define	CAN_FS1R_FSC15_Pos (15U)
#define	CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
#define	CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
#define	CAN_FS1R_FSC16_Pos (16U)
#define	CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
#define	CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
#define	CAN_FS1R_FSC17_Pos (17U)
#define	CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
#define	CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
#define	CAN_FS1R_FSC18_Pos (18U)
#define	CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
#define	CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
#define	CAN_FS1R_FSC19_Pos (19U)
#define	CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
#define	CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
#define	CAN_FS1R_FSC20_Pos (20U)
#define	CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
#define	CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
#define	CAN_FS1R_FSC21_Pos (21U)
#define	CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
#define	CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
#define	CAN_FS1R_FSC22_Pos (22U)
#define	CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
#define	CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
#define	CAN_FS1R_FSC23_Pos (23U)
#define	CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
#define	CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
#define	CAN_FS1R_FSC24_Pos (24U)
#define	CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
#define	CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
#define	CAN_FS1R_FSC25_Pos (25U)
#define	CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
#define	CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
#define	CAN_FS1R_FSC26_Pos (26U)
#define	CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
#define	CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
#define	CAN_FS1R_FSC27_Pos (27U)
#define	CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
#define	CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
#define	CAN_FFA1R_FFA_Pos (0U)
#define	CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
#define	CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
#define	CAN_FFA1R_FFA0_Pos (0U)
#define	CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
#define	CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
#define	CAN_FFA1R_FFA1_Pos (1U)
#define	CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
#define	CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
#define	CAN_FFA1R_FFA2_Pos (2U)
#define	CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
#define	CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
#define	CAN_FFA1R_FFA3_Pos (3U)
#define	CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
#define	CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
#define	CAN_FFA1R_FFA4_Pos (4U)
#define	CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
#define	CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
#define	CAN_FFA1R_FFA5_Pos (5U)
#define	CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
#define	CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
#define	CAN_FFA1R_FFA6_Pos (6U)
#define	CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
#define	CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
#define	CAN_FFA1R_FFA7_Pos (7U)
#define	CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
#define	CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
#define	CAN_FFA1R_FFA8_Pos (8U)
#define	CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
#define	CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
#define	CAN_FFA1R_FFA9_Pos (9U)
#define	CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
#define	CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
#define	CAN_FFA1R_FFA10_Pos (10U)
#define	CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
#define	CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
#define	CAN_FFA1R_FFA11_Pos (11U)
#define	CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
#define	CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
#define	CAN_FFA1R_FFA12_Pos (12U)
#define	CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
#define	CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
#define	CAN_FFA1R_FFA13_Pos (13U)
#define	CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
#define	CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
#define	CAN_FFA1R_FFA14_Pos (14U)
#define	CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
#define	CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
#define	CAN_FFA1R_FFA15_Pos (15U)
#define	CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
#define	CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
#define	CAN_FFA1R_FFA16_Pos (16U)
#define	CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
#define	CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
#define	CAN_FFA1R_FFA17_Pos (17U)
#define	CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
#define	CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
#define	CAN_FFA1R_FFA18_Pos (18U)
#define	CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
#define	CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
#define	CAN_FFA1R_FFA19_Pos (19U)
#define	CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
#define	CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
#define	CAN_FFA1R_FFA20_Pos (20U)
#define	CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
#define	CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
#define	CAN_FFA1R_FFA21_Pos (21U)
#define	CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
#define	CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
#define	CAN_FFA1R_FFA22_Pos (22U)
#define	CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
#define	CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
#define	CAN_FFA1R_FFA23_Pos (23U)
#define	CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
#define	CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
#define	CAN_FFA1R_FFA24_Pos (24U)
#define	CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
#define	CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
#define	CAN_FFA1R_FFA25_Pos (25U)
#define	CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
#define	CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
#define	CAN_FFA1R_FFA26_Pos (26U)
#define	CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
#define	CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
#define	CAN_FFA1R_FFA27_Pos (27U)
#define	CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
#define	CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
#define	CAN_FA1R_FACT_Pos (0U)
#define	CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
#define	CAN_FA1R_FACT CAN_FA1R_FACT_Msk
#define	CAN_FA1R_FACT0_Pos (0U)
#define	CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
#define	CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
#define	CAN_FA1R_FACT1_Pos (1U)
#define	CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
#define	CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
#define	CAN_FA1R_FACT2_Pos (2U)
#define	CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
#define	CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
#define	CAN_FA1R_FACT3_Pos (3U)
#define	CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
#define	CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
#define	CAN_FA1R_FACT4_Pos (4U)
#define	CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
#define	CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
#define	CAN_FA1R_FACT5_Pos (5U)
#define	CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
#define	CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
#define	CAN_FA1R_FACT6_Pos (6U)
#define	CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
#define	CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
#define	CAN_FA1R_FACT7_Pos (7U)
#define	CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
#define	CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
#define	CAN_FA1R_FACT8_Pos (8U)
#define	CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
#define	CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
#define	CAN_FA1R_FACT9_Pos (9U)
#define	CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
#define	CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
#define	CAN_FA1R_FACT10_Pos (10U)
#define	CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
#define	CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
#define	CAN_FA1R_FACT11_Pos (11U)
#define	CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
#define	CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
#define	CAN_FA1R_FACT12_Pos (12U)
#define	CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
#define	CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
#define	CAN_FA1R_FACT13_Pos (13U)
#define	CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
#define	CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
#define	CAN_FA1R_FACT14_Pos (14U)
#define	CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
#define	CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
#define	CAN_FA1R_FACT15_Pos (15U)
#define	CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
#define	CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
#define	CAN_FA1R_FACT16_Pos (16U)
#define	CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
#define	CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
#define	CAN_FA1R_FACT17_Pos (17U)
#define	CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
#define	CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
#define	CAN_FA1R_FACT18_Pos (18U)
#define	CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
#define	CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
#define	CAN_FA1R_FACT19_Pos (19U)
#define	CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
#define	CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
#define	CAN_FA1R_FACT20_Pos (20U)
#define	CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
#define	CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
#define	CAN_FA1R_FACT21_Pos (21U)
#define	CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
#define	CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
#define	CAN_FA1R_FACT22_Pos (22U)
#define	CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
#define	CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
#define	CAN_FA1R_FACT23_Pos (23U)
#define	CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
#define	CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
#define	CAN_FA1R_FACT24_Pos (24U)
#define	CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
#define	CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
#define	CAN_FA1R_FACT25_Pos (25U)
#define	CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
#define	CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
#define	CAN_FA1R_FACT26_Pos (26U)
#define	CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
#define	CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
#define	CAN_FA1R_FACT27_Pos (27U)
#define	CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
#define	CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
#define	CAN_F0R1_FB0_Pos (0U)
#define	CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
#define	CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
#define	CAN_F0R1_FB1_Pos (1U)
#define	CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
#define	CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
#define	CAN_F0R1_FB2_Pos (2U)
#define	CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
#define	CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
#define	CAN_F0R1_FB3_Pos (3U)
#define	CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
#define	CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
#define	CAN_F0R1_FB4_Pos (4U)
#define	CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
#define	CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
#define	CAN_F0R1_FB5_Pos (5U)
#define	CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
#define	CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
#define	CAN_F0R1_FB6_Pos (6U)
#define	CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
#define	CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
#define	CAN_F0R1_FB7_Pos (7U)
#define	CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
#define	CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
#define	CAN_F0R1_FB8_Pos (8U)
#define	CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
#define	CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
#define	CAN_F0R1_FB9_Pos (9U)
#define	CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
#define	CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
#define	CAN_F0R1_FB10_Pos (10U)
#define	CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
#define	CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
#define	CAN_F0R1_FB11_Pos (11U)
#define	CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
#define	CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
#define	CAN_F0R1_FB12_Pos (12U)
#define	CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
#define	CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
#define	CAN_F0R1_FB13_Pos (13U)
#define	CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
#define	CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
#define	CAN_F0R1_FB14_Pos (14U)
#define	CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
#define	CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
#define	CAN_F0R1_FB15_Pos (15U)
#define	CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
#define	CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
#define	CAN_F0R1_FB16_Pos (16U)
#define	CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
#define	CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
#define	CAN_F0R1_FB17_Pos (17U)
#define	CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
#define	CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
#define	CAN_F0R1_FB18_Pos (18U)
#define	CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
#define	CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
#define	CAN_F0R1_FB19_Pos (19U)
#define	CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
#define	CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
#define	CAN_F0R1_FB20_Pos (20U)
#define	CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
#define	CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
#define	CAN_F0R1_FB21_Pos (21U)
#define	CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
#define	CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
#define	CAN_F0R1_FB22_Pos (22U)
#define	CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
#define	CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
#define	CAN_F0R1_FB23_Pos (23U)
#define	CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
#define	CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
#define	CAN_F0R1_FB24_Pos (24U)
#define	CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
#define	CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
#define	CAN_F0R1_FB25_Pos (25U)
#define	CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
#define	CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
#define	CAN_F0R1_FB26_Pos (26U)
#define	CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
#define	CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
#define	CAN_F0R1_FB27_Pos (27U)
#define	CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
#define	CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
#define	CAN_F0R1_FB28_Pos (28U)
#define	CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
#define	CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
#define	CAN_F0R1_FB29_Pos (29U)
#define	CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
#define	CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
#define	CAN_F0R1_FB30_Pos (30U)
#define	CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
#define	CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
#define	CAN_F0R1_FB31_Pos (31U)
#define	CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
#define	CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
#define	CAN_F1R1_FB0_Pos (0U)
#define	CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
#define	CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
#define	CAN_F1R1_FB1_Pos (1U)
#define	CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
#define	CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
#define	CAN_F1R1_FB2_Pos (2U)
#define	CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
#define	CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
#define	CAN_F1R1_FB3_Pos (3U)
#define	CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
#define	CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
#define	CAN_F1R1_FB4_Pos (4U)
#define	CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
#define	CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
#define	CAN_F1R1_FB5_Pos (5U)
#define	CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
#define	CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
#define	CAN_F1R1_FB6_Pos (6U)
#define	CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
#define	CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
#define	CAN_F1R1_FB7_Pos (7U)
#define	CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
#define	CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
#define	CAN_F1R1_FB8_Pos (8U)
#define	CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
#define	CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
#define	CAN_F1R1_FB9_Pos (9U)
#define	CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
#define	CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
#define	CAN_F1R1_FB10_Pos (10U)
#define	CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
#define	CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
#define	CAN_F1R1_FB11_Pos (11U)
#define	CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
#define	CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
#define	CAN_F1R1_FB12_Pos (12U)
#define	CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
#define	CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
#define	CAN_F1R1_FB13_Pos (13U)
#define	CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
#define	CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
#define	CAN_F1R1_FB14_Pos (14U)
#define	CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
#define	CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
#define	CAN_F1R1_FB15_Pos (15U)
#define	CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
#define	CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
#define	CAN_F1R1_FB16_Pos (16U)
#define	CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
#define	CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
#define	CAN_F1R1_FB17_Pos (17U)
#define	CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
#define	CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
#define	CAN_F1R1_FB18_Pos (18U)
#define	CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
#define	CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
#define	CAN_F1R1_FB19_Pos (19U)
#define	CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
#define	CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
#define	CAN_F1R1_FB20_Pos (20U)
#define	CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
#define	CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
#define	CAN_F1R1_FB21_Pos (21U)
#define	CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
#define	CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
#define	CAN_F1R1_FB22_Pos (22U)
#define	CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
#define	CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
#define	CAN_F1R1_FB23_Pos (23U)
#define	CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
#define	CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
#define	CAN_F1R1_FB24_Pos (24U)
#define	CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
#define	CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
#define	CAN_F1R1_FB25_Pos (25U)
#define	CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
#define	CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
#define	CAN_F1R1_FB26_Pos (26U)
#define	CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
#define	CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
#define	CAN_F1R1_FB27_Pos (27U)
#define	CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
#define	CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
#define	CAN_F1R1_FB28_Pos (28U)
#define	CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
#define	CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
#define	CAN_F1R1_FB29_Pos (29U)
#define	CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
#define	CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
#define	CAN_F1R1_FB30_Pos (30U)
#define	CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
#define	CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
#define	CAN_F1R1_FB31_Pos (31U)
#define	CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
#define	CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
#define	CAN_F2R1_FB0_Pos (0U)
#define	CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
#define	CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
#define	CAN_F2R1_FB1_Pos (1U)
#define	CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
#define	CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
#define	CAN_F2R1_FB2_Pos (2U)
#define	CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
#define	CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
#define	CAN_F2R1_FB3_Pos (3U)
#define	CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
#define	CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
#define	CAN_F2R1_FB4_Pos (4U)
#define	CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
#define	CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
#define	CAN_F2R1_FB5_Pos (5U)
#define	CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
#define	CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
#define	CAN_F2R1_FB6_Pos (6U)
#define	CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
#define	CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
#define	CAN_F2R1_FB7_Pos (7U)
#define	CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
#define	CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
#define	CAN_F2R1_FB8_Pos (8U)
#define	CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
#define	CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
#define	CAN_F2R1_FB9_Pos (9U)
#define	CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
#define	CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
#define	CAN_F2R1_FB10_Pos (10U)
#define	CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
#define	CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
#define	CAN_F2R1_FB11_Pos (11U)
#define	CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
#define	CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
#define	CAN_F2R1_FB12_Pos (12U)
#define	CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
#define	CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
#define	CAN_F2R1_FB13_Pos (13U)
#define	CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
#define	CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
#define	CAN_F2R1_FB14_Pos (14U)
#define	CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
#define	CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
#define	CAN_F2R1_FB15_Pos (15U)
#define	CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
#define	CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
#define	CAN_F2R1_FB16_Pos (16U)
#define	CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
#define	CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
#define	CAN_F2R1_FB17_Pos (17U)
#define	CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
#define	CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
#define	CAN_F2R1_FB18_Pos (18U)
#define	CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
#define	CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
#define	CAN_F2R1_FB19_Pos (19U)
#define	CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
#define	CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
#define	CAN_F2R1_FB20_Pos (20U)
#define	CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
#define	CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
#define	CAN_F2R1_FB21_Pos (21U)
#define	CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
#define	CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
#define	CAN_F2R1_FB22_Pos (22U)
#define	CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
#define	CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
#define	CAN_F2R1_FB23_Pos (23U)
#define	CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
#define	CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
#define	CAN_F2R1_FB24_Pos (24U)
#define	CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
#define	CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
#define	CAN_F2R1_FB25_Pos (25U)
#define	CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
#define	CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
#define	CAN_F2R1_FB26_Pos (26U)
#define	CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
#define	CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
#define	CAN_F2R1_FB27_Pos (27U)
#define	CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
#define	CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
#define	CAN_F2R1_FB28_Pos (28U)
#define	CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
#define	CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
#define	CAN_F2R1_FB29_Pos (29U)
#define	CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
#define	CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
#define	CAN_F2R1_FB30_Pos (30U)
#define	CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
#define	CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
#define	CAN_F2R1_FB31_Pos (31U)
#define	CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
#define	CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
#define	CAN_F3R1_FB0_Pos (0U)
#define	CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
#define	CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
#define	CAN_F3R1_FB1_Pos (1U)
#define	CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
#define	CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
#define	CAN_F3R1_FB2_Pos (2U)
#define	CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
#define	CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
#define	CAN_F3R1_FB3_Pos (3U)
#define	CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
#define	CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
#define	CAN_F3R1_FB4_Pos (4U)
#define	CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
#define	CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
#define	CAN_F3R1_FB5_Pos (5U)
#define	CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
#define	CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
#define	CAN_F3R1_FB6_Pos (6U)
#define	CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
#define	CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
#define	CAN_F3R1_FB7_Pos (7U)
#define	CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
#define	CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
#define	CAN_F3R1_FB8_Pos (8U)
#define	CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
#define	CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
#define	CAN_F3R1_FB9_Pos (9U)
#define	CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
#define	CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
#define	CAN_F3R1_FB10_Pos (10U)
#define	CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
#define	CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
#define	CAN_F3R1_FB11_Pos (11U)
#define	CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
#define	CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
#define	CAN_F3R1_FB12_Pos (12U)
#define	CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
#define	CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
#define	CAN_F3R1_FB13_Pos (13U)
#define	CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
#define	CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
#define	CAN_F3R1_FB14_Pos (14U)
#define	CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
#define	CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
#define	CAN_F3R1_FB15_Pos (15U)
#define	CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
#define	CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
#define	CAN_F3R1_FB16_Pos (16U)
#define	CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
#define	CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
#define	CAN_F3R1_FB17_Pos (17U)
#define	CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
#define	CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
#define	CAN_F3R1_FB18_Pos (18U)
#define	CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
#define	CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
#define	CAN_F3R1_FB19_Pos (19U)
#define	CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
#define	CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
#define	CAN_F3R1_FB20_Pos (20U)
#define	CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
#define	CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
#define	CAN_F3R1_FB21_Pos (21U)
#define	CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
#define	CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
#define	CAN_F3R1_FB22_Pos (22U)
#define	CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
#define	CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
#define	CAN_F3R1_FB23_Pos (23U)
#define	CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
#define	CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
#define	CAN_F3R1_FB24_Pos (24U)
#define	CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
#define	CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
#define	CAN_F3R1_FB25_Pos (25U)
#define	CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
#define	CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
#define	CAN_F3R1_FB26_Pos (26U)
#define	CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
#define	CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
#define	CAN_F3R1_FB27_Pos (27U)
#define	CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
#define	CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
#define	CAN_F3R1_FB28_Pos (28U)
#define	CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
#define	CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
#define	CAN_F3R1_FB29_Pos (29U)
#define	CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
#define	CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
#define	CAN_F3R1_FB30_Pos (30U)
#define	CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
#define	CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
#define	CAN_F3R1_FB31_Pos (31U)
#define	CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
#define	CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
#define	CAN_F4R1_FB0_Pos (0U)
#define	CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
#define	CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
#define	CAN_F4R1_FB1_Pos (1U)
#define	CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
#define	CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
#define	CAN_F4R1_FB2_Pos (2U)
#define	CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
#define	CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
#define	CAN_F4R1_FB3_Pos (3U)
#define	CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
#define	CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
#define	CAN_F4R1_FB4_Pos (4U)
#define	CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
#define	CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
#define	CAN_F4R1_FB5_Pos (5U)
#define	CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
#define	CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
#define	CAN_F4R1_FB6_Pos (6U)
#define	CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
#define	CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
#define	CAN_F4R1_FB7_Pos (7U)
#define	CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
#define	CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
#define	CAN_F4R1_FB8_Pos (8U)
#define	CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
#define	CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
#define	CAN_F4R1_FB9_Pos (9U)
#define	CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
#define	CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
#define	CAN_F4R1_FB10_Pos (10U)
#define	CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
#define	CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
#define	CAN_F4R1_FB11_Pos (11U)
#define	CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
#define	CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
#define	CAN_F4R1_FB12_Pos (12U)
#define	CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
#define	CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
#define	CAN_F4R1_FB13_Pos (13U)
#define	CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
#define	CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
#define	CAN_F4R1_FB14_Pos (14U)
#define	CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
#define	CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
#define	CAN_F4R1_FB15_Pos (15U)
#define	CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
#define	CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
#define	CAN_F4R1_FB16_Pos (16U)
#define	CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
#define	CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
#define	CAN_F4R1_FB17_Pos (17U)
#define	CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
#define	CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
#define	CAN_F4R1_FB18_Pos (18U)
#define	CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
#define	CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
#define	CAN_F4R1_FB19_Pos (19U)
#define	CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
#define	CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
#define	CAN_F4R1_FB20_Pos (20U)
#define	CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
#define	CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
#define	CAN_F4R1_FB21_Pos (21U)
#define	CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
#define	CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
#define	CAN_F4R1_FB22_Pos (22U)
#define	CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
#define	CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
#define	CAN_F4R1_FB23_Pos (23U)
#define	CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
#define	CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
#define	CAN_F4R1_FB24_Pos (24U)
#define	CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
#define	CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
#define	CAN_F4R1_FB25_Pos (25U)
#define	CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
#define	CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
#define	CAN_F4R1_FB26_Pos (26U)
#define	CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
#define	CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
#define	CAN_F4R1_FB27_Pos (27U)
#define	CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
#define	CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
#define	CAN_F4R1_FB28_Pos (28U)
#define	CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
#define	CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
#define	CAN_F4R1_FB29_Pos (29U)
#define	CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
#define	CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
#define	CAN_F4R1_FB30_Pos (30U)
#define	CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
#define	CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
#define	CAN_F4R1_FB31_Pos (31U)
#define	CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
#define	CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
#define	CAN_F5R1_FB0_Pos (0U)
#define	CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
#define	CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
#define	CAN_F5R1_FB1_Pos (1U)
#define	CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
#define	CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
#define	CAN_F5R1_FB2_Pos (2U)
#define	CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
#define	CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
#define	CAN_F5R1_FB3_Pos (3U)
#define	CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
#define	CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
#define	CAN_F5R1_FB4_Pos (4U)
#define	CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
#define	CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
#define	CAN_F5R1_FB5_Pos (5U)
#define	CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
#define	CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
#define	CAN_F5R1_FB6_Pos (6U)
#define	CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
#define	CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
#define	CAN_F5R1_FB7_Pos (7U)
#define	CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
#define	CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
#define	CAN_F5R1_FB8_Pos (8U)
#define	CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
#define	CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
#define	CAN_F5R1_FB9_Pos (9U)
#define	CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
#define	CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
#define	CAN_F5R1_FB10_Pos (10U)
#define	CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
#define	CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
#define	CAN_F5R1_FB11_Pos (11U)
#define	CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
#define	CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
#define	CAN_F5R1_FB12_Pos (12U)
#define	CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
#define	CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
#define	CAN_F5R1_FB13_Pos (13U)
#define	CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
#define	CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
#define	CAN_F5R1_FB14_Pos (14U)
#define	CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
#define	CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
#define	CAN_F5R1_FB15_Pos (15U)
#define	CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
#define	CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
#define	CAN_F5R1_FB16_Pos (16U)
#define	CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
#define	CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
#define	CAN_F5R1_FB17_Pos (17U)
#define	CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
#define	CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
#define	CAN_F5R1_FB18_Pos (18U)
#define	CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
#define	CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
#define	CAN_F5R1_FB19_Pos (19U)
#define	CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
#define	CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
#define	CAN_F5R1_FB20_Pos (20U)
#define	CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
#define	CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
#define	CAN_F5R1_FB21_Pos (21U)
#define	CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
#define	CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
#define	CAN_F5R1_FB22_Pos (22U)
#define	CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
#define	CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
#define	CAN_F5R1_FB23_Pos (23U)
#define	CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
#define	CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
#define	CAN_F5R1_FB24_Pos (24U)
#define	CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
#define	CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
#define	CAN_F5R1_FB25_Pos (25U)
#define	CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
#define	CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
#define	CAN_F5R1_FB26_Pos (26U)
#define	CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
#define	CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
#define	CAN_F5R1_FB27_Pos (27U)
#define	CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
#define	CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
#define	CAN_F5R1_FB28_Pos (28U)
#define	CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
#define	CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
#define	CAN_F5R1_FB29_Pos (29U)
#define	CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
#define	CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
#define	CAN_F5R1_FB30_Pos (30U)
#define	CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
#define	CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
#define	CAN_F5R1_FB31_Pos (31U)
#define	CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
#define	CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
#define	CAN_F6R1_FB0_Pos (0U)
#define	CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
#define	CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
#define	CAN_F6R1_FB1_Pos (1U)
#define	CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
#define	CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
#define	CAN_F6R1_FB2_Pos (2U)
#define	CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
#define	CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
#define	CAN_F6R1_FB3_Pos (3U)
#define	CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
#define	CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
#define	CAN_F6R1_FB4_Pos (4U)
#define	CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
#define	CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
#define	CAN_F6R1_FB5_Pos (5U)
#define	CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
#define	CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
#define	CAN_F6R1_FB6_Pos (6U)
#define	CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
#define	CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
#define	CAN_F6R1_FB7_Pos (7U)
#define	CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
#define	CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
#define	CAN_F6R1_FB8_Pos (8U)
#define	CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
#define	CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
#define	CAN_F6R1_FB9_Pos (9U)
#define	CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
#define	CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
#define	CAN_F6R1_FB10_Pos (10U)
#define	CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
#define	CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
#define	CAN_F6R1_FB11_Pos (11U)
#define	CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
#define	CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
#define	CAN_F6R1_FB12_Pos (12U)
#define	CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
#define	CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
#define	CAN_F6R1_FB13_Pos (13U)
#define	CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
#define	CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
#define	CAN_F6R1_FB14_Pos (14U)
#define	CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
#define	CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
#define	CAN_F6R1_FB15_Pos (15U)
#define	CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
#define	CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
#define	CAN_F6R1_FB16_Pos (16U)
#define	CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
#define	CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
#define	CAN_F6R1_FB17_Pos (17U)
#define	CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
#define	CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
#define	CAN_F6R1_FB18_Pos (18U)
#define	CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
#define	CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
#define	CAN_F6R1_FB19_Pos (19U)
#define	CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
#define	CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
#define	CAN_F6R1_FB20_Pos (20U)
#define	CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
#define	CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
#define	CAN_F6R1_FB21_Pos (21U)
#define	CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
#define	CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
#define	CAN_F6R1_FB22_Pos (22U)
#define	CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
#define	CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
#define	CAN_F6R1_FB23_Pos (23U)
#define	CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
#define	CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
#define	CAN_F6R1_FB24_Pos (24U)
#define	CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
#define	CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
#define	CAN_F6R1_FB25_Pos (25U)
#define	CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
#define	CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
#define	CAN_F6R1_FB26_Pos (26U)
#define	CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
#define	CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
#define	CAN_F6R1_FB27_Pos (27U)
#define	CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
#define	CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
#define	CAN_F6R1_FB28_Pos (28U)
#define	CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
#define	CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
#define	CAN_F6R1_FB29_Pos (29U)
#define	CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
#define	CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
#define	CAN_F6R1_FB30_Pos (30U)
#define	CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
#define	CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
#define	CAN_F6R1_FB31_Pos (31U)
#define	CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
#define	CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
#define	CAN_F7R1_FB0_Pos (0U)
#define	CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
#define	CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
#define	CAN_F7R1_FB1_Pos (1U)
#define	CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
#define	CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
#define	CAN_F7R1_FB2_Pos (2U)
#define	CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
#define	CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
#define	CAN_F7R1_FB3_Pos (3U)
#define	CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
#define	CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
#define	CAN_F7R1_FB4_Pos (4U)
#define	CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
#define	CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
#define	CAN_F7R1_FB5_Pos (5U)
#define	CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
#define	CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
#define	CAN_F7R1_FB6_Pos (6U)
#define	CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
#define	CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
#define	CAN_F7R1_FB7_Pos (7U)
#define	CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
#define	CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
#define	CAN_F7R1_FB8_Pos (8U)
#define	CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
#define	CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
#define	CAN_F7R1_FB9_Pos (9U)
#define	CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
#define	CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
#define	CAN_F7R1_FB10_Pos (10U)
#define	CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
#define	CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
#define	CAN_F7R1_FB11_Pos (11U)
#define	CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
#define	CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
#define	CAN_F7R1_FB12_Pos (12U)
#define	CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
#define	CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
#define	CAN_F7R1_FB13_Pos (13U)
#define	CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
#define	CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
#define	CAN_F7R1_FB14_Pos (14U)
#define	CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
#define	CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
#define	CAN_F7R1_FB15_Pos (15U)
#define	CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
#define	CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
#define	CAN_F7R1_FB16_Pos (16U)
#define	CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
#define	CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
#define	CAN_F7R1_FB17_Pos (17U)
#define	CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
#define	CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
#define	CAN_F7R1_FB18_Pos (18U)
#define	CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
#define	CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
#define	CAN_F7R1_FB19_Pos (19U)
#define	CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
#define	CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
#define	CAN_F7R1_FB20_Pos (20U)
#define	CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
#define	CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
#define	CAN_F7R1_FB21_Pos (21U)
#define	CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
#define	CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
#define	CAN_F7R1_FB22_Pos (22U)
#define	CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
#define	CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
#define	CAN_F7R1_FB23_Pos (23U)
#define	CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
#define	CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
#define	CAN_F7R1_FB24_Pos (24U)
#define	CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
#define	CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
#define	CAN_F7R1_FB25_Pos (25U)
#define	CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
#define	CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
#define	CAN_F7R1_FB26_Pos (26U)
#define	CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
#define	CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
#define	CAN_F7R1_FB27_Pos (27U)
#define	CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
#define	CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
#define	CAN_F7R1_FB28_Pos (28U)
#define	CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
#define	CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
#define	CAN_F7R1_FB29_Pos (29U)
#define	CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
#define	CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
#define	CAN_F7R1_FB30_Pos (30U)
#define	CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
#define	CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
#define	CAN_F7R1_FB31_Pos (31U)
#define	CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
#define	CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
#define	CAN_F8R1_FB0_Pos (0U)
#define	CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
#define	CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
#define	CAN_F8R1_FB1_Pos (1U)
#define	CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
#define	CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
#define	CAN_F8R1_FB2_Pos (2U)
#define	CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
#define	CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
#define	CAN_F8R1_FB3_Pos (3U)
#define	CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
#define	CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
#define	CAN_F8R1_FB4_Pos (4U)
#define	CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
#define	CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
#define	CAN_F8R1_FB5_Pos (5U)
#define	CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
#define	CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
#define	CAN_F8R1_FB6_Pos (6U)
#define	CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
#define	CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
#define	CAN_F8R1_FB7_Pos (7U)
#define	CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
#define	CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
#define	CAN_F8R1_FB8_Pos (8U)
#define	CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
#define	CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
#define	CAN_F8R1_FB9_Pos (9U)
#define	CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
#define	CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
#define	CAN_F8R1_FB10_Pos (10U)
#define	CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
#define	CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
#define	CAN_F8R1_FB11_Pos (11U)
#define	CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
#define	CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
#define	CAN_F8R1_FB12_Pos (12U)
#define	CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
#define	CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
#define	CAN_F8R1_FB13_Pos (13U)
#define	CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
#define	CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
#define	CAN_F8R1_FB14_Pos (14U)
#define	CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
#define	CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
#define	CAN_F8R1_FB15_Pos (15U)
#define	CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
#define	CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
#define	CAN_F8R1_FB16_Pos (16U)
#define	CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
#define	CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
#define	CAN_F8R1_FB17_Pos (17U)
#define	CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
#define	CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
#define	CAN_F8R1_FB18_Pos (18U)
#define	CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
#define	CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
#define	CAN_F8R1_FB19_Pos (19U)
#define	CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
#define	CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
#define	CAN_F8R1_FB20_Pos (20U)
#define	CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
#define	CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
#define	CAN_F8R1_FB21_Pos (21U)
#define	CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
#define	CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
#define	CAN_F8R1_FB22_Pos (22U)
#define	CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
#define	CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
#define	CAN_F8R1_FB23_Pos (23U)
#define	CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
#define	CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
#define	CAN_F8R1_FB24_Pos (24U)
#define	CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
#define	CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
#define	CAN_F8R1_FB25_Pos (25U)
#define	CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
#define	CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
#define	CAN_F8R1_FB26_Pos (26U)
#define	CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
#define	CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
#define	CAN_F8R1_FB27_Pos (27U)
#define	CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
#define	CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
#define	CAN_F8R1_FB28_Pos (28U)
#define	CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
#define	CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
#define	CAN_F8R1_FB29_Pos (29U)
#define	CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
#define	CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
#define	CAN_F8R1_FB30_Pos (30U)
#define	CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
#define	CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
#define	CAN_F8R1_FB31_Pos (31U)
#define	CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
#define	CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
#define	CAN_F9R1_FB0_Pos (0U)
#define	CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
#define	CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
#define	CAN_F9R1_FB1_Pos (1U)
#define	CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
#define	CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
#define	CAN_F9R1_FB2_Pos (2U)
#define	CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
#define	CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
#define	CAN_F9R1_FB3_Pos (3U)
#define	CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
#define	CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
#define	CAN_F9R1_FB4_Pos (4U)
#define	CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
#define	CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
#define	CAN_F9R1_FB5_Pos (5U)
#define	CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
#define	CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
#define	CAN_F9R1_FB6_Pos (6U)
#define	CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
#define	CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
#define	CAN_F9R1_FB7_Pos (7U)
#define	CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
#define	CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
#define	CAN_F9R1_FB8_Pos (8U)
#define	CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
#define	CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
#define	CAN_F9R1_FB9_Pos (9U)
#define	CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
#define	CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
#define	CAN_F9R1_FB10_Pos (10U)
#define	CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
#define	CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
#define	CAN_F9R1_FB11_Pos (11U)
#define	CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
#define	CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
#define	CAN_F9R1_FB12_Pos (12U)
#define	CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
#define	CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
#define	CAN_F9R1_FB13_Pos (13U)
#define	CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
#define	CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
#define	CAN_F9R1_FB14_Pos (14U)
#define	CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
#define	CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
#define	CAN_F9R1_FB15_Pos (15U)
#define	CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
#define	CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
#define	CAN_F9R1_FB16_Pos (16U)
#define	CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
#define	CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
#define	CAN_F9R1_FB17_Pos (17U)
#define	CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
#define	CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
#define	CAN_F9R1_FB18_Pos (18U)
#define	CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
#define	CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
#define	CAN_F9R1_FB19_Pos (19U)
#define	CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
#define	CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
#define	CAN_F9R1_FB20_Pos (20U)
#define	CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
#define	CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
#define	CAN_F9R1_FB21_Pos (21U)
#define	CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
#define	CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
#define	CAN_F9R1_FB22_Pos (22U)
#define	CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
#define	CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
#define	CAN_F9R1_FB23_Pos (23U)
#define	CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
#define	CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
#define	CAN_F9R1_FB24_Pos (24U)
#define	CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
#define	CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
#define	CAN_F9R1_FB25_Pos (25U)
#define	CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
#define	CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
#define	CAN_F9R1_FB26_Pos (26U)
#define	CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
#define	CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
#define	CAN_F9R1_FB27_Pos (27U)
#define	CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
#define	CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
#define	CAN_F9R1_FB28_Pos (28U)
#define	CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
#define	CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
#define	CAN_F9R1_FB29_Pos (29U)
#define	CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
#define	CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
#define	CAN_F9R1_FB30_Pos (30U)
#define	CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
#define	CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
#define	CAN_F9R1_FB31_Pos (31U)
#define	CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
#define	CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
#define	CAN_F10R1_FB0_Pos (0U)
#define	CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
#define	CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
#define	CAN_F10R1_FB1_Pos (1U)
#define	CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
#define	CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
#define	CAN_F10R1_FB2_Pos (2U)
#define	CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
#define	CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
#define	CAN_F10R1_FB3_Pos (3U)
#define	CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
#define	CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
#define	CAN_F10R1_FB4_Pos (4U)
#define	CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
#define	CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
#define	CAN_F10R1_FB5_Pos (5U)
#define	CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
#define	CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
#define	CAN_F10R1_FB6_Pos (6U)
#define	CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
#define	CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
#define	CAN_F10R1_FB7_Pos (7U)
#define	CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
#define	CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
#define	CAN_F10R1_FB8_Pos (8U)
#define	CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
#define	CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
#define	CAN_F10R1_FB9_Pos (9U)
#define	CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
#define	CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
#define	CAN_F10R1_FB10_Pos (10U)
#define	CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
#define	CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
#define	CAN_F10R1_FB11_Pos (11U)
#define	CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
#define	CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
#define	CAN_F10R1_FB12_Pos (12U)
#define	CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
#define	CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
#define	CAN_F10R1_FB13_Pos (13U)
#define	CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
#define	CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
#define	CAN_F10R1_FB14_Pos (14U)
#define	CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
#define	CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
#define	CAN_F10R1_FB15_Pos (15U)
#define	CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
#define	CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
#define	CAN_F10R1_FB16_Pos (16U)
#define	CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
#define	CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
#define	CAN_F10R1_FB17_Pos (17U)
#define	CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
#define	CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
#define	CAN_F10R1_FB18_Pos (18U)
#define	CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
#define	CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
#define	CAN_F10R1_FB19_Pos (19U)
#define	CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
#define	CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
#define	CAN_F10R1_FB20_Pos (20U)
#define	CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
#define	CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
#define	CAN_F10R1_FB21_Pos (21U)
#define	CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
#define	CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
#define	CAN_F10R1_FB22_Pos (22U)
#define	CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
#define	CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
#define	CAN_F10R1_FB23_Pos (23U)
#define	CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
#define	CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
#define	CAN_F10R1_FB24_Pos (24U)
#define	CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
#define	CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
#define	CAN_F10R1_FB25_Pos (25U)
#define	CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
#define	CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
#define	CAN_F10R1_FB26_Pos (26U)
#define	CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
#define	CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
#define	CAN_F10R1_FB27_Pos (27U)
#define	CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
#define	CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
#define	CAN_F10R1_FB28_Pos (28U)
#define	CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
#define	CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
#define	CAN_F10R1_FB29_Pos (29U)
#define	CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
#define	CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
#define	CAN_F10R1_FB30_Pos (30U)
#define	CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
#define	CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
#define	CAN_F10R1_FB31_Pos (31U)
#define	CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
#define	CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
#define	CAN_F11R1_FB0_Pos (0U)
#define	CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
#define	CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
#define	CAN_F11R1_FB1_Pos (1U)
#define	CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
#define	CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
#define	CAN_F11R1_FB2_Pos (2U)
#define	CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
#define	CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
#define	CAN_F11R1_FB3_Pos (3U)
#define	CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
#define	CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
#define	CAN_F11R1_FB4_Pos (4U)
#define	CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
#define	CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
#define	CAN_F11R1_FB5_Pos (5U)
#define	CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
#define	CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
#define	CAN_F11R1_FB6_Pos (6U)
#define	CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
#define	CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
#define	CAN_F11R1_FB7_Pos (7U)
#define	CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
#define	CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
#define	CAN_F11R1_FB8_Pos (8U)
#define	CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
#define	CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
#define	CAN_F11R1_FB9_Pos (9U)
#define	CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
#define	CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
#define	CAN_F11R1_FB10_Pos (10U)
#define	CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
#define	CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
#define	CAN_F11R1_FB11_Pos (11U)
#define	CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
#define	CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
#define	CAN_F11R1_FB12_Pos (12U)
#define	CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
#define	CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
#define	CAN_F11R1_FB13_Pos (13U)
#define	CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
#define	CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
#define	CAN_F11R1_FB14_Pos (14U)
#define	CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
#define	CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
#define	CAN_F11R1_FB15_Pos (15U)
#define	CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
#define	CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
#define	CAN_F11R1_FB16_Pos (16U)
#define	CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
#define	CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
#define	CAN_F11R1_FB17_Pos (17U)
#define	CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
#define	CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
#define	CAN_F11R1_FB18_Pos (18U)
#define	CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
#define	CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
#define	CAN_F11R1_FB19_Pos (19U)
#define	CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
#define	CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
#define	CAN_F11R1_FB20_Pos (20U)
#define	CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
#define	CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
#define	CAN_F11R1_FB21_Pos (21U)
#define	CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
#define	CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
#define	CAN_F11R1_FB22_Pos (22U)
#define	CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
#define	CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
#define	CAN_F11R1_FB23_Pos (23U)
#define	CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
#define	CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
#define	CAN_F11R1_FB24_Pos (24U)
#define	CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
#define	CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
#define	CAN_F11R1_FB25_Pos (25U)
#define	CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
#define	CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
#define	CAN_F11R1_FB26_Pos (26U)
#define	CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
#define	CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
#define	CAN_F11R1_FB27_Pos (27U)
#define	CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
#define	CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
#define	CAN_F11R1_FB28_Pos (28U)
#define	CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
#define	CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
#define	CAN_F11R1_FB29_Pos (29U)
#define	CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
#define	CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
#define	CAN_F11R1_FB30_Pos (30U)
#define	CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
#define	CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
#define	CAN_F11R1_FB31_Pos (31U)
#define	CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
#define	CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
#define	CAN_F12R1_FB0_Pos (0U)
#define	CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
#define	CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
#define	CAN_F12R1_FB1_Pos (1U)
#define	CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
#define	CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
#define	CAN_F12R1_FB2_Pos (2U)
#define	CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
#define	CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
#define	CAN_F12R1_FB3_Pos (3U)
#define	CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
#define	CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
#define	CAN_F12R1_FB4_Pos (4U)
#define	CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
#define	CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
#define	CAN_F12R1_FB5_Pos (5U)
#define	CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
#define	CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
#define	CAN_F12R1_FB6_Pos (6U)
#define	CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
#define	CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
#define	CAN_F12R1_FB7_Pos (7U)
#define	CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
#define	CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
#define	CAN_F12R1_FB8_Pos (8U)
#define	CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
#define	CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
#define	CAN_F12R1_FB9_Pos (9U)
#define	CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
#define	CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
#define	CAN_F12R1_FB10_Pos (10U)
#define	CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
#define	CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
#define	CAN_F12R1_FB11_Pos (11U)
#define	CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
#define	CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
#define	CAN_F12R1_FB12_Pos (12U)
#define	CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
#define	CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
#define	CAN_F12R1_FB13_Pos (13U)
#define	CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
#define	CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
#define	CAN_F12R1_FB14_Pos (14U)
#define	CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
#define	CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
#define	CAN_F12R1_FB15_Pos (15U)
#define	CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
#define	CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
#define	CAN_F12R1_FB16_Pos (16U)
#define	CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
#define	CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
#define	CAN_F12R1_FB17_Pos (17U)
#define	CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
#define	CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
#define	CAN_F12R1_FB18_Pos (18U)
#define	CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
#define	CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
#define	CAN_F12R1_FB19_Pos (19U)
#define	CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
#define	CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
#define	CAN_F12R1_FB20_Pos (20U)
#define	CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
#define	CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
#define	CAN_F12R1_FB21_Pos (21U)
#define	CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
#define	CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
#define	CAN_F12R1_FB22_Pos (22U)
#define	CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
#define	CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
#define	CAN_F12R1_FB23_Pos (23U)
#define	CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
#define	CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
#define	CAN_F12R1_FB24_Pos (24U)
#define	CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
#define	CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
#define	CAN_F12R1_FB25_Pos (25U)
#define	CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
#define	CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
#define	CAN_F12R1_FB26_Pos (26U)
#define	CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
#define	CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
#define	CAN_F12R1_FB27_Pos (27U)
#define	CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
#define	CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
#define	CAN_F12R1_FB28_Pos (28U)
#define	CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
#define	CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
#define	CAN_F12R1_FB29_Pos (29U)
#define	CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
#define	CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
#define	CAN_F12R1_FB30_Pos (30U)
#define	CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
#define	CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
#define	CAN_F12R1_FB31_Pos (31U)
#define	CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
#define	CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
#define	CAN_F13R1_FB0_Pos (0U)
#define	CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
#define	CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
#define	CAN_F13R1_FB1_Pos (1U)
#define	CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
#define	CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
#define	CAN_F13R1_FB2_Pos (2U)
#define	CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
#define	CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
#define	CAN_F13R1_FB3_Pos (3U)
#define	CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
#define	CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
#define	CAN_F13R1_FB4_Pos (4U)
#define	CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
#define	CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
#define	CAN_F13R1_FB5_Pos (5U)
#define	CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
#define	CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
#define	CAN_F13R1_FB6_Pos (6U)
#define	CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
#define	CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
#define	CAN_F13R1_FB7_Pos (7U)
#define	CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
#define	CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
#define	CAN_F13R1_FB8_Pos (8U)
#define	CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
#define	CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
#define	CAN_F13R1_FB9_Pos (9U)
#define	CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
#define	CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
#define	CAN_F13R1_FB10_Pos (10U)
#define	CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
#define	CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
#define	CAN_F13R1_FB11_Pos (11U)
#define	CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
#define	CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
#define	CAN_F13R1_FB12_Pos (12U)
#define	CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
#define	CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
#define	CAN_F13R1_FB13_Pos (13U)
#define	CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
#define	CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
#define	CAN_F13R1_FB14_Pos (14U)
#define	CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
#define	CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
#define	CAN_F13R1_FB15_Pos (15U)
#define	CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
#define	CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
#define	CAN_F13R1_FB16_Pos (16U)
#define	CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
#define	CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
#define	CAN_F13R1_FB17_Pos (17U)
#define	CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
#define	CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
#define	CAN_F13R1_FB18_Pos (18U)
#define	CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
#define	CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
#define	CAN_F13R1_FB19_Pos (19U)
#define	CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
#define	CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
#define	CAN_F13R1_FB20_Pos (20U)
#define	CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
#define	CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
#define	CAN_F13R1_FB21_Pos (21U)
#define	CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
#define	CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
#define	CAN_F13R1_FB22_Pos (22U)
#define	CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
#define	CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
#define	CAN_F13R1_FB23_Pos (23U)
#define	CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
#define	CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
#define	CAN_F13R1_FB24_Pos (24U)
#define	CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
#define	CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
#define	CAN_F13R1_FB25_Pos (25U)
#define	CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
#define	CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
#define	CAN_F13R1_FB26_Pos (26U)
#define	CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
#define	CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
#define	CAN_F13R1_FB27_Pos (27U)
#define	CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
#define	CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
#define	CAN_F13R1_FB28_Pos (28U)
#define	CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
#define	CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
#define	CAN_F13R1_FB29_Pos (29U)
#define	CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
#define	CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
#define	CAN_F13R1_FB30_Pos (30U)
#define	CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
#define	CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
#define	CAN_F13R1_FB31_Pos (31U)
#define	CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
#define	CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
#define	CAN_F0R2_FB0_Pos (0U)
#define	CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
#define	CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
#define	CAN_F0R2_FB1_Pos (1U)
#define	CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
#define	CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
#define	CAN_F0R2_FB2_Pos (2U)
#define	CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
#define	CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
#define	CAN_F0R2_FB3_Pos (3U)
#define	CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
#define	CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
#define	CAN_F0R2_FB4_Pos (4U)
#define	CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
#define	CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
#define	CAN_F0R2_FB5_Pos (5U)
#define	CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
#define	CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
#define	CAN_F0R2_FB6_Pos (6U)
#define	CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
#define	CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
#define	CAN_F0R2_FB7_Pos (7U)
#define	CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
#define	CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
#define	CAN_F0R2_FB8_Pos (8U)
#define	CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
#define	CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
#define	CAN_F0R2_FB9_Pos (9U)
#define	CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
#define	CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
#define	CAN_F0R2_FB10_Pos (10U)
#define	CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
#define	CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
#define	CAN_F0R2_FB11_Pos (11U)
#define	CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
#define	CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
#define	CAN_F0R2_FB12_Pos (12U)
#define	CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
#define	CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
#define	CAN_F0R2_FB13_Pos (13U)
#define	CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
#define	CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
#define	CAN_F0R2_FB14_Pos (14U)
#define	CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
#define	CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
#define	CAN_F0R2_FB15_Pos (15U)
#define	CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
#define	CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
#define	CAN_F0R2_FB16_Pos (16U)
#define	CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
#define	CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
#define	CAN_F0R2_FB17_Pos (17U)
#define	CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
#define	CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
#define	CAN_F0R2_FB18_Pos (18U)
#define	CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
#define	CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
#define	CAN_F0R2_FB19_Pos (19U)
#define	CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
#define	CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
#define	CAN_F0R2_FB20_Pos (20U)
#define	CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
#define	CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
#define	CAN_F0R2_FB21_Pos (21U)
#define	CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
#define	CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
#define	CAN_F0R2_FB22_Pos (22U)
#define	CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
#define	CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
#define	CAN_F0R2_FB23_Pos (23U)
#define	CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
#define	CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
#define	CAN_F0R2_FB24_Pos (24U)
#define	CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
#define	CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
#define	CAN_F0R2_FB25_Pos (25U)
#define	CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
#define	CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
#define	CAN_F0R2_FB26_Pos (26U)
#define	CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
#define	CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
#define	CAN_F0R2_FB27_Pos (27U)
#define	CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
#define	CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
#define	CAN_F0R2_FB28_Pos (28U)
#define	CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
#define	CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
#define	CAN_F0R2_FB29_Pos (29U)
#define	CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
#define	CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
#define	CAN_F0R2_FB30_Pos (30U)
#define	CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
#define	CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
#define	CAN_F0R2_FB31_Pos (31U)
#define	CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
#define	CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
#define	CAN_F1R2_FB0_Pos (0U)
#define	CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
#define	CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
#define	CAN_F1R2_FB1_Pos (1U)
#define	CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
#define	CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
#define	CAN_F1R2_FB2_Pos (2U)
#define	CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
#define	CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
#define	CAN_F1R2_FB3_Pos (3U)
#define	CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
#define	CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
#define	CAN_F1R2_FB4_Pos (4U)
#define	CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
#define	CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
#define	CAN_F1R2_FB5_Pos (5U)
#define	CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
#define	CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
#define	CAN_F1R2_FB6_Pos (6U)
#define	CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
#define	CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
#define	CAN_F1R2_FB7_Pos (7U)
#define	CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
#define	CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
#define	CAN_F1R2_FB8_Pos (8U)
#define	CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
#define	CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
#define	CAN_F1R2_FB9_Pos (9U)
#define	CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
#define	CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
#define	CAN_F1R2_FB10_Pos (10U)
#define	CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
#define	CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
#define	CAN_F1R2_FB11_Pos (11U)
#define	CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
#define	CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
#define	CAN_F1R2_FB12_Pos (12U)
#define	CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
#define	CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
#define	CAN_F1R2_FB13_Pos (13U)
#define	CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
#define	CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
#define	CAN_F1R2_FB14_Pos (14U)
#define	CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
#define	CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
#define	CAN_F1R2_FB15_Pos (15U)
#define	CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
#define	CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
#define	CAN_F1R2_FB16_Pos (16U)
#define	CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
#define	CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
#define	CAN_F1R2_FB17_Pos (17U)
#define	CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
#define	CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
#define	CAN_F1R2_FB18_Pos (18U)
#define	CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
#define	CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
#define	CAN_F1R2_FB19_Pos (19U)
#define	CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
#define	CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
#define	CAN_F1R2_FB20_Pos (20U)
#define	CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
#define	CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
#define	CAN_F1R2_FB21_Pos (21U)
#define	CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
#define	CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
#define	CAN_F1R2_FB22_Pos (22U)
#define	CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
#define	CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
#define	CAN_F1R2_FB23_Pos (23U)
#define	CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
#define	CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
#define	CAN_F1R2_FB24_Pos (24U)
#define	CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
#define	CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
#define	CAN_F1R2_FB25_Pos (25U)
#define	CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
#define	CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
#define	CAN_F1R2_FB26_Pos (26U)
#define	CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
#define	CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
#define	CAN_F1R2_FB27_Pos (27U)
#define	CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
#define	CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
#define	CAN_F1R2_FB28_Pos (28U)
#define	CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
#define	CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
#define	CAN_F1R2_FB29_Pos (29U)
#define	CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
#define	CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
#define	CAN_F1R2_FB30_Pos (30U)
#define	CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
#define	CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
#define	CAN_F1R2_FB31_Pos (31U)
#define	CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
#define	CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
#define	CAN_F2R2_FB0_Pos (0U)
#define	CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
#define	CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
#define	CAN_F2R2_FB1_Pos (1U)
#define	CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
#define	CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
#define	CAN_F2R2_FB2_Pos (2U)
#define	CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
#define	CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
#define	CAN_F2R2_FB3_Pos (3U)
#define	CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
#define	CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
#define	CAN_F2R2_FB4_Pos (4U)
#define	CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
#define	CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
#define	CAN_F2R2_FB5_Pos (5U)
#define	CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
#define	CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
#define	CAN_F2R2_FB6_Pos (6U)
#define	CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
#define	CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
#define	CAN_F2R2_FB7_Pos (7U)
#define	CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
#define	CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
#define	CAN_F2R2_FB8_Pos (8U)
#define	CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
#define	CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
#define	CAN_F2R2_FB9_Pos (9U)
#define	CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
#define	CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
#define	CAN_F2R2_FB10_Pos (10U)
#define	CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
#define	CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
#define	CAN_F2R2_FB11_Pos (11U)
#define	CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
#define	CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
#define	CAN_F2R2_FB12_Pos (12U)
#define	CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
#define	CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
#define	CAN_F2R2_FB13_Pos (13U)
#define	CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
#define	CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
#define	CAN_F2R2_FB14_Pos (14U)
#define	CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
#define	CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
#define	CAN_F2R2_FB15_Pos (15U)
#define	CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
#define	CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
#define	CAN_F2R2_FB16_Pos (16U)
#define	CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
#define	CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
#define	CAN_F2R2_FB17_Pos (17U)
#define	CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
#define	CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
#define	CAN_F2R2_FB18_Pos (18U)
#define	CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
#define	CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
#define	CAN_F2R2_FB19_Pos (19U)
#define	CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
#define	CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
#define	CAN_F2R2_FB20_Pos (20U)
#define	CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
#define	CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
#define	CAN_F2R2_FB21_Pos (21U)
#define	CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
#define	CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
#define	CAN_F2R2_FB22_Pos (22U)
#define	CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
#define	CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
#define	CAN_F2R2_FB23_Pos (23U)
#define	CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
#define	CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
#define	CAN_F2R2_FB24_Pos (24U)
#define	CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
#define	CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
#define	CAN_F2R2_FB25_Pos (25U)
#define	CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
#define	CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
#define	CAN_F2R2_FB26_Pos (26U)
#define	CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
#define	CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
#define	CAN_F2R2_FB27_Pos (27U)
#define	CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
#define	CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
#define	CAN_F2R2_FB28_Pos (28U)
#define	CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
#define	CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
#define	CAN_F2R2_FB29_Pos (29U)
#define	CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
#define	CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
#define	CAN_F2R2_FB30_Pos (30U)
#define	CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
#define	CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
#define	CAN_F2R2_FB31_Pos (31U)
#define	CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
#define	CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
#define	CAN_F3R2_FB0_Pos (0U)
#define	CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
#define	CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
#define	CAN_F3R2_FB1_Pos (1U)
#define	CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
#define	CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
#define	CAN_F3R2_FB2_Pos (2U)
#define	CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
#define	CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
#define	CAN_F3R2_FB3_Pos (3U)
#define	CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
#define	CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
#define	CAN_F3R2_FB4_Pos (4U)
#define	CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
#define	CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
#define	CAN_F3R2_FB5_Pos (5U)
#define	CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
#define	CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
#define	CAN_F3R2_FB6_Pos (6U)
#define	CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
#define	CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
#define	CAN_F3R2_FB7_Pos (7U)
#define	CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
#define	CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
#define	CAN_F3R2_FB8_Pos (8U)
#define	CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
#define	CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
#define	CAN_F3R2_FB9_Pos (9U)
#define	CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
#define	CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
#define	CAN_F3R2_FB10_Pos (10U)
#define	CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
#define	CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
#define	CAN_F3R2_FB11_Pos (11U)
#define	CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
#define	CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
#define	CAN_F3R2_FB12_Pos (12U)
#define	CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
#define	CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
#define	CAN_F3R2_FB13_Pos (13U)
#define	CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
#define	CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
#define	CAN_F3R2_FB14_Pos (14U)
#define	CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
#define	CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
#define	CAN_F3R2_FB15_Pos (15U)
#define	CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
#define	CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
#define	CAN_F3R2_FB16_Pos (16U)
#define	CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
#define	CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
#define	CAN_F3R2_FB17_Pos (17U)
#define	CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
#define	CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
#define	CAN_F3R2_FB18_Pos (18U)
#define	CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
#define	CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
#define	CAN_F3R2_FB19_Pos (19U)
#define	CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
#define	CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
#define	CAN_F3R2_FB20_Pos (20U)
#define	CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
#define	CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
#define	CAN_F3R2_FB21_Pos (21U)
#define	CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
#define	CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
#define	CAN_F3R2_FB22_Pos (22U)
#define	CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
#define	CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
#define	CAN_F3R2_FB23_Pos (23U)
#define	CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
#define	CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
#define	CAN_F3R2_FB24_Pos (24U)
#define	CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
#define	CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
#define	CAN_F3R2_FB25_Pos (25U)
#define	CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
#define	CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
#define	CAN_F3R2_FB26_Pos (26U)
#define	CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
#define	CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
#define	CAN_F3R2_FB27_Pos (27U)
#define	CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
#define	CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
#define	CAN_F3R2_FB28_Pos (28U)
#define	CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
#define	CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
#define	CAN_F3R2_FB29_Pos (29U)
#define	CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
#define	CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
#define	CAN_F3R2_FB30_Pos (30U)
#define	CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
#define	CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
#define	CAN_F3R2_FB31_Pos (31U)
#define	CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
#define	CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
#define	CAN_F4R2_FB0_Pos (0U)
#define	CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
#define	CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
#define	CAN_F4R2_FB1_Pos (1U)
#define	CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
#define	CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
#define	CAN_F4R2_FB2_Pos (2U)
#define	CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
#define	CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
#define	CAN_F4R2_FB3_Pos (3U)
#define	CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
#define	CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
#define	CAN_F4R2_FB4_Pos (4U)
#define	CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
#define	CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
#define	CAN_F4R2_FB5_Pos (5U)
#define	CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
#define	CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
#define	CAN_F4R2_FB6_Pos (6U)
#define	CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
#define	CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
#define	CAN_F4R2_FB7_Pos (7U)
#define	CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
#define	CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
#define	CAN_F4R2_FB8_Pos (8U)
#define	CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
#define	CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
#define	CAN_F4R2_FB9_Pos (9U)
#define	CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
#define	CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
#define	CAN_F4R2_FB10_Pos (10U)
#define	CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
#define	CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
#define	CAN_F4R2_FB11_Pos (11U)
#define	CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
#define	CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
#define	CAN_F4R2_FB12_Pos (12U)
#define	CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
#define	CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
#define	CAN_F4R2_FB13_Pos (13U)
#define	CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
#define	CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
#define	CAN_F4R2_FB14_Pos (14U)
#define	CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
#define	CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
#define	CAN_F4R2_FB15_Pos (15U)
#define	CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
#define	CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
#define	CAN_F4R2_FB16_Pos (16U)
#define	CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
#define	CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
#define	CAN_F4R2_FB17_Pos (17U)
#define	CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
#define	CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
#define	CAN_F4R2_FB18_Pos (18U)
#define	CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
#define	CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
#define	CAN_F4R2_FB19_Pos (19U)
#define	CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
#define	CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
#define	CAN_F4R2_FB20_Pos (20U)
#define	CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
#define	CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
#define	CAN_F4R2_FB21_Pos (21U)
#define	CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
#define	CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
#define	CAN_F4R2_FB22_Pos (22U)
#define	CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
#define	CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
#define	CAN_F4R2_FB23_Pos (23U)
#define	CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
#define	CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
#define	CAN_F4R2_FB24_Pos (24U)
#define	CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
#define	CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
#define	CAN_F4R2_FB25_Pos (25U)
#define	CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
#define	CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
#define	CAN_F4R2_FB26_Pos (26U)
#define	CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
#define	CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
#define	CAN_F4R2_FB27_Pos (27U)
#define	CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
#define	CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
#define	CAN_F4R2_FB28_Pos (28U)
#define	CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
#define	CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
#define	CAN_F4R2_FB29_Pos (29U)
#define	CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
#define	CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
#define	CAN_F4R2_FB30_Pos (30U)
#define	CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
#define	CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
#define	CAN_F4R2_FB31_Pos (31U)
#define	CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
#define	CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
#define	CAN_F5R2_FB0_Pos (0U)
#define	CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
#define	CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
#define	CAN_F5R2_FB1_Pos (1U)
#define	CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
#define	CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
#define	CAN_F5R2_FB2_Pos (2U)
#define	CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
#define	CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
#define	CAN_F5R2_FB3_Pos (3U)
#define	CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
#define	CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
#define	CAN_F5R2_FB4_Pos (4U)
#define	CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
#define	CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
#define	CAN_F5R2_FB5_Pos (5U)
#define	CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
#define	CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
#define	CAN_F5R2_FB6_Pos (6U)
#define	CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
#define	CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
#define	CAN_F5R2_FB7_Pos (7U)
#define	CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
#define	CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
#define	CAN_F5R2_FB8_Pos (8U)
#define	CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
#define	CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
#define	CAN_F5R2_FB9_Pos (9U)
#define	CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
#define	CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
#define	CAN_F5R2_FB10_Pos (10U)
#define	CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
#define	CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
#define	CAN_F5R2_FB11_Pos (11U)
#define	CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
#define	CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
#define	CAN_F5R2_FB12_Pos (12U)
#define	CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
#define	CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
#define	CAN_F5R2_FB13_Pos (13U)
#define	CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
#define	CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
#define	CAN_F5R2_FB14_Pos (14U)
#define	CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
#define	CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
#define	CAN_F5R2_FB15_Pos (15U)
#define	CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
#define	CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
#define	CAN_F5R2_FB16_Pos (16U)
#define	CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
#define	CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
#define	CAN_F5R2_FB17_Pos (17U)
#define	CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
#define	CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
#define	CAN_F5R2_FB18_Pos (18U)
#define	CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
#define	CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
#define	CAN_F5R2_FB19_Pos (19U)
#define	CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
#define	CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
#define	CAN_F5R2_FB20_Pos (20U)
#define	CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
#define	CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
#define	CAN_F5R2_FB21_Pos (21U)
#define	CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
#define	CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
#define	CAN_F5R2_FB22_Pos (22U)
#define	CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
#define	CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
#define	CAN_F5R2_FB23_Pos (23U)
#define	CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
#define	CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
#define	CAN_F5R2_FB24_Pos (24U)
#define	CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
#define	CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
#define	CAN_F5R2_FB25_Pos (25U)
#define	CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
#define	CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
#define	CAN_F5R2_FB26_Pos (26U)
#define	CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
#define	CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
#define	CAN_F5R2_FB27_Pos (27U)
#define	CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
#define	CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
#define	CAN_F5R2_FB28_Pos (28U)
#define	CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
#define	CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
#define	CAN_F5R2_FB29_Pos (29U)
#define	CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
#define	CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
#define	CAN_F5R2_FB30_Pos (30U)
#define	CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
#define	CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
#define	CAN_F5R2_FB31_Pos (31U)
#define	CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
#define	CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
#define	CAN_F6R2_FB0_Pos (0U)
#define	CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
#define	CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
#define	CAN_F6R2_FB1_Pos (1U)
#define	CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
#define	CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
#define	CAN_F6R2_FB2_Pos (2U)
#define	CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
#define	CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
#define	CAN_F6R2_FB3_Pos (3U)
#define	CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
#define	CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
#define	CAN_F6R2_FB4_Pos (4U)
#define	CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
#define	CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
#define	CAN_F6R2_FB5_Pos (5U)
#define	CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
#define	CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
#define	CAN_F6R2_FB6_Pos (6U)
#define	CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
#define	CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
#define	CAN_F6R2_FB7_Pos (7U)
#define	CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
#define	CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
#define	CAN_F6R2_FB8_Pos (8U)
#define	CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
#define	CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
#define	CAN_F6R2_FB9_Pos (9U)
#define	CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
#define	CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
#define	CAN_F6R2_FB10_Pos (10U)
#define	CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
#define	CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
#define	CAN_F6R2_FB11_Pos (11U)
#define	CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
#define	CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
#define	CAN_F6R2_FB12_Pos (12U)
#define	CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
#define	CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
#define	CAN_F6R2_FB13_Pos (13U)
#define	CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
#define	CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
#define	CAN_F6R2_FB14_Pos (14U)
#define	CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
#define	CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
#define	CAN_F6R2_FB15_Pos (15U)
#define	CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
#define	CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
#define	CAN_F6R2_FB16_Pos (16U)
#define	CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
#define	CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
#define	CAN_F6R2_FB17_Pos (17U)
#define	CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
#define	CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
#define	CAN_F6R2_FB18_Pos (18U)
#define	CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
#define	CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
#define	CAN_F6R2_FB19_Pos (19U)
#define	CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
#define	CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
#define	CAN_F6R2_FB20_Pos (20U)
#define	CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
#define	CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
#define	CAN_F6R2_FB21_Pos (21U)
#define	CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
#define	CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
#define	CAN_F6R2_FB22_Pos (22U)
#define	CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
#define	CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
#define	CAN_F6R2_FB23_Pos (23U)
#define	CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
#define	CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
#define	CAN_F6R2_FB24_Pos (24U)
#define	CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
#define	CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
#define	CAN_F6R2_FB25_Pos (25U)
#define	CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
#define	CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
#define	CAN_F6R2_FB26_Pos (26U)
#define	CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
#define	CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
#define	CAN_F6R2_FB27_Pos (27U)
#define	CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
#define	CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
#define	CAN_F6R2_FB28_Pos (28U)
#define	CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
#define	CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
#define	CAN_F6R2_FB29_Pos (29U)
#define	CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
#define	CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
#define	CAN_F6R2_FB30_Pos (30U)
#define	CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
#define	CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
#define	CAN_F6R2_FB31_Pos (31U)
#define	CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
#define	CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
#define	CAN_F7R2_FB0_Pos (0U)
#define	CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
#define	CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
#define	CAN_F7R2_FB1_Pos (1U)
#define	CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
#define	CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
#define	CAN_F7R2_FB2_Pos (2U)
#define	CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
#define	CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
#define	CAN_F7R2_FB3_Pos (3U)
#define	CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
#define	CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
#define	CAN_F7R2_FB4_Pos (4U)
#define	CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
#define	CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
#define	CAN_F7R2_FB5_Pos (5U)
#define	CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
#define	CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
#define	CAN_F7R2_FB6_Pos (6U)
#define	CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
#define	CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
#define	CAN_F7R2_FB7_Pos (7U)
#define	CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
#define	CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
#define	CAN_F7R2_FB8_Pos (8U)
#define	CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
#define	CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
#define	CAN_F7R2_FB9_Pos (9U)
#define	CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
#define	CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
#define	CAN_F7R2_FB10_Pos (10U)
#define	CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
#define	CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
#define	CAN_F7R2_FB11_Pos (11U)
#define	CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
#define	CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
#define	CAN_F7R2_FB12_Pos (12U)
#define	CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
#define	CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
#define	CAN_F7R2_FB13_Pos (13U)
#define	CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
#define	CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
#define	CAN_F7R2_FB14_Pos (14U)
#define	CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
#define	CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
#define	CAN_F7R2_FB15_Pos (15U)
#define	CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
#define	CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
#define	CAN_F7R2_FB16_Pos (16U)
#define	CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
#define	CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
#define	CAN_F7R2_FB17_Pos (17U)
#define	CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
#define	CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
#define	CAN_F7R2_FB18_Pos (18U)
#define	CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
#define	CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
#define	CAN_F7R2_FB19_Pos (19U)
#define	CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
#define	CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
#define	CAN_F7R2_FB20_Pos (20U)
#define	CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
#define	CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
#define	CAN_F7R2_FB21_Pos (21U)
#define	CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
#define	CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
#define	CAN_F7R2_FB22_Pos (22U)
#define	CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
#define	CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
#define	CAN_F7R2_FB23_Pos (23U)
#define	CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
#define	CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
#define	CAN_F7R2_FB24_Pos (24U)
#define	CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
#define	CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
#define	CAN_F7R2_FB25_Pos (25U)
#define	CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
#define	CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
#define	CAN_F7R2_FB26_Pos (26U)
#define	CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
#define	CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
#define	CAN_F7R2_FB27_Pos (27U)
#define	CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
#define	CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
#define	CAN_F7R2_FB28_Pos (28U)
#define	CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
#define	CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
#define	CAN_F7R2_FB29_Pos (29U)
#define	CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
#define	CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
#define	CAN_F7R2_FB30_Pos (30U)
#define	CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
#define	CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
#define	CAN_F7R2_FB31_Pos (31U)
#define	CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
#define	CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
#define	CAN_F8R2_FB0_Pos (0U)
#define	CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
#define	CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
#define	CAN_F8R2_FB1_Pos (1U)
#define	CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
#define	CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
#define	CAN_F8R2_FB2_Pos (2U)
#define	CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
#define	CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
#define	CAN_F8R2_FB3_Pos (3U)
#define	CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
#define	CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
#define	CAN_F8R2_FB4_Pos (4U)
#define	CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
#define	CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
#define	CAN_F8R2_FB5_Pos (5U)
#define	CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
#define	CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
#define	CAN_F8R2_FB6_Pos (6U)
#define	CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
#define	CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
#define	CAN_F8R2_FB7_Pos (7U)
#define	CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
#define	CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
#define	CAN_F8R2_FB8_Pos (8U)
#define	CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
#define	CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
#define	CAN_F8R2_FB9_Pos (9U)
#define	CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
#define	CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
#define	CAN_F8R2_FB10_Pos (10U)
#define	CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
#define	CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
#define	CAN_F8R2_FB11_Pos (11U)
#define	CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
#define	CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
#define	CAN_F8R2_FB12_Pos (12U)
#define	CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
#define	CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
#define	CAN_F8R2_FB13_Pos (13U)
#define	CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
#define	CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
#define	CAN_F8R2_FB14_Pos (14U)
#define	CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
#define	CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
#define	CAN_F8R2_FB15_Pos (15U)
#define	CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
#define	CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
#define	CAN_F8R2_FB16_Pos (16U)
#define	CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
#define	CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
#define	CAN_F8R2_FB17_Pos (17U)
#define	CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
#define	CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
#define	CAN_F8R2_FB18_Pos (18U)
#define	CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
#define	CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
#define	CAN_F8R2_FB19_Pos (19U)
#define	CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
#define	CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
#define	CAN_F8R2_FB20_Pos (20U)
#define	CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
#define	CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
#define	CAN_F8R2_FB21_Pos (21U)
#define	CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
#define	CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
#define	CAN_F8R2_FB22_Pos (22U)
#define	CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
#define	CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
#define	CAN_F8R2_FB23_Pos (23U)
#define	CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
#define	CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
#define	CAN_F8R2_FB24_Pos (24U)
#define	CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
#define	CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
#define	CAN_F8R2_FB25_Pos (25U)
#define	CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
#define	CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
#define	CAN_F8R2_FB26_Pos (26U)
#define	CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
#define	CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
#define	CAN_F8R2_FB27_Pos (27U)
#define	CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
#define	CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
#define	CAN_F8R2_FB28_Pos (28U)
#define	CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
#define	CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
#define	CAN_F8R2_FB29_Pos (29U)
#define	CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
#define	CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
#define	CAN_F8R2_FB30_Pos (30U)
#define	CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
#define	CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
#define	CAN_F8R2_FB31_Pos (31U)
#define	CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
#define	CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
#define	CAN_F9R2_FB0_Pos (0U)
#define	CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
#define	CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
#define	CAN_F9R2_FB1_Pos (1U)
#define	CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
#define	CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
#define	CAN_F9R2_FB2_Pos (2U)
#define	CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
#define	CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
#define	CAN_F9R2_FB3_Pos (3U)
#define	CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
#define	CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
#define	CAN_F9R2_FB4_Pos (4U)
#define	CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
#define	CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
#define	CAN_F9R2_FB5_Pos (5U)
#define	CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
#define	CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
#define	CAN_F9R2_FB6_Pos (6U)
#define	CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
#define	CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
#define	CAN_F9R2_FB7_Pos (7U)
#define	CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
#define	CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
#define	CAN_F9R2_FB8_Pos (8U)
#define	CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
#define	CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
#define	CAN_F9R2_FB9_Pos (9U)
#define	CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
#define	CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
#define	CAN_F9R2_FB10_Pos (10U)
#define	CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
#define	CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
#define	CAN_F9R2_FB11_Pos (11U)
#define	CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
#define	CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
#define	CAN_F9R2_FB12_Pos (12U)
#define	CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
#define	CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
#define	CAN_F9R2_FB13_Pos (13U)
#define	CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
#define	CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
#define	CAN_F9R2_FB14_Pos (14U)
#define	CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
#define	CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
#define	CAN_F9R2_FB15_Pos (15U)
#define	CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
#define	CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
#define	CAN_F9R2_FB16_Pos (16U)
#define	CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
#define	CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
#define	CAN_F9R2_FB17_Pos (17U)
#define	CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
#define	CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
#define	CAN_F9R2_FB18_Pos (18U)
#define	CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
#define	CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
#define	CAN_F9R2_FB19_Pos (19U)
#define	CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
#define	CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
#define	CAN_F9R2_FB20_Pos (20U)
#define	CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
#define	CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
#define	CAN_F9R2_FB21_Pos (21U)
#define	CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
#define	CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
#define	CAN_F9R2_FB22_Pos (22U)
#define	CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
#define	CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
#define	CAN_F9R2_FB23_Pos (23U)
#define	CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
#define	CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
#define	CAN_F9R2_FB24_Pos (24U)
#define	CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
#define	CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
#define	CAN_F9R2_FB25_Pos (25U)
#define	CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
#define	CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
#define	CAN_F9R2_FB26_Pos (26U)
#define	CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
#define	CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
#define	CAN_F9R2_FB27_Pos (27U)
#define	CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
#define	CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
#define	CAN_F9R2_FB28_Pos (28U)
#define	CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
#define	CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
#define	CAN_F9R2_FB29_Pos (29U)
#define	CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
#define	CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
#define	CAN_F9R2_FB30_Pos (30U)
#define	CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
#define	CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
#define	CAN_F9R2_FB31_Pos (31U)
#define	CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
#define	CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
#define	CAN_F10R2_FB0_Pos (0U)
#define	CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
#define	CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
#define	CAN_F10R2_FB1_Pos (1U)
#define	CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
#define	CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
#define	CAN_F10R2_FB2_Pos (2U)
#define	CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
#define	CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
#define	CAN_F10R2_FB3_Pos (3U)
#define	CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
#define	CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
#define	CAN_F10R2_FB4_Pos (4U)
#define	CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
#define	CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
#define	CAN_F10R2_FB5_Pos (5U)
#define	CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
#define	CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
#define	CAN_F10R2_FB6_Pos (6U)
#define	CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
#define	CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
#define	CAN_F10R2_FB7_Pos (7U)
#define	CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
#define	CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
#define	CAN_F10R2_FB8_Pos (8U)
#define	CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
#define	CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
#define	CAN_F10R2_FB9_Pos (9U)
#define	CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
#define	CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
#define	CAN_F10R2_FB10_Pos (10U)
#define	CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
#define	CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
#define	CAN_F10R2_FB11_Pos (11U)
#define	CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
#define	CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
#define	CAN_F10R2_FB12_Pos (12U)
#define	CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
#define	CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
#define	CAN_F10R2_FB13_Pos (13U)
#define	CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
#define	CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
#define	CAN_F10R2_FB14_Pos (14U)
#define	CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
#define	CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
#define	CAN_F10R2_FB15_Pos (15U)
#define	CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
#define	CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
#define	CAN_F10R2_FB16_Pos (16U)
#define	CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
#define	CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
#define	CAN_F10R2_FB17_Pos (17U)
#define	CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
#define	CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
#define	CAN_F10R2_FB18_Pos (18U)
#define	CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
#define	CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
#define	CAN_F10R2_FB19_Pos (19U)
#define	CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
#define	CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
#define	CAN_F10R2_FB20_Pos (20U)
#define	CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
#define	CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
#define	CAN_F10R2_FB21_Pos (21U)
#define	CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
#define	CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
#define	CAN_F10R2_FB22_Pos (22U)
#define	CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
#define	CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
#define	CAN_F10R2_FB23_Pos (23U)
#define	CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
#define	CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
#define	CAN_F10R2_FB24_Pos (24U)
#define	CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
#define	CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
#define	CAN_F10R2_FB25_Pos (25U)
#define	CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
#define	CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
#define	CAN_F10R2_FB26_Pos (26U)
#define	CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
#define	CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
#define	CAN_F10R2_FB27_Pos (27U)
#define	CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
#define	CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
#define	CAN_F10R2_FB28_Pos (28U)
#define	CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
#define	CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
#define	CAN_F10R2_FB29_Pos (29U)
#define	CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
#define	CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
#define	CAN_F10R2_FB30_Pos (30U)
#define	CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
#define	CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
#define	CAN_F10R2_FB31_Pos (31U)
#define	CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
#define	CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
#define	CAN_F11R2_FB0_Pos (0U)
#define	CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
#define	CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
#define	CAN_F11R2_FB1_Pos (1U)
#define	CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
#define	CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
#define	CAN_F11R2_FB2_Pos (2U)
#define	CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
#define	CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
#define	CAN_F11R2_FB3_Pos (3U)
#define	CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
#define	CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
#define	CAN_F11R2_FB4_Pos (4U)
#define	CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
#define	CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
#define	CAN_F11R2_FB5_Pos (5U)
#define	CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
#define	CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
#define	CAN_F11R2_FB6_Pos (6U)
#define	CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
#define	CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
#define	CAN_F11R2_FB7_Pos (7U)
#define	CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
#define	CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
#define	CAN_F11R2_FB8_Pos (8U)
#define	CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
#define	CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
#define	CAN_F11R2_FB9_Pos (9U)
#define	CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
#define	CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
#define	CAN_F11R2_FB10_Pos (10U)
#define	CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
#define	CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
#define	CAN_F11R2_FB11_Pos (11U)
#define	CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
#define	CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
#define	CAN_F11R2_FB12_Pos (12U)
#define	CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
#define	CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
#define	CAN_F11R2_FB13_Pos (13U)
#define	CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
#define	CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
#define	CAN_F11R2_FB14_Pos (14U)
#define	CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
#define	CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
#define	CAN_F11R2_FB15_Pos (15U)
#define	CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
#define	CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
#define	CAN_F11R2_FB16_Pos (16U)
#define	CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
#define	CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
#define	CAN_F11R2_FB17_Pos (17U)
#define	CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
#define	CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
#define	CAN_F11R2_FB18_Pos (18U)
#define	CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
#define	CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
#define	CAN_F11R2_FB19_Pos (19U)
#define	CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
#define	CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
#define	CAN_F11R2_FB20_Pos (20U)
#define	CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
#define	CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
#define	CAN_F11R2_FB21_Pos (21U)
#define	CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
#define	CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
#define	CAN_F11R2_FB22_Pos (22U)
#define	CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
#define	CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
#define	CAN_F11R2_FB23_Pos (23U)
#define	CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
#define	CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
#define	CAN_F11R2_FB24_Pos (24U)
#define	CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
#define	CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
#define	CAN_F11R2_FB25_Pos (25U)
#define	CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
#define	CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
#define	CAN_F11R2_FB26_Pos (26U)
#define	CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
#define	CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
#define	CAN_F11R2_FB27_Pos (27U)
#define	CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
#define	CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
#define	CAN_F11R2_FB28_Pos (28U)
#define	CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
#define	CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
#define	CAN_F11R2_FB29_Pos (29U)
#define	CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
#define	CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
#define	CAN_F11R2_FB30_Pos (30U)
#define	CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
#define	CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
#define	CAN_F11R2_FB31_Pos (31U)
#define	CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
#define	CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
#define	CAN_F12R2_FB0_Pos (0U)
#define	CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
#define	CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
#define	CAN_F12R2_FB1_Pos (1U)
#define	CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
#define	CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
#define	CAN_F12R2_FB2_Pos (2U)
#define	CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
#define	CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
#define	CAN_F12R2_FB3_Pos (3U)
#define	CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
#define	CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
#define	CAN_F12R2_FB4_Pos (4U)
#define	CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
#define	CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
#define	CAN_F12R2_FB5_Pos (5U)
#define	CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
#define	CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
#define	CAN_F12R2_FB6_Pos (6U)
#define	CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
#define	CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
#define	CAN_F12R2_FB7_Pos (7U)
#define	CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
#define	CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
#define	CAN_F12R2_FB8_Pos (8U)
#define	CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
#define	CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
#define	CAN_F12R2_FB9_Pos (9U)
#define	CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
#define	CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
#define	CAN_F12R2_FB10_Pos (10U)
#define	CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
#define	CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
#define	CAN_F12R2_FB11_Pos (11U)
#define	CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
#define	CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
#define	CAN_F12R2_FB12_Pos (12U)
#define	CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
#define	CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
#define	CAN_F12R2_FB13_Pos (13U)
#define	CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
#define	CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
#define	CAN_F12R2_FB14_Pos (14U)
#define	CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
#define	CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
#define	CAN_F12R2_FB15_Pos (15U)
#define	CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
#define	CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
#define	CAN_F12R2_FB16_Pos (16U)
#define	CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
#define	CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
#define	CAN_F12R2_FB17_Pos (17U)
#define	CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
#define	CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
#define	CAN_F12R2_FB18_Pos (18U)
#define	CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
#define	CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
#define	CAN_F12R2_FB19_Pos (19U)
#define	CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
#define	CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
#define	CAN_F12R2_FB20_Pos (20U)
#define	CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
#define	CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
#define	CAN_F12R2_FB21_Pos (21U)
#define	CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
#define	CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
#define	CAN_F12R2_FB22_Pos (22U)
#define	CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
#define	CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
#define	CAN_F12R2_FB23_Pos (23U)
#define	CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
#define	CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
#define	CAN_F12R2_FB24_Pos (24U)
#define	CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
#define	CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
#define	CAN_F12R2_FB25_Pos (25U)
#define	CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
#define	CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
#define	CAN_F12R2_FB26_Pos (26U)
#define	CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
#define	CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
#define	CAN_F12R2_FB27_Pos (27U)
#define	CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
#define	CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
#define	CAN_F12R2_FB28_Pos (28U)
#define	CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
#define	CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
#define	CAN_F12R2_FB29_Pos (29U)
#define	CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
#define	CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
#define	CAN_F12R2_FB30_Pos (30U)
#define	CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
#define	CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
#define	CAN_F12R2_FB31_Pos (31U)
#define	CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
#define	CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
#define	CAN_F13R2_FB0_Pos (0U)
#define	CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
#define	CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
#define	CAN_F13R2_FB1_Pos (1U)
#define	CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
#define	CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
#define	CAN_F13R2_FB2_Pos (2U)
#define	CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
#define	CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
#define	CAN_F13R2_FB3_Pos (3U)
#define	CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
#define	CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
#define	CAN_F13R2_FB4_Pos (4U)
#define	CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
#define	CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
#define	CAN_F13R2_FB5_Pos (5U)
#define	CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
#define	CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
#define	CAN_F13R2_FB6_Pos (6U)
#define	CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
#define	CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
#define	CAN_F13R2_FB7_Pos (7U)
#define	CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
#define	CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
#define	CAN_F13R2_FB8_Pos (8U)
#define	CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
#define	CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
#define	CAN_F13R2_FB9_Pos (9U)
#define	CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
#define	CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
#define	CAN_F13R2_FB10_Pos (10U)
#define	CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
#define	CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
#define	CAN_F13R2_FB11_Pos (11U)
#define	CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
#define	CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
#define	CAN_F13R2_FB12_Pos (12U)
#define	CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
#define	CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
#define	CAN_F13R2_FB13_Pos (13U)
#define	CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
#define	CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
#define	CAN_F13R2_FB14_Pos (14U)
#define	CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
#define	CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
#define	CAN_F13R2_FB15_Pos (15U)
#define	CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
#define	CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
#define	CAN_F13R2_FB16_Pos (16U)
#define	CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
#define	CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
#define	CAN_F13R2_FB17_Pos (17U)
#define	CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
#define	CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
#define	CAN_F13R2_FB18_Pos (18U)
#define	CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
#define	CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
#define	CAN_F13R2_FB19_Pos (19U)
#define	CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
#define	CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
#define	CAN_F13R2_FB20_Pos (20U)
#define	CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
#define	CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
#define	CAN_F13R2_FB21_Pos (21U)
#define	CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
#define	CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
#define	CAN_F13R2_FB22_Pos (22U)
#define	CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
#define	CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
#define	CAN_F13R2_FB23_Pos (23U)
#define	CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
#define	CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
#define	CAN_F13R2_FB24_Pos (24U)
#define	CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
#define	CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
#define	CAN_F13R2_FB25_Pos (25U)
#define	CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
#define	CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
#define	CAN_F13R2_FB26_Pos (26U)
#define	CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
#define	CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
#define	CAN_F13R2_FB27_Pos (27U)
#define	CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
#define	CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
#define	CAN_F13R2_FB28_Pos (28U)
#define	CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
#define	CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
#define	CAN_F13R2_FB29_Pos (29U)
#define	CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
#define	CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
#define	CAN_F13R2_FB30_Pos (30U)
#define	CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
#define	CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
#define	CAN_F13R2_FB31_Pos (31U)
#define	CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
#define	CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
#define	CRC_DR_DR_Pos (0U)
#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
#define	CRC_DR_DR CRC_DR_DR_Msk
#define	CRC_IDR_IDR_Pos (0U)
#define	CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
#define	CRC_IDR_IDR CRC_IDR_IDR_Msk
#define	CRC_CR_RESET_Pos (0U)
#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
#define	CRC_CR_RESET CRC_CR_RESET_Msk
#define	DAC_CHANNEL2_SUPPORT
#define	DAC_CR_EN1_Pos (0U)
#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
#define	DAC_CR_EN1 DAC_CR_EN1_Msk
#define	DAC_CR_BOFF1_Pos (1U)
#define	DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
#define	DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
#define	DAC_CR_TEN1_Pos (2U)
#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk
#define	DAC_CR_TSEL1_Pos (3U)
#define	DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
#define	DAC_CR_WAVE1_Pos (6U)
#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
#define	DAC_CR_MAMP1_Pos (8U)
#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
#define	DAC_CR_DMAEN1_Pos (12U)
#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
#define	DAC_CR_DMAUDRIE1_Pos (13U)
#define	DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
#define	DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
#define	DAC_CR_EN2_Pos (16U)
#define	DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
#define	DAC_CR_EN2 DAC_CR_EN2_Msk
#define	DAC_CR_BOFF2_Pos (17U)
#define	DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
#define	DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
#define	DAC_CR_TEN2_Pos (18U)
#define	DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
#define	DAC_CR_TEN2 DAC_CR_TEN2_Msk
#define	DAC_CR_TSEL2_Pos (19U)
#define	DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
#define	DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
#define	DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
#define	DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
#define	DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
#define	DAC_CR_WAVE2_Pos (22U)
#define	DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
#define	DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
#define	DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
#define	DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
#define	DAC_CR_MAMP2_Pos (24U)
#define	DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
#define	DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
#define	DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
#define	DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
#define	DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
#define	DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
#define	DAC_CR_DMAEN2_Pos (28U)
#define	DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
#define	DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
#define	DAC_CR_DMAUDRIE2_Pos (29U)
#define	DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
#define	DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
#define	DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define	DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
#define	DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
#define	DAC_DHR12R1_DACC1DHR_Pos (0U)
#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
#define	DAC_DHR12L1_DACC1DHR_Pos (4U)
#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
#define	DAC_DHR8R1_DACC1DHR_Pos (0U)
#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
#define	DAC_DHR12R2_DACC2DHR_Pos (0U)
#define	DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
#define	DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
#define	DAC_DHR12L2_DACC2DHR_Pos (4U)
#define	DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
#define	DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
#define	DAC_DHR8R2_DACC2DHR_Pos (0U)
#define	DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
#define	DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
#define	DAC_DHR12RD_DACC1DHR_Pos (0U)
#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
#define	DAC_DHR12RD_DACC2DHR_Pos (16U)
#define	DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
#define	DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
#define	DAC_DHR12LD_DACC1DHR_Pos (4U)
#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
#define	DAC_DHR12LD_DACC2DHR_Pos (20U)
#define	DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
#define	DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
#define	DAC_DHR8RD_DACC1DHR_Pos (0U)
#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
#define	DAC_DHR8RD_DACC2DHR_Pos (8U)
#define	DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
#define	DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
#define	DAC_DOR1_DACC1DOR_Pos (0U)
#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
#define	DAC_DOR2_DACC2DOR_Pos (0U)
#define	DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
#define	DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
#define	DAC_SR_DMAUDR1_Pos (13U)
#define	DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
#define	DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
#define	DAC_SR_DMAUDR2_Pos (29U)
#define	DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
#define	DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
#define	DCMI_CR_CAPTURE_Pos (0U)
#define	DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
#define	DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
#define	DCMI_CR_CM_Pos (1U)
#define	DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
#define	DCMI_CR_CM DCMI_CR_CM_Msk
#define	DCMI_CR_CROP_Pos (2U)
#define	DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
#define	DCMI_CR_CROP DCMI_CR_CROP_Msk
#define	DCMI_CR_JPEG_Pos (3U)
#define	DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
#define	DCMI_CR_JPEG DCMI_CR_JPEG_Msk
#define	DCMI_CR_ESS_Pos (4U)
#define	DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
#define	DCMI_CR_ESS DCMI_CR_ESS_Msk
#define	DCMI_CR_PCKPOL_Pos (5U)
#define	DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
#define	DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
#define	DCMI_CR_HSPOL_Pos (6U)
#define	DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
#define	DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
#define	DCMI_CR_VSPOL_Pos (7U)
#define	DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
#define	DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
#define	DCMI_CR_FCRC_0 0x00000100U
#define	DCMI_CR_FCRC_1 0x00000200U
#define	DCMI_CR_EDM_0 0x00000400U
#define	DCMI_CR_EDM_1 0x00000800U
#define	DCMI_CR_CRE_Pos (12U)
#define	DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
#define	DCMI_CR_CRE DCMI_CR_CRE_Msk
#define	DCMI_CR_ENABLE_Pos (14U)
#define	DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
#define	DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
#define	DCMI_SR_HSYNC_Pos (0U)
#define	DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
#define	DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
#define	DCMI_SR_VSYNC_Pos (1U)
#define	DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
#define	DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
#define	DCMI_SR_FNE_Pos (2U)
#define	DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
#define	DCMI_SR_FNE DCMI_SR_FNE_Msk
#define	DCMI_RIS_FRAME_RIS_Pos (0U)
#define	DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
#define	DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
#define	DCMI_RIS_OVR_RIS_Pos (1U)
#define	DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
#define	DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
#define	DCMI_RIS_ERR_RIS_Pos (2U)
#define	DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
#define	DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
#define	DCMI_RIS_VSYNC_RIS_Pos (3U)
#define	DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
#define	DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
#define	DCMI_RIS_LINE_RIS_Pos (4U)
#define	DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
#define	DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
#define	DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
#define	DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
#define	DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
#define	DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
#define	DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
#define	DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
#define	DCMI_IER_FRAME_IE_Pos (0U)
#define	DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
#define	DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
#define	DCMI_IER_OVR_IE_Pos (1U)
#define	DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
#define	DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
#define	DCMI_IER_ERR_IE_Pos (2U)
#define	DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
#define	DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
#define	DCMI_IER_VSYNC_IE_Pos (3U)
#define	DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
#define	DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
#define	DCMI_IER_LINE_IE_Pos (4U)
#define	DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
#define	DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
#define	DCMI_IER_OVF_IE DCMI_IER_OVR_IE
#define	DCMI_MIS_FRAME_MIS_Pos (0U)
#define	DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
#define	DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
#define	DCMI_MIS_OVR_MIS_Pos (1U)
#define	DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
#define	DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
#define	DCMI_MIS_ERR_MIS_Pos (2U)
#define	DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
#define	DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
#define	DCMI_MIS_VSYNC_MIS_Pos (3U)
#define	DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
#define	DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
#define	DCMI_MIS_LINE_MIS_Pos (4U)
#define	DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
#define	DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
#define	DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
#define	DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
#define	DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
#define	DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
#define	DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
#define	DCMI_ICR_FRAME_ISC_Pos (0U)
#define	DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
#define	DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
#define	DCMI_ICR_OVR_ISC_Pos (1U)
#define	DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
#define	DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
#define	DCMI_ICR_ERR_ISC_Pos (2U)
#define	DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
#define	DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
#define	DCMI_ICR_VSYNC_ISC_Pos (3U)
#define	DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
#define	DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
#define	DCMI_ICR_LINE_ISC_Pos (4U)
#define	DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
#define	DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
#define	DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
#define	DCMI_ESCR_FSC_Pos (0U)
#define	DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
#define	DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
#define	DCMI_ESCR_LSC_Pos (8U)
#define	DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
#define	DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
#define	DCMI_ESCR_LEC_Pos (16U)
#define	DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
#define	DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
#define	DCMI_ESCR_FEC_Pos (24U)
#define	DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
#define	DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
#define	DCMI_ESUR_FSU_Pos (0U)
#define	DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
#define	DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
#define	DCMI_ESUR_LSU_Pos (8U)
#define	DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
#define	DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
#define	DCMI_ESUR_LEU_Pos (16U)
#define	DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
#define	DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
#define	DCMI_ESUR_FEU_Pos (24U)
#define	DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
#define	DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
#define	DCMI_CWSTRT_HOFFCNT_Pos (0U)
#define	DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
#define	DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
#define	DCMI_CWSTRT_VST_Pos (16U)
#define	DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
#define	DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
#define	DCMI_CWSIZE_CAPCNT_Pos (0U)
#define	DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
#define	DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
#define	DCMI_CWSIZE_VLINE_Pos (16U)
#define	DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
#define	DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
#define	DCMI_DR_BYTE0_Pos (0U)
#define	DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
#define	DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
#define	DCMI_DR_BYTE1_Pos (8U)
#define	DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
#define	DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
#define	DCMI_DR_BYTE2_Pos (16U)
#define	DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
#define	DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
#define	DCMI_DR_BYTE3_Pos (24U)
#define	DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
#define	DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
#define	DMA_SxCR_CHSEL_Pos (25U)
#define	DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
#define	DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
#define	DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
#define	DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
#define	DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
#define	DMA_SxCR_MBURST_Pos (23U)
#define	DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
#define	DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
#define	DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
#define	DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
#define	DMA_SxCR_PBURST_Pos (21U)
#define	DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
#define	DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
#define	DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
#define	DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
#define	DMA_SxCR_CT_Pos (19U)
#define	DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
#define	DMA_SxCR_CT DMA_SxCR_CT_Msk
#define	DMA_SxCR_DBM_Pos (18U)
#define	DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
#define	DMA_SxCR_DBM DMA_SxCR_DBM_Msk
#define	DMA_SxCR_PL_Pos (16U)
#define	DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
#define	DMA_SxCR_PL DMA_SxCR_PL_Msk
#define	DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
#define	DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
#define	DMA_SxCR_PINCOS_Pos (15U)
#define	DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
#define	DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
#define	DMA_SxCR_MSIZE_Pos (13U)
#define	DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
#define	DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
#define	DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
#define	DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
#define	DMA_SxCR_PSIZE_Pos (11U)
#define	DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
#define	DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
#define	DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
#define	DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
#define	DMA_SxCR_MINC_Pos (10U)
#define	DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
#define	DMA_SxCR_MINC DMA_SxCR_MINC_Msk
#define	DMA_SxCR_PINC_Pos (9U)
#define	DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
#define	DMA_SxCR_PINC DMA_SxCR_PINC_Msk
#define	DMA_SxCR_CIRC_Pos (8U)
#define	DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
#define	DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
#define	DMA_SxCR_DIR_Pos (6U)
#define	DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
#define	DMA_SxCR_DIR DMA_SxCR_DIR_Msk
#define	DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
#define	DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
#define	DMA_SxCR_PFCTRL_Pos (5U)
#define	DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
#define	DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
#define	DMA_SxCR_TCIE_Pos (4U)
#define	DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
#define	DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
#define	DMA_SxCR_HTIE_Pos (3U)
#define	DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
#define	DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
#define	DMA_SxCR_TEIE_Pos (2U)
#define	DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
#define	DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
#define	DMA_SxCR_DMEIE_Pos (1U)
#define	DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
#define	DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
#define	DMA_SxCR_EN_Pos (0U)
#define	DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
#define	DMA_SxCR_EN DMA_SxCR_EN_Msk
#define	DMA_SxCR_ACK_Pos (20U)
#define	DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
#define	DMA_SxCR_ACK DMA_SxCR_ACK_Msk
#define	DMA_SxNDT_Pos (0U)
#define	DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
#define	DMA_SxNDT DMA_SxNDT_Msk
#define	DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
#define	DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
#define	DMA_SxFCR_FEIE_Pos (7U)
#define	DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
#define	DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
#define	DMA_SxFCR_FS_Pos (3U)
#define	DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
#define	DMA_SxFCR_FS DMA_SxFCR_FS_Msk
#define	DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
#define	DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
#define	DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
#define	DMA_SxFCR_DMDIS_Pos (2U)
#define	DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
#define	DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
#define	DMA_SxFCR_FTH_Pos (0U)
#define	DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
#define	DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
#define	DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
#define	DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
#define	DMA_LISR_TCIF3_Pos (27U)
#define	DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
#define	DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
#define	DMA_LISR_HTIF3_Pos (26U)
#define	DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
#define	DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
#define	DMA_LISR_TEIF3_Pos (25U)
#define	DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
#define	DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
#define	DMA_LISR_DMEIF3_Pos (24U)
#define	DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
#define	DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
#define	DMA_LISR_FEIF3_Pos (22U)
#define	DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
#define	DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
#define	DMA_LISR_TCIF2_Pos (21U)
#define	DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
#define	DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
#define	DMA_LISR_HTIF2_Pos (20U)
#define	DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
#define	DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
#define	DMA_LISR_TEIF2_Pos (19U)
#define	DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
#define	DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
#define	DMA_LISR_DMEIF2_Pos (18U)
#define	DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
#define	DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
#define	DMA_LISR_FEIF2_Pos (16U)
#define	DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
#define	DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
#define	DMA_LISR_TCIF1_Pos (11U)
#define	DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
#define	DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
#define	DMA_LISR_HTIF1_Pos (10U)
#define	DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
#define	DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
#define	DMA_LISR_TEIF1_Pos (9U)
#define	DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
#define	DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
#define	DMA_LISR_DMEIF1_Pos (8U)
#define	DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
#define	DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
#define	DMA_LISR_FEIF1_Pos (6U)
#define	DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
#define	DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
#define	DMA_LISR_TCIF0_Pos (5U)
#define	DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
#define	DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
#define	DMA_LISR_HTIF0_Pos (4U)
#define	DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
#define	DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
#define	DMA_LISR_TEIF0_Pos (3U)
#define	DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
#define	DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
#define	DMA_LISR_DMEIF0_Pos (2U)
#define	DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
#define	DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
#define	DMA_LISR_FEIF0_Pos (0U)
#define	DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
#define	DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
#define	DMA_HISR_TCIF7_Pos (27U)
#define	DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
#define	DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
#define	DMA_HISR_HTIF7_Pos (26U)
#define	DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
#define	DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
#define	DMA_HISR_TEIF7_Pos (25U)
#define	DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
#define	DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
#define	DMA_HISR_DMEIF7_Pos (24U)
#define	DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
#define	DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
#define	DMA_HISR_FEIF7_Pos (22U)
#define	DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
#define	DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
#define	DMA_HISR_TCIF6_Pos (21U)
#define	DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
#define	DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
#define	DMA_HISR_HTIF6_Pos (20U)
#define	DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
#define	DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
#define	DMA_HISR_TEIF6_Pos (19U)
#define	DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
#define	DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
#define	DMA_HISR_DMEIF6_Pos (18U)
#define	DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
#define	DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
#define	DMA_HISR_FEIF6_Pos (16U)
#define	DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
#define	DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
#define	DMA_HISR_TCIF5_Pos (11U)
#define	DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
#define	DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
#define	DMA_HISR_HTIF5_Pos (10U)
#define	DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
#define	DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
#define	DMA_HISR_TEIF5_Pos (9U)
#define	DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
#define	DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
#define	DMA_HISR_DMEIF5_Pos (8U)
#define	DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
#define	DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
#define	DMA_HISR_FEIF5_Pos (6U)
#define	DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
#define	DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
#define	DMA_HISR_TCIF4_Pos (5U)
#define	DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
#define	DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
#define	DMA_HISR_HTIF4_Pos (4U)
#define	DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
#define	DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
#define	DMA_HISR_TEIF4_Pos (3U)
#define	DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
#define	DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
#define	DMA_HISR_DMEIF4_Pos (2U)
#define	DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
#define	DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
#define	DMA_HISR_FEIF4_Pos (0U)
#define	DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
#define	DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
#define	DMA_LIFCR_CTCIF3_Pos (27U)
#define	DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
#define	DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
#define	DMA_LIFCR_CHTIF3_Pos (26U)
#define	DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
#define	DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
#define	DMA_LIFCR_CTEIF3_Pos (25U)
#define	DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
#define	DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
#define	DMA_LIFCR_CDMEIF3_Pos (24U)
#define	DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
#define	DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
#define	DMA_LIFCR_CFEIF3_Pos (22U)
#define	DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
#define	DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
#define	DMA_LIFCR_CTCIF2_Pos (21U)
#define	DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
#define	DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
#define	DMA_LIFCR_CHTIF2_Pos (20U)
#define	DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
#define	DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
#define	DMA_LIFCR_CTEIF2_Pos (19U)
#define	DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
#define	DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
#define	DMA_LIFCR_CDMEIF2_Pos (18U)
#define	DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
#define	DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
#define	DMA_LIFCR_CFEIF2_Pos (16U)
#define	DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
#define	DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
#define	DMA_LIFCR_CTCIF1_Pos (11U)
#define	DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
#define	DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
#define	DMA_LIFCR_CHTIF1_Pos (10U)
#define	DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
#define	DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
#define	DMA_LIFCR_CTEIF1_Pos (9U)
#define	DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
#define	DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
#define	DMA_LIFCR_CDMEIF1_Pos (8U)
#define	DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
#define	DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
#define	DMA_LIFCR_CFEIF1_Pos (6U)
#define	DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
#define	DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
#define	DMA_LIFCR_CTCIF0_Pos (5U)
#define	DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
#define	DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
#define	DMA_LIFCR_CHTIF0_Pos (4U)
#define	DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
#define	DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
#define	DMA_LIFCR_CTEIF0_Pos (3U)
#define	DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
#define	DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
#define	DMA_LIFCR_CDMEIF0_Pos (2U)
#define	DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
#define	DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
#define	DMA_LIFCR_CFEIF0_Pos (0U)
#define	DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
#define	DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
#define	DMA_HIFCR_CTCIF7_Pos (27U)
#define	DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
#define	DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
#define	DMA_HIFCR_CHTIF7_Pos (26U)
#define	DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
#define	DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
#define	DMA_HIFCR_CTEIF7_Pos (25U)
#define	DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
#define	DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
#define	DMA_HIFCR_CDMEIF7_Pos (24U)
#define	DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
#define	DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
#define	DMA_HIFCR_CFEIF7_Pos (22U)
#define	DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
#define	DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
#define	DMA_HIFCR_CTCIF6_Pos (21U)
#define	DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
#define	DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
#define	DMA_HIFCR_CHTIF6_Pos (20U)
#define	DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
#define	DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
#define	DMA_HIFCR_CTEIF6_Pos (19U)
#define	DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
#define	DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
#define	DMA_HIFCR_CDMEIF6_Pos (18U)
#define	DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
#define	DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
#define	DMA_HIFCR_CFEIF6_Pos (16U)
#define	DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
#define	DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
#define	DMA_HIFCR_CTCIF5_Pos (11U)
#define	DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
#define	DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
#define	DMA_HIFCR_CHTIF5_Pos (10U)
#define	DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
#define	DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
#define	DMA_HIFCR_CTEIF5_Pos (9U)
#define	DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
#define	DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
#define	DMA_HIFCR_CDMEIF5_Pos (8U)
#define	DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
#define	DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
#define	DMA_HIFCR_CFEIF5_Pos (6U)
#define	DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
#define	DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
#define	DMA_HIFCR_CTCIF4_Pos (5U)
#define	DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
#define	DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
#define	DMA_HIFCR_CHTIF4_Pos (4U)
#define	DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
#define	DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
#define	DMA_HIFCR_CTEIF4_Pos (3U)
#define	DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
#define	DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
#define	DMA_HIFCR_CDMEIF4_Pos (2U)
#define	DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
#define	DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
#define	DMA_HIFCR_CFEIF4_Pos (0U)
#define	DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
#define	DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
#define	DMA_SxPAR_PA_Pos (0U)
#define	DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
#define	DMA_SxPAR_PA DMA_SxPAR_PA_Msk
#define	DMA_SxM0AR_M0A_Pos (0U)
#define	DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
#define	DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
#define	DMA_SxM1AR_M1A_Pos (0U)
#define	DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
#define	DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
#define	EXTI_IMR_MR0_Pos (0U)
#define	EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
#define	EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
#define	EXTI_IMR_MR1_Pos (1U)
#define	EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
#define	EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
#define	EXTI_IMR_MR2_Pos (2U)
#define	EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
#define	EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
#define	EXTI_IMR_MR3_Pos (3U)
#define	EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
#define	EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
#define	EXTI_IMR_MR4_Pos (4U)
#define	EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
#define	EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
#define	EXTI_IMR_MR5_Pos (5U)
#define	EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
#define	EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
#define	EXTI_IMR_MR6_Pos (6U)
#define	EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
#define	EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
#define	EXTI_IMR_MR7_Pos (7U)
#define	EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
#define	EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
#define	EXTI_IMR_MR8_Pos (8U)
#define	EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
#define	EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
#define	EXTI_IMR_MR9_Pos (9U)
#define	EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
#define	EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
#define	EXTI_IMR_MR10_Pos (10U)
#define	EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
#define	EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
#define	EXTI_IMR_MR11_Pos (11U)
#define	EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
#define	EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
#define	EXTI_IMR_MR12_Pos (12U)
#define	EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
#define	EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
#define	EXTI_IMR_MR13_Pos (13U)
#define	EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
#define	EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
#define	EXTI_IMR_MR14_Pos (14U)
#define	EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
#define	EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
#define	EXTI_IMR_MR15_Pos (15U)
#define	EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
#define	EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
#define	EXTI_IMR_MR16_Pos (16U)
#define	EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
#define	EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
#define	EXTI_IMR_MR17_Pos (17U)
#define	EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
#define	EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
#define	EXTI_IMR_MR18_Pos (18U)
#define	EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
#define	EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
#define	EXTI_IMR_MR19_Pos (19U)
#define	EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
#define	EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
#define	EXTI_IMR_MR20_Pos (20U)
#define	EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
#define	EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
#define	EXTI_IMR_MR21_Pos (21U)
#define	EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
#define	EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
#define	EXTI_IMR_MR22_Pos (22U)
#define	EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
#define	EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
#define	EXTI_IMR_IM0 EXTI_IMR_MR0
#define	EXTI_IMR_IM1 EXTI_IMR_MR1
#define	EXTI_IMR_IM2 EXTI_IMR_MR2
#define	EXTI_IMR_IM3 EXTI_IMR_MR3
#define	EXTI_IMR_IM4 EXTI_IMR_MR4
#define	EXTI_IMR_IM5 EXTI_IMR_MR5
#define	EXTI_IMR_IM6 EXTI_IMR_MR6
#define	EXTI_IMR_IM7 EXTI_IMR_MR7
#define	EXTI_IMR_IM8 EXTI_IMR_MR8
#define	EXTI_IMR_IM9 EXTI_IMR_MR9
#define	EXTI_IMR_IM10 EXTI_IMR_MR10
#define	EXTI_IMR_IM11 EXTI_IMR_MR11
#define	EXTI_IMR_IM12 EXTI_IMR_MR12
#define	EXTI_IMR_IM13 EXTI_IMR_MR13
#define	EXTI_IMR_IM14 EXTI_IMR_MR14
#define	EXTI_IMR_IM15 EXTI_IMR_MR15
#define	EXTI_IMR_IM16 EXTI_IMR_MR16
#define	EXTI_IMR_IM17 EXTI_IMR_MR17
#define	EXTI_IMR_IM18 EXTI_IMR_MR18
#define	EXTI_IMR_IM19 EXTI_IMR_MR19
#define	EXTI_IMR_IM20 EXTI_IMR_MR20
#define	EXTI_IMR_IM21 EXTI_IMR_MR21
#define	EXTI_IMR_IM22 EXTI_IMR_MR22
#define	EXTI_IMR_IM_Pos (0U)
#define	EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
#define	EXTI_IMR_IM EXTI_IMR_IM_Msk
#define	EXTI_EMR_MR0_Pos (0U)
#define	EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
#define	EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
#define	EXTI_EMR_MR1_Pos (1U)
#define	EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
#define	EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
#define	EXTI_EMR_MR2_Pos (2U)
#define	EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
#define	EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
#define	EXTI_EMR_MR3_Pos (3U)
#define	EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
#define	EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
#define	EXTI_EMR_MR4_Pos (4U)
#define	EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
#define	EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
#define	EXTI_EMR_MR5_Pos (5U)
#define	EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
#define	EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
#define	EXTI_EMR_MR6_Pos (6U)
#define	EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
#define	EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
#define	EXTI_EMR_MR7_Pos (7U)
#define	EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
#define	EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
#define	EXTI_EMR_MR8_Pos (8U)
#define	EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
#define	EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
#define	EXTI_EMR_MR9_Pos (9U)
#define	EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
#define	EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
#define	EXTI_EMR_MR10_Pos (10U)
#define	EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
#define	EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
#define	EXTI_EMR_MR11_Pos (11U)
#define	EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
#define	EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
#define	EXTI_EMR_MR12_Pos (12U)
#define	EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
#define	EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
#define	EXTI_EMR_MR13_Pos (13U)
#define	EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
#define	EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
#define	EXTI_EMR_MR14_Pos (14U)
#define	EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
#define	EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
#define	EXTI_EMR_MR15_Pos (15U)
#define	EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
#define	EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
#define	EXTI_EMR_MR16_Pos (16U)
#define	EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
#define	EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
#define	EXTI_EMR_MR17_Pos (17U)
#define	EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
#define	EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
#define	EXTI_EMR_MR18_Pos (18U)
#define	EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
#define	EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
#define	EXTI_EMR_MR19_Pos (19U)
#define	EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
#define	EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
#define	EXTI_EMR_MR20_Pos (20U)
#define	EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
#define	EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
#define	EXTI_EMR_MR21_Pos (21U)
#define	EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
#define	EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
#define	EXTI_EMR_MR22_Pos (22U)
#define	EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
#define	EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
#define	EXTI_EMR_EM0 EXTI_EMR_MR0
#define	EXTI_EMR_EM1 EXTI_EMR_MR1
#define	EXTI_EMR_EM2 EXTI_EMR_MR2
#define	EXTI_EMR_EM3 EXTI_EMR_MR3
#define	EXTI_EMR_EM4 EXTI_EMR_MR4
#define	EXTI_EMR_EM5 EXTI_EMR_MR5
#define	EXTI_EMR_EM6 EXTI_EMR_MR6
#define	EXTI_EMR_EM7 EXTI_EMR_MR7
#define	EXTI_EMR_EM8 EXTI_EMR_MR8
#define	EXTI_EMR_EM9 EXTI_EMR_MR9
#define	EXTI_EMR_EM10 EXTI_EMR_MR10
#define	EXTI_EMR_EM11 EXTI_EMR_MR11
#define	EXTI_EMR_EM12 EXTI_EMR_MR12
#define	EXTI_EMR_EM13 EXTI_EMR_MR13
#define	EXTI_EMR_EM14 EXTI_EMR_MR14
#define	EXTI_EMR_EM15 EXTI_EMR_MR15
#define	EXTI_EMR_EM16 EXTI_EMR_MR16
#define	EXTI_EMR_EM17 EXTI_EMR_MR17
#define	EXTI_EMR_EM18 EXTI_EMR_MR18
#define	EXTI_EMR_EM19 EXTI_EMR_MR19
#define	EXTI_EMR_EM20 EXTI_EMR_MR20
#define	EXTI_EMR_EM21 EXTI_EMR_MR21
#define	EXTI_EMR_EM22 EXTI_EMR_MR22
#define	EXTI_RTSR_TR0_Pos (0U)
#define	EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
#define	EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
#define	EXTI_RTSR_TR1_Pos (1U)
#define	EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
#define	EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
#define	EXTI_RTSR_TR2_Pos (2U)
#define	EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
#define	EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
#define	EXTI_RTSR_TR3_Pos (3U)
#define	EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
#define	EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
#define	EXTI_RTSR_TR4_Pos (4U)
#define	EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
#define	EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
#define	EXTI_RTSR_TR5_Pos (5U)
#define	EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
#define	EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
#define	EXTI_RTSR_TR6_Pos (6U)
#define	EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
#define	EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
#define	EXTI_RTSR_TR7_Pos (7U)
#define	EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
#define	EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
#define	EXTI_RTSR_TR8_Pos (8U)
#define	EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
#define	EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
#define	EXTI_RTSR_TR9_Pos (9U)
#define	EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
#define	EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
#define	EXTI_RTSR_TR10_Pos (10U)
#define	EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
#define	EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
#define	EXTI_RTSR_TR11_Pos (11U)
#define	EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
#define	EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
#define	EXTI_RTSR_TR12_Pos (12U)
#define	EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
#define	EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
#define	EXTI_RTSR_TR13_Pos (13U)
#define	EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
#define	EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
#define	EXTI_RTSR_TR14_Pos (14U)
#define	EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
#define	EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
#define	EXTI_RTSR_TR15_Pos (15U)
#define	EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
#define	EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
#define	EXTI_RTSR_TR16_Pos (16U)
#define	EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
#define	EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
#define	EXTI_RTSR_TR17_Pos (17U)
#define	EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
#define	EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
#define	EXTI_RTSR_TR18_Pos (18U)
#define	EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
#define	EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
#define	EXTI_RTSR_TR19_Pos (19U)
#define	EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
#define	EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
#define	EXTI_RTSR_TR20_Pos (20U)
#define	EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
#define	EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
#define	EXTI_RTSR_TR21_Pos (21U)
#define	EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
#define	EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
#define	EXTI_RTSR_TR22_Pos (22U)
#define	EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
#define	EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
#define	EXTI_FTSR_TR0_Pos (0U)
#define	EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
#define	EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
#define	EXTI_FTSR_TR1_Pos (1U)
#define	EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
#define	EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
#define	EXTI_FTSR_TR2_Pos (2U)
#define	EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
#define	EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
#define	EXTI_FTSR_TR3_Pos (3U)
#define	EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
#define	EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
#define	EXTI_FTSR_TR4_Pos (4U)
#define	EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
#define	EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
#define	EXTI_FTSR_TR5_Pos (5U)
#define	EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
#define	EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
#define	EXTI_FTSR_TR6_Pos (6U)
#define	EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
#define	EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
#define	EXTI_FTSR_TR7_Pos (7U)
#define	EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
#define	EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
#define	EXTI_FTSR_TR8_Pos (8U)
#define	EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
#define	EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
#define	EXTI_FTSR_TR9_Pos (9U)
#define	EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
#define	EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
#define	EXTI_FTSR_TR10_Pos (10U)
#define	EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
#define	EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
#define	EXTI_FTSR_TR11_Pos (11U)
#define	EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
#define	EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
#define	EXTI_FTSR_TR12_Pos (12U)
#define	EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
#define	EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
#define	EXTI_FTSR_TR13_Pos (13U)
#define	EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
#define	EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
#define	EXTI_FTSR_TR14_Pos (14U)
#define	EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
#define	EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
#define	EXTI_FTSR_TR15_Pos (15U)
#define	EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
#define	EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
#define	EXTI_FTSR_TR16_Pos (16U)
#define	EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
#define	EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
#define	EXTI_FTSR_TR17_Pos (17U)
#define	EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
#define	EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
#define	EXTI_FTSR_TR18_Pos (18U)
#define	EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
#define	EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
#define	EXTI_FTSR_TR19_Pos (19U)
#define	EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
#define	EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
#define	EXTI_FTSR_TR20_Pos (20U)
#define	EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
#define	EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
#define	EXTI_FTSR_TR21_Pos (21U)
#define	EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
#define	EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
#define	EXTI_FTSR_TR22_Pos (22U)
#define	EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
#define	EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
#define	EXTI_SWIER_SWIER0_Pos (0U)
#define	EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
#define	EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
#define	EXTI_SWIER_SWIER1_Pos (1U)
#define	EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
#define	EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
#define	EXTI_SWIER_SWIER2_Pos (2U)
#define	EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
#define	EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
#define	EXTI_SWIER_SWIER3_Pos (3U)
#define	EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
#define	EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
#define	EXTI_SWIER_SWIER4_Pos (4U)
#define	EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
#define	EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
#define	EXTI_SWIER_SWIER5_Pos (5U)
#define	EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
#define	EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
#define	EXTI_SWIER_SWIER6_Pos (6U)
#define	EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
#define	EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
#define	EXTI_SWIER_SWIER7_Pos (7U)
#define	EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
#define	EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
#define	EXTI_SWIER_SWIER8_Pos (8U)
#define	EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
#define	EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
#define	EXTI_SWIER_SWIER9_Pos (9U)
#define	EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
#define	EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
#define	EXTI_SWIER_SWIER10_Pos (10U)
#define	EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
#define	EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
#define	EXTI_SWIER_SWIER11_Pos (11U)
#define	EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
#define	EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
#define	EXTI_SWIER_SWIER12_Pos (12U)
#define	EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
#define	EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
#define	EXTI_SWIER_SWIER13_Pos (13U)
#define	EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
#define	EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
#define	EXTI_SWIER_SWIER14_Pos (14U)
#define	EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
#define	EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
#define	EXTI_SWIER_SWIER15_Pos (15U)
#define	EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
#define	EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
#define	EXTI_SWIER_SWIER16_Pos (16U)
#define	EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
#define	EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
#define	EXTI_SWIER_SWIER17_Pos (17U)
#define	EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
#define	EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
#define	EXTI_SWIER_SWIER18_Pos (18U)
#define	EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
#define	EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
#define	EXTI_SWIER_SWIER19_Pos (19U)
#define	EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
#define	EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
#define	EXTI_SWIER_SWIER20_Pos (20U)
#define	EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
#define	EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
#define	EXTI_SWIER_SWIER21_Pos (21U)
#define	EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
#define	EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
#define	EXTI_SWIER_SWIER22_Pos (22U)
#define	EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
#define	EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
#define	EXTI_PR_PR0_Pos (0U)
#define	EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
#define	EXTI_PR_PR0 EXTI_PR_PR0_Msk
#define	EXTI_PR_PR1_Pos (1U)
#define	EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
#define	EXTI_PR_PR1 EXTI_PR_PR1_Msk
#define	EXTI_PR_PR2_Pos (2U)
#define	EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
#define	EXTI_PR_PR2 EXTI_PR_PR2_Msk
#define	EXTI_PR_PR3_Pos (3U)
#define	EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
#define	EXTI_PR_PR3 EXTI_PR_PR3_Msk
#define	EXTI_PR_PR4_Pos (4U)
#define	EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
#define	EXTI_PR_PR4 EXTI_PR_PR4_Msk
#define	EXTI_PR_PR5_Pos (5U)
#define	EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
#define	EXTI_PR_PR5 EXTI_PR_PR5_Msk
#define	EXTI_PR_PR6_Pos (6U)
#define	EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
#define	EXTI_PR_PR6 EXTI_PR_PR6_Msk
#define	EXTI_PR_PR7_Pos (7U)
#define	EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
#define	EXTI_PR_PR7 EXTI_PR_PR7_Msk
#define	EXTI_PR_PR8_Pos (8U)
#define	EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
#define	EXTI_PR_PR8 EXTI_PR_PR8_Msk
#define	EXTI_PR_PR9_Pos (9U)
#define	EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
#define	EXTI_PR_PR9 EXTI_PR_PR9_Msk
#define	EXTI_PR_PR10_Pos (10U)
#define	EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
#define	EXTI_PR_PR10 EXTI_PR_PR10_Msk
#define	EXTI_PR_PR11_Pos (11U)
#define	EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
#define	EXTI_PR_PR11 EXTI_PR_PR11_Msk
#define	EXTI_PR_PR12_Pos (12U)
#define	EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
#define	EXTI_PR_PR12 EXTI_PR_PR12_Msk
#define	EXTI_PR_PR13_Pos (13U)
#define	EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
#define	EXTI_PR_PR13 EXTI_PR_PR13_Msk
#define	EXTI_PR_PR14_Pos (14U)
#define	EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
#define	EXTI_PR_PR14 EXTI_PR_PR14_Msk
#define	EXTI_PR_PR15_Pos (15U)
#define	EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
#define	EXTI_PR_PR15 EXTI_PR_PR15_Msk
#define	EXTI_PR_PR16_Pos (16U)
#define	EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
#define	EXTI_PR_PR16 EXTI_PR_PR16_Msk
#define	EXTI_PR_PR17_Pos (17U)
#define	EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
#define	EXTI_PR_PR17 EXTI_PR_PR17_Msk
#define	EXTI_PR_PR18_Pos (18U)
#define	EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
#define	EXTI_PR_PR18 EXTI_PR_PR18_Msk
#define	EXTI_PR_PR19_Pos (19U)
#define	EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
#define	EXTI_PR_PR19 EXTI_PR_PR19_Msk
#define	EXTI_PR_PR20_Pos (20U)
#define	EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
#define	EXTI_PR_PR20 EXTI_PR_PR20_Msk
#define	EXTI_PR_PR21_Pos (21U)
#define	EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
#define	EXTI_PR_PR21 EXTI_PR_PR21_Msk
#define	EXTI_PR_PR22_Pos (22U)
#define	EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
#define	EXTI_PR_PR22 EXTI_PR_PR22_Msk
#define	FLASH_ACR_LATENCY_Pos (0U)
#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define	FLASH_ACR_LATENCY_0WS 0x00000000U
#define	FLASH_ACR_LATENCY_1WS 0x00000001U
#define	FLASH_ACR_LATENCY_2WS 0x00000002U
#define	FLASH_ACR_LATENCY_3WS 0x00000003U
#define	FLASH_ACR_LATENCY_4WS 0x00000004U
#define	FLASH_ACR_LATENCY_5WS 0x00000005U
#define	FLASH_ACR_LATENCY_6WS 0x00000006U
#define	FLASH_ACR_LATENCY_7WS 0x00000007U
#define	FLASH_ACR_PRFTEN_Pos (8U)
#define	FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
#define	FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define	FLASH_ACR_ICEN_Pos (9U)
#define	FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
#define	FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define	FLASH_ACR_DCEN_Pos (10U)
#define	FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
#define	FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define	FLASH_ACR_ICRST_Pos (11U)
#define	FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
#define	FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define	FLASH_ACR_DCRST_Pos (12U)
#define	FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
#define	FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define	FLASH_SR_EOP_Pos (0U)
#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
#define	FLASH_SR_EOP FLASH_SR_EOP_Msk
#define	FLASH_SR_OPERR_Pos (1U)
#define	FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
#define	FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define	FLASH_SR_WRPERR_Pos (4U)
#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define	FLASH_SR_PGAERR_Pos (5U)
#define	FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
#define	FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define	FLASH_SR_PGPERR_Pos (6U)
#define	FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
#define	FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
#define	FLASH_SR_PGSERR_Pos (7U)
#define	FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
#define	FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define	FLASH_SR_BSY_Pos (16U)
#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
#define	FLASH_SR_BSY FLASH_SR_BSY_Msk
#define	FLASH_CR_PG_Pos (0U)
#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
#define	FLASH_CR_PG FLASH_CR_PG_Msk
#define	FLASH_CR_SER_Pos (1U)
#define	FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
#define	FLASH_CR_SER FLASH_CR_SER_Msk
#define	FLASH_CR_MER_Pos (2U)
#define	FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
#define	FLASH_CR_MER FLASH_CR_MER_Msk
#define	FLASH_CR_SNB_Pos (3U)
#define	FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos)
#define	FLASH_CR_SNB FLASH_CR_SNB_Msk
#define	FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
#define	FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
#define	FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
#define	FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
#define	FLASH_CR_PSIZE_Pos (8U)
#define	FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
#define	FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
#define	FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
#define	FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
#define	FLASH_CR_STRT_Pos (16U)
#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
#define	FLASH_CR_STRT FLASH_CR_STRT_Msk
#define	FLASH_CR_EOPIE_Pos (24U)
#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define	FLASH_CR_ERRIE_Pos (25U)
#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define	FLASH_CR_LOCK_Pos (31U)
#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk
#define	FLASH_OPTCR_OPTLOCK_Pos (0U)
#define	FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
#define	FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
#define	FLASH_OPTCR_OPTSTRT_Pos (1U)
#define	FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
#define	FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
#define	FLASH_OPTCR_BOR_LEV_0 0x00000004U
#define	FLASH_OPTCR_BOR_LEV_1 0x00000008U
#define	FLASH_OPTCR_BOR_LEV_Pos (2U)
#define	FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
#define	FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
#define	FLASH_OPTCR_WDG_SW_Pos (5U)
#define	FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
#define	FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
#define	FLASH_OPTCR_nRST_STOP_Pos (6U)
#define	FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
#define	FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
#define	FLASH_OPTCR_nRST_STDBY_Pos (7U)
#define	FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
#define	FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
#define	FLASH_OPTCR_RDP_Pos (8U)
#define	FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
#define	FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
#define	FLASH_OPTCR_nWRP_Pos (16U)
#define	FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
#define	FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
#define	FLASH_OPTCR_nWRP_0 0x00010000U
#define	FLASH_OPTCR_nWRP_1 0x00020000U
#define	FLASH_OPTCR_nWRP_2 0x00040000U
#define	FLASH_OPTCR_nWRP_3 0x00080000U
#define	FLASH_OPTCR_nWRP_4 0x00100000U
#define	FLASH_OPTCR_nWRP_5 0x00200000U
#define	FLASH_OPTCR_nWRP_6 0x00400000U
#define	FLASH_OPTCR_nWRP_7 0x00800000U
#define	FLASH_OPTCR_nWRP_8 0x01000000U
#define	FLASH_OPTCR_nWRP_9 0x02000000U
#define	FLASH_OPTCR_nWRP_10 0x04000000U
#define	FLASH_OPTCR_nWRP_11 0x08000000U
#define	FLASH_OPTCR1_nWRP_Pos (16U)
#define	FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
#define	FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
#define	FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
#define	FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
#define	FLASH_SR_SOP FLASH_SR_OPERR
#define	FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
#define	FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
#define	FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
#define	FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
#define	FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
#define	FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
#define	FSMC_BCR1_MBKEN_Pos (0U)
#define	FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
#define	FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
#define	FSMC_BCR1_MUXEN_Pos (1U)
#define	FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
#define	FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
#define	FSMC_BCR1_MTYP_Pos (2U)
#define	FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
#define	FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
#define	FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
#define	FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
#define	FSMC_BCR1_MWID_Pos (4U)
#define	FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
#define	FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
#define	FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
#define	FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
#define	FSMC_BCR1_FACCEN_Pos (6U)
#define	FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
#define	FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
#define	FSMC_BCR1_BURSTEN_Pos (8U)
#define	FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
#define	FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
#define	FSMC_BCR1_WAITPOL_Pos (9U)
#define	FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
#define	FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
#define	FSMC_BCR1_WRAPMOD_Pos (10U)
#define	FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
#define	FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
#define	FSMC_BCR1_WAITCFG_Pos (11U)
#define	FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
#define	FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
#define	FSMC_BCR1_WREN_Pos (12U)
#define	FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
#define	FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
#define	FSMC_BCR1_WAITEN_Pos (13U)
#define	FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
#define	FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
#define	FSMC_BCR1_EXTMOD_Pos (14U)
#define	FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
#define	FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
#define	FSMC_BCR1_ASYNCWAIT_Pos (15U)
#define	FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
#define	FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
#define	FSMC_BCR1_CPSIZE_Pos (16U)
#define	FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
#define	FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
#define	FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
#define	FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
#define	FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
#define	FSMC_BCR1_CBURSTRW_Pos (19U)
#define	FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
#define	FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
#define	FSMC_BCR2_MBKEN_Pos (0U)
#define	FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
#define	FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
#define	FSMC_BCR2_MUXEN_Pos (1U)
#define	FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
#define	FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
#define	FSMC_BCR2_MTYP_Pos (2U)
#define	FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
#define	FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
#define	FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
#define	FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
#define	FSMC_BCR2_MWID_Pos (4U)
#define	FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
#define	FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
#define	FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
#define	FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
#define	FSMC_BCR2_FACCEN_Pos (6U)
#define	FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
#define	FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
#define	FSMC_BCR2_BURSTEN_Pos (8U)
#define	FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
#define	FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
#define	FSMC_BCR2_WAITPOL_Pos (9U)
#define	FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
#define	FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
#define	FSMC_BCR2_WRAPMOD_Pos (10U)
#define	FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
#define	FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
#define	FSMC_BCR2_WAITCFG_Pos (11U)
#define	FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
#define	FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
#define	FSMC_BCR2_WREN_Pos (12U)
#define	FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
#define	FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
#define	FSMC_BCR2_WAITEN_Pos (13U)
#define	FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
#define	FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
#define	FSMC_BCR2_EXTMOD_Pos (14U)
#define	FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
#define	FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
#define	FSMC_BCR2_ASYNCWAIT_Pos (15U)
#define	FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
#define	FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
#define	FSMC_BCR2_CPSIZE_Pos (16U)
#define	FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
#define	FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
#define	FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
#define	FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
#define	FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
#define	FSMC_BCR2_CBURSTRW_Pos (19U)
#define	FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
#define	FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
#define	FSMC_BCR3_MBKEN_Pos (0U)
#define	FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
#define	FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
#define	FSMC_BCR3_MUXEN_Pos (1U)
#define	FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
#define	FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
#define	FSMC_BCR3_MTYP_Pos (2U)
#define	FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
#define	FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
#define	FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
#define	FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
#define	FSMC_BCR3_MWID_Pos (4U)
#define	FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
#define	FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
#define	FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
#define	FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
#define	FSMC_BCR3_FACCEN_Pos (6U)
#define	FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
#define	FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
#define	FSMC_BCR3_BURSTEN_Pos (8U)
#define	FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
#define	FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
#define	FSMC_BCR3_WAITPOL_Pos (9U)
#define	FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
#define	FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
#define	FSMC_BCR3_WRAPMOD_Pos (10U)
#define	FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
#define	FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
#define	FSMC_BCR3_WAITCFG_Pos (11U)
#define	FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
#define	FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
#define	FSMC_BCR3_WREN_Pos (12U)
#define	FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
#define	FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
#define	FSMC_BCR3_WAITEN_Pos (13U)
#define	FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
#define	FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
#define	FSMC_BCR3_EXTMOD_Pos (14U)
#define	FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
#define	FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
#define	FSMC_BCR3_ASYNCWAIT_Pos (15U)
#define	FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
#define	FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
#define	FSMC_BCR3_CPSIZE_Pos (16U)
#define	FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
#define	FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
#define	FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
#define	FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
#define	FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
#define	FSMC_BCR3_CBURSTRW_Pos (19U)
#define	FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
#define	FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
#define	FSMC_BCR4_MBKEN_Pos (0U)
#define	FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
#define	FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
#define	FSMC_BCR4_MUXEN_Pos (1U)
#define	FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
#define	FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
#define	FSMC_BCR4_MTYP_Pos (2U)
#define	FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
#define	FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
#define	FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
#define	FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
#define	FSMC_BCR4_MWID_Pos (4U)
#define	FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
#define	FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
#define	FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
#define	FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
#define	FSMC_BCR4_FACCEN_Pos (6U)
#define	FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
#define	FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
#define	FSMC_BCR4_BURSTEN_Pos (8U)
#define	FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
#define	FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
#define	FSMC_BCR4_WAITPOL_Pos (9U)
#define	FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
#define	FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
#define	FSMC_BCR4_WRAPMOD_Pos (10U)
#define	FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
#define	FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
#define	FSMC_BCR4_WAITCFG_Pos (11U)
#define	FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
#define	FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
#define	FSMC_BCR4_WREN_Pos (12U)
#define	FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
#define	FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
#define	FSMC_BCR4_WAITEN_Pos (13U)
#define	FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
#define	FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
#define	FSMC_BCR4_EXTMOD_Pos (14U)
#define	FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
#define	FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
#define	FSMC_BCR4_ASYNCWAIT_Pos (15U)
#define	FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
#define	FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
#define	FSMC_BCR4_CPSIZE_Pos (16U)
#define	FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
#define	FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
#define	FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
#define	FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
#define	FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
#define	FSMC_BCR4_CBURSTRW_Pos (19U)
#define	FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
#define	FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
#define	FSMC_BTR1_ADDSET_Pos (0U)
#define	FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
#define	FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
#define	FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
#define	FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
#define	FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
#define	FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
#define	FSMC_BTR1_ADDHLD_Pos (4U)
#define	FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
#define	FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
#define	FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
#define	FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
#define	FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
#define	FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
#define	FSMC_BTR1_DATAST_Pos (8U)
#define	FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
#define	FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
#define	FSMC_BTR1_BUSTURN_Pos (16U)
#define	FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
#define	FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
#define	FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
#define	FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
#define	FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
#define	FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
#define	FSMC_BTR1_CLKDIV_Pos (20U)
#define	FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
#define	FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
#define	FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
#define	FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
#define	FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
#define	FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
#define	FSMC_BTR1_DATLAT_Pos (24U)
#define	FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
#define	FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
#define	FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
#define	FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
#define	FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
#define	FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
#define	FSMC_BTR1_ACCMOD_Pos (28U)
#define	FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
#define	FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
#define	FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
#define	FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
#define	FSMC_BTR2_ADDSET_Pos (0U)
#define	FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
#define	FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
#define	FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
#define	FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
#define	FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
#define	FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
#define	FSMC_BTR2_ADDHLD_Pos (4U)
#define	FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
#define	FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
#define	FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
#define	FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
#define	FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
#define	FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
#define	FSMC_BTR2_DATAST_Pos (8U)
#define	FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
#define	FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
#define	FSMC_BTR2_BUSTURN_Pos (16U)
#define	FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
#define	FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
#define	FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
#define	FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
#define	FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
#define	FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
#define	FSMC_BTR2_CLKDIV_Pos (20U)
#define	FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
#define	FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
#define	FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
#define	FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
#define	FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
#define	FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
#define	FSMC_BTR2_DATLAT_Pos (24U)
#define	FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
#define	FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
#define	FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
#define	FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
#define	FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
#define	FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
#define	FSMC_BTR2_ACCMOD_Pos (28U)
#define	FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
#define	FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
#define	FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
#define	FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
#define	FSMC_BTR3_ADDSET_Pos (0U)
#define	FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
#define	FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
#define	FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
#define	FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
#define	FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
#define	FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
#define	FSMC_BTR3_ADDHLD_Pos (4U)
#define	FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
#define	FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
#define	FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
#define	FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
#define	FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
#define	FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
#define	FSMC_BTR3_DATAST_Pos (8U)
#define	FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
#define	FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
#define	FSMC_BTR3_BUSTURN_Pos (16U)
#define	FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
#define	FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
#define	FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
#define	FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
#define	FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
#define	FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
#define	FSMC_BTR3_CLKDIV_Pos (20U)
#define	FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
#define	FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
#define	FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
#define	FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
#define	FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
#define	FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
#define	FSMC_BTR3_DATLAT_Pos (24U)
#define	FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
#define	FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
#define	FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
#define	FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
#define	FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
#define	FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
#define	FSMC_BTR3_ACCMOD_Pos (28U)
#define	FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
#define	FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
#define	FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
#define	FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
#define	FSMC_BTR4_ADDSET_Pos (0U)
#define	FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
#define	FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
#define	FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
#define	FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
#define	FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
#define	FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
#define	FSMC_BTR4_ADDHLD_Pos (4U)
#define	FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
#define	FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
#define	FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
#define	FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
#define	FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
#define	FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
#define	FSMC_BTR4_DATAST_Pos (8U)
#define	FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
#define	FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
#define	FSMC_BTR4_BUSTURN_Pos (16U)
#define	FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
#define	FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
#define	FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
#define	FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
#define	FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
#define	FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
#define	FSMC_BTR4_CLKDIV_Pos (20U)
#define	FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
#define	FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
#define	FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
#define	FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
#define	FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
#define	FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
#define	FSMC_BTR4_DATLAT_Pos (24U)
#define	FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
#define	FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
#define	FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
#define	FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
#define	FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
#define	FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
#define	FSMC_BTR4_ACCMOD_Pos (28U)
#define	FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
#define	FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
#define	FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
#define	FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
#define	FSMC_BWTR1_ADDSET_Pos (0U)
#define	FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
#define	FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
#define	FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
#define	FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
#define	FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
#define	FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
#define	FSMC_BWTR1_ADDHLD_Pos (4U)
#define	FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
#define	FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
#define	FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
#define	FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
#define	FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
#define	FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
#define	FSMC_BWTR1_DATAST_Pos (8U)
#define	FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
#define	FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
#define	FSMC_BWTR1_BUSTURN_Pos (16U)
#define	FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
#define	FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
#define	FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
#define	FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
#define	FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
#define	FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
#define	FSMC_BWTR1_ACCMOD_Pos (28U)
#define	FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
#define	FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
#define	FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
#define	FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
#define	FSMC_BWTR2_ADDSET_Pos (0U)
#define	FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
#define	FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
#define	FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
#define	FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
#define	FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
#define	FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
#define	FSMC_BWTR2_ADDHLD_Pos (4U)
#define	FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
#define	FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
#define	FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
#define	FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
#define	FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
#define	FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
#define	FSMC_BWTR2_DATAST_Pos (8U)
#define	FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
#define	FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
#define	FSMC_BWTR2_BUSTURN_Pos (16U)
#define	FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
#define	FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
#define	FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
#define	FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
#define	FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
#define	FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
#define	FSMC_BWTR2_ACCMOD_Pos (28U)
#define	FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
#define	FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
#define	FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
#define	FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
#define	FSMC_BWTR3_ADDSET_Pos (0U)
#define	FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
#define	FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
#define	FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
#define	FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
#define	FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
#define	FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
#define	FSMC_BWTR3_ADDHLD_Pos (4U)
#define	FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
#define	FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
#define	FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
#define	FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
#define	FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
#define	FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
#define	FSMC_BWTR3_DATAST_Pos (8U)
#define	FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
#define	FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
#define	FSMC_BWTR3_BUSTURN_Pos (16U)
#define	FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
#define	FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
#define	FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
#define	FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
#define	FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
#define	FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
#define	FSMC_BWTR3_ACCMOD_Pos (28U)
#define	FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
#define	FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
#define	FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
#define	FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
#define	FSMC_BWTR4_ADDSET_Pos (0U)
#define	FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
#define	FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
#define	FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
#define	FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
#define	FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
#define	FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
#define	FSMC_BWTR4_ADDHLD_Pos (4U)
#define	FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
#define	FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
#define	FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
#define	FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
#define	FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
#define	FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
#define	FSMC_BWTR4_DATAST_Pos (8U)
#define	FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
#define	FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
#define	FSMC_BWTR4_DATAST_0 0x00000100U
#define	FSMC_BWTR4_DATAST_1 0x00000200U
#define	FSMC_BWTR4_DATAST_2 0x00000400U
#define	FSMC_BWTR4_DATAST_3 0x00000800U
#define	FSMC_BWTR4_DATAST_4 0x00001000U
#define	FSMC_BWTR4_DATAST_5 0x00002000U
#define	FSMC_BWTR4_DATAST_6 0x00004000U
#define	FSMC_BWTR4_DATAST_7 0x00008000U
#define	FSMC_BWTR4_BUSTURN_Pos (16U)
#define	FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
#define	FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
#define	FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
#define	FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
#define	FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
#define	FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
#define	FSMC_BWTR4_ACCMOD_Pos (28U)
#define	FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
#define	FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
#define	FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
#define	FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
#define	FSMC_PCR2_PWAITEN_Pos (1U)
#define	FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
#define	FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
#define	FSMC_PCR2_PBKEN_Pos (2U)
#define	FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
#define	FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
#define	FSMC_PCR2_PTYP_Pos (3U)
#define	FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
#define	FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
#define	FSMC_PCR2_PWID_Pos (4U)
#define	FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
#define	FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
#define	FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
#define	FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
#define	FSMC_PCR2_ECCEN_Pos (6U)
#define	FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
#define	FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
#define	FSMC_PCR2_TCLR_Pos (9U)
#define	FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
#define	FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
#define	FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
#define	FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
#define	FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
#define	FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
#define	FSMC_PCR2_TAR_Pos (13U)
#define	FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
#define	FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
#define	FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
#define	FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
#define	FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
#define	FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
#define	FSMC_PCR2_ECCPS_Pos (17U)
#define	FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
#define	FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
#define	FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
#define	FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
#define	FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
#define	FSMC_PCR3_PWAITEN_Pos (1U)
#define	FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
#define	FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
#define	FSMC_PCR3_PBKEN_Pos (2U)
#define	FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
#define	FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
#define	FSMC_PCR3_PTYP_Pos (3U)
#define	FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
#define	FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
#define	FSMC_PCR3_PWID_Pos (4U)
#define	FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
#define	FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
#define	FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
#define	FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
#define	FSMC_PCR3_ECCEN_Pos (6U)
#define	FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
#define	FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
#define	FSMC_PCR3_TCLR_Pos (9U)
#define	FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
#define	FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
#define	FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
#define	FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
#define	FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
#define	FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
#define	FSMC_PCR3_TAR_Pos (13U)
#define	FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
#define	FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
#define	FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
#define	FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
#define	FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
#define	FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
#define	FSMC_PCR3_ECCPS_Pos (17U)
#define	FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
#define	FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
#define	FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
#define	FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
#define	FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
#define	FSMC_PCR4_PWAITEN_Pos (1U)
#define	FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
#define	FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
#define	FSMC_PCR4_PBKEN_Pos (2U)
#define	FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
#define	FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
#define	FSMC_PCR4_PTYP_Pos (3U)
#define	FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
#define	FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
#define	FSMC_PCR4_PWID_Pos (4U)
#define	FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
#define	FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
#define	FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
#define	FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
#define	FSMC_PCR4_ECCEN_Pos (6U)
#define	FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
#define	FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
#define	FSMC_PCR4_TCLR_Pos (9U)
#define	FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
#define	FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
#define	FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
#define	FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
#define	FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
#define	FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
#define	FSMC_PCR4_TAR_Pos (13U)
#define	FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
#define	FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
#define	FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
#define	FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
#define	FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
#define	FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
#define	FSMC_PCR4_ECCPS_Pos (17U)
#define	FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
#define	FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
#define	FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
#define	FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
#define	FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
#define	FSMC_SR2_IRS_Pos (0U)
#define	FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
#define	FSMC_SR2_IRS FSMC_SR2_IRS_Msk
#define	FSMC_SR2_ILS_Pos (1U)
#define	FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
#define	FSMC_SR2_ILS FSMC_SR2_ILS_Msk
#define	FSMC_SR2_IFS_Pos (2U)
#define	FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
#define	FSMC_SR2_IFS FSMC_SR2_IFS_Msk
#define	FSMC_SR2_IREN_Pos (3U)
#define	FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
#define	FSMC_SR2_IREN FSMC_SR2_IREN_Msk
#define	FSMC_SR2_ILEN_Pos (4U)
#define	FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
#define	FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
#define	FSMC_SR2_IFEN_Pos (5U)
#define	FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
#define	FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
#define	FSMC_SR2_FEMPT_Pos (6U)
#define	FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
#define	FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
#define	FSMC_SR3_IRS_Pos (0U)
#define	FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
#define	FSMC_SR3_IRS FSMC_SR3_IRS_Msk
#define	FSMC_SR3_ILS_Pos (1U)
#define	FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
#define	FSMC_SR3_ILS FSMC_SR3_ILS_Msk
#define	FSMC_SR3_IFS_Pos (2U)
#define	FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
#define	FSMC_SR3_IFS FSMC_SR3_IFS_Msk
#define	FSMC_SR3_IREN_Pos (3U)
#define	FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
#define	FSMC_SR3_IREN FSMC_SR3_IREN_Msk
#define	FSMC_SR3_ILEN_Pos (4U)
#define	FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
#define	FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
#define	FSMC_SR3_IFEN_Pos (5U)
#define	FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
#define	FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
#define	FSMC_SR3_FEMPT_Pos (6U)
#define	FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
#define	FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
#define	FSMC_SR4_IRS_Pos (0U)
#define	FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
#define	FSMC_SR4_IRS FSMC_SR4_IRS_Msk
#define	FSMC_SR4_ILS_Pos (1U)
#define	FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
#define	FSMC_SR4_ILS FSMC_SR4_ILS_Msk
#define	FSMC_SR4_IFS_Pos (2U)
#define	FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
#define	FSMC_SR4_IFS FSMC_SR4_IFS_Msk
#define	FSMC_SR4_IREN_Pos (3U)
#define	FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
#define	FSMC_SR4_IREN FSMC_SR4_IREN_Msk
#define	FSMC_SR4_ILEN_Pos (4U)
#define	FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
#define	FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
#define	FSMC_SR4_IFEN_Pos (5U)
#define	FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
#define	FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
#define	FSMC_SR4_FEMPT_Pos (6U)
#define	FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
#define	FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
#define	FSMC_PMEM2_MEMSET2_Pos (0U)
#define	FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
#define	FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_Pos (8U)
#define	FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
#define	FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_Pos (16U)
#define	FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
#define	FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_Pos (24U)
#define	FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
#define	FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
#define	FSMC_PMEM3_MEMSET3_Pos (0U)
#define	FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
#define	FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_Pos (8U)
#define	FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
#define	FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_Pos (16U)
#define	FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
#define	FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_Pos (24U)
#define	FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
#define	FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
#define	FSMC_PMEM4_MEMSET4_Pos (0U)
#define	FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
#define	FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_Pos (8U)
#define	FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
#define	FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_Pos (16U)
#define	FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
#define	FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_Pos (24U)
#define	FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
#define	FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
#define	FSMC_PATT2_ATTSET2_Pos (0U)
#define	FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
#define	FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
#define	FSMC_PATT2_ATTWAIT2_Pos (8U)
#define	FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
#define	FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
#define	FSMC_PATT2_ATTHOLD2_Pos (16U)
#define	FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
#define	FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
#define	FSMC_PATT2_ATTHIZ2_Pos (24U)
#define	FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
#define	FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
#define	FSMC_PATT3_ATTSET3_Pos (0U)
#define	FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
#define	FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
#define	FSMC_PATT3_ATTWAIT3_Pos (8U)
#define	FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
#define	FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
#define	FSMC_PATT3_ATTHOLD3_Pos (16U)
#define	FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
#define	FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
#define	FSMC_PATT3_ATTHIZ3_Pos (24U)
#define	FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
#define	FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
#define	FSMC_PATT4_ATTSET4_Pos (0U)
#define	FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
#define	FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
#define	FSMC_PATT4_ATTWAIT4_Pos (8U)
#define	FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
#define	FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
#define	FSMC_PATT4_ATTHOLD4_Pos (16U)
#define	FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
#define	FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
#define	FSMC_PATT4_ATTHIZ4_Pos (24U)
#define	FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
#define	FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
#define	FSMC_PIO4_IOSET4_Pos (0U)
#define	FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
#define	FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
#define	FSMC_PIO4_IOWAIT4_Pos (8U)
#define	FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
#define	FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
#define	FSMC_PIO4_IOHOLD4_Pos (16U)
#define	FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
#define	FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
#define	FSMC_PIO4_IOHIZ4_Pos (24U)
#define	FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
#define	FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
#define	FSMC_ECCR2_ECC2_Pos (0U)
#define	FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
#define	FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
#define	FSMC_ECCR3_ECC3_Pos (0U)
#define	FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
#define	FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
#define	GPIO_MODER_MODER0_Pos (0U)
#define	GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
#define	GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
#define	GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
#define	GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
#define	GPIO_MODER_MODER1_Pos (2U)
#define	GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
#define	GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
#define	GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
#define	GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
#define	GPIO_MODER_MODER2_Pos (4U)
#define	GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
#define	GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
#define	GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
#define	GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
#define	GPIO_MODER_MODER3_Pos (6U)
#define	GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
#define	GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
#define	GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
#define	GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
#define	GPIO_MODER_MODER4_Pos (8U)
#define	GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
#define	GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
#define	GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
#define	GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
#define	GPIO_MODER_MODER5_Pos (10U)
#define	GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
#define	GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
#define	GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
#define	GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
#define	GPIO_MODER_MODER6_Pos (12U)
#define	GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
#define	GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
#define	GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
#define	GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
#define	GPIO_MODER_MODER7_Pos (14U)
#define	GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
#define	GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
#define	GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
#define	GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
#define	GPIO_MODER_MODER8_Pos (16U)
#define	GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
#define	GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
#define	GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
#define	GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
#define	GPIO_MODER_MODER9_Pos (18U)
#define	GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
#define	GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
#define	GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
#define	GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
#define	GPIO_MODER_MODER10_Pos (20U)
#define	GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
#define	GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
#define	GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
#define	GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
#define	GPIO_MODER_MODER11_Pos (22U)
#define	GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
#define	GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
#define	GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
#define	GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
#define	GPIO_MODER_MODER12_Pos (24U)
#define	GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
#define	GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
#define	GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
#define	GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
#define	GPIO_MODER_MODER13_Pos (26U)
#define	GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
#define	GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
#define	GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
#define	GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
#define	GPIO_MODER_MODER14_Pos (28U)
#define	GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
#define	GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
#define	GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
#define	GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
#define	GPIO_MODER_MODER15_Pos (30U)
#define	GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
#define	GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
#define	GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
#define	GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
#define	GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
#define	GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
#define	GPIO_MODER_MODE0 GPIO_MODER_MODER0
#define	GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
#define	GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
#define	GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
#define	GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
#define	GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define	GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define	GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define	GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define	GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define	GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define	GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
#define	GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
#define	GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
#define	GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
#define	GPIO_MODER_MODE3 GPIO_MODER_MODER3
#define	GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
#define	GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
#define	GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
#define	GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
#define	GPIO_MODER_MODE4 GPIO_MODER_MODER4
#define	GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
#define	GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
#define	GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
#define	GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
#define	GPIO_MODER_MODE5 GPIO_MODER_MODER5
#define	GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
#define	GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
#define	GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
#define	GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
#define	GPIO_MODER_MODE6 GPIO_MODER_MODER6
#define	GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
#define	GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
#define	GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
#define	GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
#define	GPIO_MODER_MODE7 GPIO_MODER_MODER7
#define	GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define	GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define	GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define	GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define	GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define	GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define	GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
#define	GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
#define	GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
#define	GPIO_MODER_MODE9 GPIO_MODER_MODER9
#define	GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
#define	GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
#define	GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
#define	GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
#define	GPIO_MODER_MODE10 GPIO_MODER_MODER10
#define	GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
#define	GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
#define	GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
#define	GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
#define	GPIO_MODER_MODE11 GPIO_MODER_MODER11
#define	GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
#define	GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
#define	GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
#define	GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
#define	GPIO_MODER_MODE12 GPIO_MODER_MODER12
#define	GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
#define	GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
#define	GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
#define	GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
#define	GPIO_MODER_MODE13 GPIO_MODER_MODER13
#define	GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
#define	GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
#define	GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
#define	GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
#define	GPIO_MODER_MODE14 GPIO_MODER_MODER14
#define	GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
#define	GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
#define	GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
#define	GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
#define	GPIO_MODER_MODE15 GPIO_MODER_MODER15
#define	GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
#define	GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
#define	GPIO_OTYPER_OT0_Pos (0U)
#define	GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
#define	GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define	GPIO_OTYPER_OT1_Pos (1U)
#define	GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
#define	GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define	GPIO_OTYPER_OT2_Pos (2U)
#define	GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
#define	GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define	GPIO_OTYPER_OT3_Pos (3U)
#define	GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
#define	GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define	GPIO_OTYPER_OT4_Pos (4U)
#define	GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
#define	GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define	GPIO_OTYPER_OT5_Pos (5U)
#define	GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
#define	GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define	GPIO_OTYPER_OT6_Pos (6U)
#define	GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
#define	GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define	GPIO_OTYPER_OT7_Pos (7U)
#define	GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
#define	GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define	GPIO_OTYPER_OT8_Pos (8U)
#define	GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
#define	GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define	GPIO_OTYPER_OT9_Pos (9U)
#define	GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
#define	GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define	GPIO_OTYPER_OT10_Pos (10U)
#define	GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
#define	GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define	GPIO_OTYPER_OT11_Pos (11U)
#define	GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
#define	GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define	GPIO_OTYPER_OT12_Pos (12U)
#define	GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
#define	GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define	GPIO_OTYPER_OT13_Pos (13U)
#define	GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
#define	GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define	GPIO_OTYPER_OT14_Pos (14U)
#define	GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
#define	GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define	GPIO_OTYPER_OT15_Pos (15U)
#define	GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
#define	GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
#define	GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define	GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define	GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define	GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define	GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define	GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define	GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define	GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define	GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define	GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define	GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define	GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define	GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define	GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define	GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define	GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
#define	GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define	GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
#define	GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define	GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
#define	GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
#define	GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define	GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
#define	GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define	GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
#define	GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
#define	GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define	GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
#define	GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define	GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
#define	GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
#define	GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define	GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
#define	GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define	GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
#define	GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
#define	GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define	GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
#define	GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define	GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
#define	GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
#define	GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define	GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
#define	GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define	GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
#define	GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
#define	GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define	GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
#define	GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define	GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
#define	GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
#define	GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define	GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
#define	GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define	GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
#define	GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
#define	GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define	GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
#define	GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define	GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
#define	GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
#define	GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define	GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
#define	GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define	GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
#define	GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
#define	GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define	GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
#define	GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define	GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
#define	GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
#define	GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define	GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
#define	GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define	GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
#define	GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
#define	GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define	GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
#define	GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define	GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
#define	GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
#define	GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define	GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
#define	GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define	GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
#define	GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
#define	GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define	GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
#define	GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define	GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
#define	GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
#define	GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define	GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
#define	GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define	GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
#define	GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
#define	GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define	GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define	GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define	GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define	GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define	GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define	GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define	GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define	GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define	GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define	GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define	GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define	GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define	GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define	GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define	GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define	GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define	GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define	GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define	GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define	GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define	GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define	GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define	GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define	GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define	GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define	GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define	GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define	GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define	GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define	GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define	GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define	GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define	GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define	GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define	GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define	GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define	GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define	GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define	GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define	GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define	GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define	GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define	GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define	GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define	GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define	GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define	GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
#define	GPIO_PUPDR_PUPD0_Pos (0U)
#define	GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
#define	GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define	GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
#define	GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
#define	GPIO_PUPDR_PUPD1_Pos (2U)
#define	GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
#define	GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define	GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
#define	GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
#define	GPIO_PUPDR_PUPD2_Pos (4U)
#define	GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
#define	GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define	GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
#define	GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
#define	GPIO_PUPDR_PUPD3_Pos (6U)
#define	GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
#define	GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define	GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
#define	GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
#define	GPIO_PUPDR_PUPD4_Pos (8U)
#define	GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
#define	GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define	GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
#define	GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
#define	GPIO_PUPDR_PUPD5_Pos (10U)
#define	GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
#define	GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define	GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
#define	GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
#define	GPIO_PUPDR_PUPD6_Pos (12U)
#define	GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
#define	GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define	GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
#define	GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
#define	GPIO_PUPDR_PUPD7_Pos (14U)
#define	GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
#define	GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define	GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
#define	GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
#define	GPIO_PUPDR_PUPD8_Pos (16U)
#define	GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
#define	GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define	GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
#define	GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
#define	GPIO_PUPDR_PUPD9_Pos (18U)
#define	GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
#define	GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define	GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
#define	GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
#define	GPIO_PUPDR_PUPD10_Pos (20U)
#define	GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
#define	GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define	GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
#define	GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
#define	GPIO_PUPDR_PUPD11_Pos (22U)
#define	GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
#define	GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define	GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
#define	GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
#define	GPIO_PUPDR_PUPD12_Pos (24U)
#define	GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
#define	GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define	GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
#define	GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
#define	GPIO_PUPDR_PUPD13_Pos (26U)
#define	GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
#define	GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define	GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
#define	GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
#define	GPIO_PUPDR_PUPD14_Pos (28U)
#define	GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
#define	GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define	GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
#define	GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
#define	GPIO_PUPDR_PUPD15_Pos (30U)
#define	GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
#define	GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define	GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
#define	GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
#define	GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define	GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define	GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define	GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define	GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define	GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define	GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define	GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define	GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define	GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define	GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define	GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define	GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define	GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define	GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define	GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define	GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define	GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define	GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define	GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define	GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define	GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define	GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define	GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define	GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define	GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define	GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define	GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define	GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define	GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define	GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define	GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define	GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define	GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define	GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define	GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define	GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define	GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define	GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define	GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define	GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define	GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define	GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define	GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define	GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define	GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define	GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define	GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
#define	GPIO_IDR_ID0_Pos (0U)
#define	GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
#define	GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define	GPIO_IDR_ID1_Pos (1U)
#define	GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
#define	GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define	GPIO_IDR_ID2_Pos (2U)
#define	GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
#define	GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define	GPIO_IDR_ID3_Pos (3U)
#define	GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
#define	GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define	GPIO_IDR_ID4_Pos (4U)
#define	GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
#define	GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define	GPIO_IDR_ID5_Pos (5U)
#define	GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
#define	GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define	GPIO_IDR_ID6_Pos (6U)
#define	GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
#define	GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define	GPIO_IDR_ID7_Pos (7U)
#define	GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
#define	GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define	GPIO_IDR_ID8_Pos (8U)
#define	GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
#define	GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define	GPIO_IDR_ID9_Pos (9U)
#define	GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
#define	GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define	GPIO_IDR_ID10_Pos (10U)
#define	GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
#define	GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define	GPIO_IDR_ID11_Pos (11U)
#define	GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
#define	GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define	GPIO_IDR_ID12_Pos (12U)
#define	GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
#define	GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define	GPIO_IDR_ID13_Pos (13U)
#define	GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
#define	GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define	GPIO_IDR_ID14_Pos (14U)
#define	GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
#define	GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define	GPIO_IDR_ID15_Pos (15U)
#define	GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
#define	GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
#define	GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define	GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define	GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define	GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define	GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define	GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define	GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define	GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define	GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define	GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define	GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define	GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define	GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define	GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define	GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define	GPIO_IDR_IDR_15 GPIO_IDR_ID15
#define	GPIO_ODR_OD0_Pos (0U)
#define	GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
#define	GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define	GPIO_ODR_OD1_Pos (1U)
#define	GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
#define	GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define	GPIO_ODR_OD2_Pos (2U)
#define	GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
#define	GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define	GPIO_ODR_OD3_Pos (3U)
#define	GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
#define	GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define	GPIO_ODR_OD4_Pos (4U)
#define	GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
#define	GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define	GPIO_ODR_OD5_Pos (5U)
#define	GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
#define	GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define	GPIO_ODR_OD6_Pos (6U)
#define	GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
#define	GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define	GPIO_ODR_OD7_Pos (7U)
#define	GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
#define	GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define	GPIO_ODR_OD8_Pos (8U)
#define	GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
#define	GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define	GPIO_ODR_OD9_Pos (9U)
#define	GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
#define	GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define	GPIO_ODR_OD10_Pos (10U)
#define	GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
#define	GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define	GPIO_ODR_OD11_Pos (11U)
#define	GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
#define	GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define	GPIO_ODR_OD12_Pos (12U)
#define	GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
#define	GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define	GPIO_ODR_OD13_Pos (13U)
#define	GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
#define	GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define	GPIO_ODR_OD14_Pos (14U)
#define	GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
#define	GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define	GPIO_ODR_OD15_Pos (15U)
#define	GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
#define	GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
#define	GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define	GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define	GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define	GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define	GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define	GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define	GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define	GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define	GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define	GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define	GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define	GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define	GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define	GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define	GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define	GPIO_ODR_ODR_15 GPIO_ODR_OD15
#define	GPIO_BSRR_BS0_Pos (0U)
#define	GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
#define	GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define	GPIO_BSRR_BS1_Pos (1U)
#define	GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
#define	GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define	GPIO_BSRR_BS2_Pos (2U)
#define	GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
#define	GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define	GPIO_BSRR_BS3_Pos (3U)
#define	GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
#define	GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define	GPIO_BSRR_BS4_Pos (4U)
#define	GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
#define	GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define	GPIO_BSRR_BS5_Pos (5U)
#define	GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
#define	GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define	GPIO_BSRR_BS6_Pos (6U)
#define	GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
#define	GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define	GPIO_BSRR_BS7_Pos (7U)
#define	GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
#define	GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define	GPIO_BSRR_BS8_Pos (8U)
#define	GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
#define	GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define	GPIO_BSRR_BS9_Pos (9U)
#define	GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
#define	GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define	GPIO_BSRR_BS10_Pos (10U)
#define	GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
#define	GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define	GPIO_BSRR_BS11_Pos (11U)
#define	GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
#define	GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define	GPIO_BSRR_BS12_Pos (12U)
#define	GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
#define	GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define	GPIO_BSRR_BS13_Pos (13U)
#define	GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
#define	GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define	GPIO_BSRR_BS14_Pos (14U)
#define	GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
#define	GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define	GPIO_BSRR_BS15_Pos (15U)
#define	GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
#define	GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define	GPIO_BSRR_BR0_Pos (16U)
#define	GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
#define	GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define	GPIO_BSRR_BR1_Pos (17U)
#define	GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
#define	GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define	GPIO_BSRR_BR2_Pos (18U)
#define	GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
#define	GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define	GPIO_BSRR_BR3_Pos (19U)
#define	GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
#define	GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define	GPIO_BSRR_BR4_Pos (20U)
#define	GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
#define	GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define	GPIO_BSRR_BR5_Pos (21U)
#define	GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
#define	GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define	GPIO_BSRR_BR6_Pos (22U)
#define	GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
#define	GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define	GPIO_BSRR_BR7_Pos (23U)
#define	GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
#define	GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define	GPIO_BSRR_BR8_Pos (24U)
#define	GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
#define	GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define	GPIO_BSRR_BR9_Pos (25U)
#define	GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
#define	GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define	GPIO_BSRR_BR10_Pos (26U)
#define	GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
#define	GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define	GPIO_BSRR_BR11_Pos (27U)
#define	GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
#define	GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define	GPIO_BSRR_BR12_Pos (28U)
#define	GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
#define	GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define	GPIO_BSRR_BR13_Pos (29U)
#define	GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
#define	GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define	GPIO_BSRR_BR14_Pos (30U)
#define	GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
#define	GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define	GPIO_BSRR_BR15_Pos (31U)
#define	GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
#define	GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
#define	GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define	GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define	GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define	GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define	GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define	GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define	GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define	GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define	GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define	GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define	GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define	GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define	GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define	GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define	GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define	GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define	GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define	GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define	GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define	GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define	GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define	GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define	GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define	GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define	GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define	GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define	GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define	GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define	GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define	GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define	GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define	GPIO_BSRR_BR_15 GPIO_BSRR_BR15
#define	GPIO_BRR_BR0 GPIO_BSRR_BR0
#define	GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
#define	GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
#define	GPIO_BRR_BR1 GPIO_BSRR_BR1
#define	GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
#define	GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
#define	GPIO_BRR_BR2 GPIO_BSRR_BR2
#define	GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
#define	GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
#define	GPIO_BRR_BR3 GPIO_BSRR_BR3
#define	GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
#define	GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
#define	GPIO_BRR_BR4 GPIO_BSRR_BR4
#define	GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
#define	GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
#define	GPIO_BRR_BR5 GPIO_BSRR_BR5
#define	GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
#define	GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
#define	GPIO_BRR_BR6 GPIO_BSRR_BR6
#define	GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
#define	GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
#define	GPIO_BRR_BR7 GPIO_BSRR_BR7
#define	GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
#define	GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
#define	GPIO_BRR_BR8 GPIO_BSRR_BR8
#define	GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
#define	GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
#define	GPIO_BRR_BR9 GPIO_BSRR_BR9
#define	GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
#define	GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
#define	GPIO_BRR_BR10 GPIO_BSRR_BR10
#define	GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
#define	GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
#define	GPIO_BRR_BR11 GPIO_BSRR_BR11
#define	GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
#define	GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
#define	GPIO_BRR_BR12 GPIO_BSRR_BR12
#define	GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
#define	GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
#define	GPIO_BRR_BR13 GPIO_BSRR_BR13
#define	GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
#define	GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
#define	GPIO_BRR_BR14 GPIO_BSRR_BR14
#define	GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
#define	GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
#define	GPIO_BRR_BR15 GPIO_BSRR_BR15
#define	GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
#define	GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
#define	GPIO_LCKR_LCK0_Pos (0U)
#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define	GPIO_LCKR_LCK1_Pos (1U)
#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define	GPIO_LCKR_LCK2_Pos (2U)
#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define	GPIO_LCKR_LCK3_Pos (3U)
#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define	GPIO_LCKR_LCK4_Pos (4U)
#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define	GPIO_LCKR_LCK5_Pos (5U)
#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define	GPIO_LCKR_LCK6_Pos (6U)
#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define	GPIO_LCKR_LCK7_Pos (7U)
#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define	GPIO_LCKR_LCK8_Pos (8U)
#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define	GPIO_LCKR_LCK9_Pos (9U)
#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define	GPIO_LCKR_LCK10_Pos (10U)
#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define	GPIO_LCKR_LCK11_Pos (11U)
#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define	GPIO_LCKR_LCK12_Pos (12U)
#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define	GPIO_LCKR_LCK13_Pos (13U)
#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define	GPIO_LCKR_LCK14_Pos (14U)
#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define	GPIO_LCKR_LCK15_Pos (15U)
#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define	GPIO_LCKR_LCKK_Pos (16U)
#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
#define	GPIO_AFRL_AFSEL0_Pos (0U)
#define	GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
#define	GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define	GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
#define	GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
#define	GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
#define	GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
#define	GPIO_AFRL_AFSEL1_Pos (4U)
#define	GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
#define	GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define	GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
#define	GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
#define	GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
#define	GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
#define	GPIO_AFRL_AFSEL2_Pos (8U)
#define	GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
#define	GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define	GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
#define	GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
#define	GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
#define	GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
#define	GPIO_AFRL_AFSEL3_Pos (12U)
#define	GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
#define	GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define	GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
#define	GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
#define	GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
#define	GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
#define	GPIO_AFRL_AFSEL4_Pos (16U)
#define	GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
#define	GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define	GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
#define	GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
#define	GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
#define	GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
#define	GPIO_AFRL_AFSEL5_Pos (20U)
#define	GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
#define	GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define	GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
#define	GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
#define	GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
#define	GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
#define	GPIO_AFRL_AFSEL6_Pos (24U)
#define	GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
#define	GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define	GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
#define	GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
#define	GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
#define	GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
#define	GPIO_AFRL_AFSEL7_Pos (28U)
#define	GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
#define	GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define	GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
#define	GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
#define	GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
#define	GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
#define	GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define	GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
#define	GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
#define	GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
#define	GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
#define	GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define	GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
#define	GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
#define	GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
#define	GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
#define	GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define	GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
#define	GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
#define	GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
#define	GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
#define	GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define	GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
#define	GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
#define	GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
#define	GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
#define	GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define	GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
#define	GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
#define	GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
#define	GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
#define	GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define	GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
#define	GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
#define	GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
#define	GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
#define	GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define	GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
#define	GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
#define	GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
#define	GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
#define	GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
#define	GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
#define	GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
#define	GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
#define	GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
#define	GPIO_AFRH_AFSEL8_Pos (0U)
#define	GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
#define	GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define	GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
#define	GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
#define	GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
#define	GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
#define	GPIO_AFRH_AFSEL9_Pos (4U)
#define	GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
#define	GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define	GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
#define	GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
#define	GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
#define	GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
#define	GPIO_AFRH_AFSEL10_Pos (8U)
#define	GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
#define	GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define	GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
#define	GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
#define	GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
#define	GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
#define	GPIO_AFRH_AFSEL11_Pos (12U)
#define	GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
#define	GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define	GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
#define	GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
#define	GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
#define	GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
#define	GPIO_AFRH_AFSEL12_Pos (16U)
#define	GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
#define	GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define	GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
#define	GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
#define	GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
#define	GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
#define	GPIO_AFRH_AFSEL13_Pos (20U)
#define	GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
#define	GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define	GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
#define	GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
#define	GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
#define	GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
#define	GPIO_AFRH_AFSEL14_Pos (24U)
#define	GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
#define	GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define	GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
#define	GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
#define	GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
#define	GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
#define	GPIO_AFRH_AFSEL15_Pos (28U)
#define	GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
#define	GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define	GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
#define	GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
#define	GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
#define	GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
#define	GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define	GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
#define	GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
#define	GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
#define	GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
#define	GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define	GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
#define	GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
#define	GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
#define	GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
#define	GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define	GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
#define	GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
#define	GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
#define	GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
#define	GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define	GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
#define	GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
#define	GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
#define	GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
#define	GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define	GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
#define	GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
#define	GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
#define	GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
#define	GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define	GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
#define	GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
#define	GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
#define	GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
#define	GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define	GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
#define	GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
#define	GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
#define	GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
#define	GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
#define	GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
#define	GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
#define	GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
#define	GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
#define	I2C_CR1_PE_Pos (0U)
#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
#define	I2C_CR1_PE I2C_CR1_PE_Msk
#define	I2C_CR1_SMBUS_Pos (1U)
#define	I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
#define	I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
#define	I2C_CR1_SMBTYPE_Pos (3U)
#define	I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
#define	I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
#define	I2C_CR1_ENARP_Pos (4U)
#define	I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
#define	I2C_CR1_ENARP I2C_CR1_ENARP_Msk
#define	I2C_CR1_ENPEC_Pos (5U)
#define	I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
#define	I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
#define	I2C_CR1_ENGC_Pos (6U)
#define	I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
#define	I2C_CR1_ENGC I2C_CR1_ENGC_Msk
#define	I2C_CR1_NOSTRETCH_Pos (7U)
#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
#define	I2C_CR1_START_Pos (8U)
#define	I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
#define	I2C_CR1_START I2C_CR1_START_Msk
#define	I2C_CR1_STOP_Pos (9U)
#define	I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
#define	I2C_CR1_STOP I2C_CR1_STOP_Msk
#define	I2C_CR1_ACK_Pos (10U)
#define	I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
#define	I2C_CR1_ACK I2C_CR1_ACK_Msk
#define	I2C_CR1_POS_Pos (11U)
#define	I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
#define	I2C_CR1_POS I2C_CR1_POS_Msk
#define	I2C_CR1_PEC_Pos (12U)
#define	I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
#define	I2C_CR1_PEC I2C_CR1_PEC_Msk
#define	I2C_CR1_ALERT_Pos (13U)
#define	I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
#define	I2C_CR1_ALERT I2C_CR1_ALERT_Msk
#define	I2C_CR1_SWRST_Pos (15U)
#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk
#define	I2C_CR2_FREQ_Pos (0U)
#define	I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ I2C_CR2_FREQ_Msk
#define	I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
#define	I2C_CR2_ITERREN_Pos (8U)
#define	I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
#define	I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
#define	I2C_CR2_ITEVTEN_Pos (9U)
#define	I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
#define	I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
#define	I2C_CR2_ITBUFEN_Pos (10U)
#define	I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
#define	I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
#define	I2C_CR2_DMAEN_Pos (11U)
#define	I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
#define	I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
#define	I2C_CR2_LAST_Pos (12U)
#define	I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
#define	I2C_CR2_LAST I2C_CR2_LAST_Msk
#define	I2C_OAR1_ADD1_7 0x000000FEU
#define	I2C_OAR1_ADD8_9 0x00000300U
#define	I2C_OAR1_ADD0_Pos (0U)
#define	I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
#define	I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
#define	I2C_OAR1_ADD1_Pos (1U)
#define	I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
#define	I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
#define	I2C_OAR1_ADD2_Pos (2U)
#define	I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
#define	I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
#define	I2C_OAR1_ADD3_Pos (3U)
#define	I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
#define	I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
#define	I2C_OAR1_ADD4_Pos (4U)
#define	I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
#define	I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
#define	I2C_OAR1_ADD5_Pos (5U)
#define	I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
#define	I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
#define	I2C_OAR1_ADD6_Pos (6U)
#define	I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
#define	I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
#define	I2C_OAR1_ADD7_Pos (7U)
#define	I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
#define	I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
#define	I2C_OAR1_ADD8_Pos (8U)
#define	I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
#define	I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
#define	I2C_OAR1_ADD9_Pos (9U)
#define	I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
#define	I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
#define	I2C_OAR1_ADDMODE_Pos (15U)
#define	I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
#define	I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
#define	I2C_OAR2_ENDUAL_Pos (0U)
#define	I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
#define	I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
#define	I2C_OAR2_ADD2_Pos (1U)
#define	I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
#define	I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
#define	I2C_DR_DR_Pos (0U)
#define	I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
#define	I2C_DR_DR I2C_DR_DR_Msk
#define	I2C_SR1_SB_Pos (0U)
#define	I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
#define	I2C_SR1_SB I2C_SR1_SB_Msk
#define	I2C_SR1_ADDR_Pos (1U)
#define	I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
#define	I2C_SR1_ADDR I2C_SR1_ADDR_Msk
#define	I2C_SR1_BTF_Pos (2U)
#define	I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
#define	I2C_SR1_BTF I2C_SR1_BTF_Msk
#define	I2C_SR1_ADD10_Pos (3U)
#define	I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
#define	I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
#define	I2C_SR1_STOPF_Pos (4U)
#define	I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
#define	I2C_SR1_STOPF I2C_SR1_STOPF_Msk
#define	I2C_SR1_RXNE_Pos (6U)
#define	I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
#define	I2C_SR1_RXNE I2C_SR1_RXNE_Msk
#define	I2C_SR1_TXE_Pos (7U)
#define	I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
#define	I2C_SR1_TXE I2C_SR1_TXE_Msk
#define	I2C_SR1_BERR_Pos (8U)
#define	I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
#define	I2C_SR1_BERR I2C_SR1_BERR_Msk
#define	I2C_SR1_ARLO_Pos (9U)
#define	I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
#define	I2C_SR1_ARLO I2C_SR1_ARLO_Msk
#define	I2C_SR1_AF_Pos (10U)
#define	I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
#define	I2C_SR1_AF I2C_SR1_AF_Msk
#define	I2C_SR1_OVR_Pos (11U)
#define	I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
#define	I2C_SR1_OVR I2C_SR1_OVR_Msk
#define	I2C_SR1_PECERR_Pos (12U)
#define	I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
#define	I2C_SR1_PECERR I2C_SR1_PECERR_Msk
#define	I2C_SR1_TIMEOUT_Pos (14U)
#define	I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
#define	I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
#define	I2C_SR1_SMBALERT_Pos (15U)
#define	I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
#define	I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
#define	I2C_SR2_MSL_Pos (0U)
#define	I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
#define	I2C_SR2_MSL I2C_SR2_MSL_Msk
#define	I2C_SR2_BUSY_Pos (1U)
#define	I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
#define	I2C_SR2_BUSY I2C_SR2_BUSY_Msk
#define	I2C_SR2_TRA_Pos (2U)
#define	I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
#define	I2C_SR2_TRA I2C_SR2_TRA_Msk
#define	I2C_SR2_GENCALL_Pos (4U)
#define	I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
#define	I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
#define	I2C_SR2_SMBDEFAULT_Pos (5U)
#define	I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
#define	I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
#define	I2C_SR2_SMBHOST_Pos (6U)
#define	I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
#define	I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
#define	I2C_SR2_DUALF_Pos (7U)
#define	I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
#define	I2C_SR2_DUALF I2C_SR2_DUALF_Msk
#define	I2C_SR2_PEC_Pos (8U)
#define	I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
#define	I2C_SR2_PEC I2C_SR2_PEC_Msk
#define	I2C_CCR_CCR_Pos (0U)
#define	I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
#define	I2C_CCR_CCR I2C_CCR_CCR_Msk
#define	I2C_CCR_DUTY_Pos (14U)
#define	I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
#define	I2C_CCR_DUTY I2C_CCR_DUTY_Msk
#define	I2C_CCR_FS_Pos (15U)
#define	I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
#define	I2C_CCR_FS I2C_CCR_FS_Msk
#define	I2C_TRISE_TRISE_Pos (0U)
#define	I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
#define	I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
#define	IWDG_KR_KEY_Pos (0U)
#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
#define	IWDG_KR_KEY IWDG_KR_KEY_Msk
#define	IWDG_PR_PR_Pos (0U)
#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
#define	IWDG_PR_PR IWDG_PR_PR_Msk
#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
#define	IWDG_RLR_RL_Pos (0U)
#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
#define	IWDG_RLR_RL IWDG_RLR_RL_Msk
#define	IWDG_SR_PVU_Pos (0U)
#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
#define	IWDG_SR_PVU IWDG_SR_PVU_Msk
#define	IWDG_SR_RVU_Pos (1U)
#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
#define	IWDG_SR_RVU IWDG_SR_RVU_Msk
#define	PWR_CR_LPDS_Pos (0U)
#define	PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
#define	PWR_CR_LPDS PWR_CR_LPDS_Msk
#define	PWR_CR_PDDS_Pos (1U)
#define	PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
#define	PWR_CR_PDDS PWR_CR_PDDS_Msk
#define	PWR_CR_CWUF_Pos (2U)
#define	PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
#define	PWR_CR_CWUF PWR_CR_CWUF_Msk
#define	PWR_CR_CSBF_Pos (3U)
#define	PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
#define	PWR_CR_CSBF PWR_CR_CSBF_Msk
#define	PWR_CR_PVDE_Pos (4U)
#define	PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
#define	PWR_CR_PVDE PWR_CR_PVDE_Msk
#define	PWR_CR_PLS_Pos (5U)
#define	PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
#define	PWR_CR_PLS PWR_CR_PLS_Msk
#define	PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
#define	PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
#define	PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
#define	PWR_CR_PLS_LEV0 0x00000000U
#define	PWR_CR_PLS_LEV1 0x00000020U
#define	PWR_CR_PLS_LEV2 0x00000040U
#define	PWR_CR_PLS_LEV3 0x00000060U
#define	PWR_CR_PLS_LEV4 0x00000080U
#define	PWR_CR_PLS_LEV5 0x000000A0U
#define	PWR_CR_PLS_LEV6 0x000000C0U
#define	PWR_CR_PLS_LEV7 0x000000E0U
#define	PWR_CR_DBP_Pos (8U)
#define	PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
#define	PWR_CR_DBP PWR_CR_DBP_Msk
#define	PWR_CR_FPDS_Pos (9U)
#define	PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
#define	PWR_CR_FPDS PWR_CR_FPDS_Msk
#define	PWR_CR_VOS_Pos (14U)
#define	PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)
#define	PWR_CR_VOS PWR_CR_VOS_Msk
#define	PWR_CR_PMODE PWR_CR_VOS
#define	PWR_CSR_WUF_Pos (0U)
#define	PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
#define	PWR_CSR_WUF PWR_CSR_WUF_Msk
#define	PWR_CSR_SBF_Pos (1U)
#define	PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
#define	PWR_CSR_SBF PWR_CSR_SBF_Msk
#define	PWR_CSR_PVDO_Pos (2U)
#define	PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
#define	PWR_CSR_PVDO PWR_CSR_PVDO_Msk
#define	PWR_CSR_BRR_Pos (3U)
#define	PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
#define	PWR_CSR_BRR PWR_CSR_BRR_Msk
#define	PWR_CSR_EWUP_Pos (8U)
#define	PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
#define	PWR_CSR_EWUP PWR_CSR_EWUP_Msk
#define	PWR_CSR_BRE_Pos (9U)
#define	PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
#define	PWR_CSR_BRE PWR_CSR_BRE_Msk
#define	PWR_CSR_VOSRDY_Pos (14U)
#define	PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
#define	PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
#define	PWR_CSR_REGRDY PWR_CSR_VOSRDY
#define	RCC_CR_HSION_Pos (0U)
#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
#define	RCC_CR_HSION RCC_CR_HSION_Msk
#define	RCC_CR_HSIRDY_Pos (1U)
#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
#define	RCC_CR_HSITRIM_Pos (3U)
#define	RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
#define	RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
#define	RCC_CR_HSICAL_Pos (8U)
#define	RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL RCC_CR_HSICAL_Msk
#define	RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
#define	RCC_CR_HSEON_Pos (16U)
#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
#define	RCC_CR_HSEON RCC_CR_HSEON_Msk
#define	RCC_CR_HSERDY_Pos (17U)
#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk
#define	RCC_CR_HSEBYP_Pos (18U)
#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
#define	RCC_CR_CSSON_Pos (19U)
#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
#define	RCC_CR_CSSON RCC_CR_CSSON_Msk
#define	RCC_CR_PLLON_Pos (24U)
#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
#define	RCC_CR_PLLON RCC_CR_PLLON_Msk
#define	RCC_CR_PLLRDY_Pos (25U)
#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
#define	RCC_PLLI2S_SUPPORT
#define	RCC_CR_PLLI2SON_Pos (26U)
#define	RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
#define	RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
#define	RCC_CR_PLLI2SRDY_Pos (27U)
#define	RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
#define	RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
#define	RCC_PLLCFGR_PLLM_Pos (0U)
#define	RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define	RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
#define	RCC_PLLCFGR_PLLN_Pos (6U)
#define	RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define	RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
#define	RCC_PLLCFGR_PLLP_Pos (16U)
#define	RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
#define	RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define	RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
#define	RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
#define	RCC_PLLCFGR_PLLSRC_Pos (22U)
#define	RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
#define	RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define	RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
#define	RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
#define	RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
#define	RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
#define	RCC_PLLCFGR_PLLQ_Pos (24U)
#define	RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
#define	RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define	RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
#define	RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
#define	RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
#define	RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
#define	RCC_CFGR_SW_Pos (0U)
#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
#define	RCC_CFGR_SW RCC_CFGR_SW_Msk
#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
#define	RCC_CFGR_SW_HSI 0x00000000U
#define	RCC_CFGR_SW_HSE 0x00000001U
#define	RCC_CFGR_SW_PLL 0x00000002U
#define	RCC_CFGR_SWS_Pos (2U)
#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk
#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
#define	RCC_CFGR_SWS_HSI 0x00000000U
#define	RCC_CFGR_SWS_HSE 0x00000004U
#define	RCC_CFGR_SWS_PLL 0x00000008U
#define	RCC_CFGR_HPRE_Pos (4U)
#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
#define	RCC_CFGR_HPRE_DIV1 0x00000000U
#define	RCC_CFGR_HPRE_DIV2 0x00000080U
#define	RCC_CFGR_HPRE_DIV4 0x00000090U
#define	RCC_CFGR_HPRE_DIV8 0x000000A0U
#define	RCC_CFGR_HPRE_DIV16 0x000000B0U
#define	RCC_CFGR_HPRE_DIV64 0x000000C0U
#define	RCC_CFGR_HPRE_DIV128 0x000000D0U
#define	RCC_CFGR_HPRE_DIV256 0x000000E0U
#define	RCC_CFGR_HPRE_DIV512 0x000000F0U
#define	RCC_CFGR_PPRE1_Pos (10U)
#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
#define	RCC_CFGR_PPRE1_DIV1 0x00000000U
#define	RCC_CFGR_PPRE1_DIV2 0x00001000U
#define	RCC_CFGR_PPRE1_DIV4 0x00001400U
#define	RCC_CFGR_PPRE1_DIV8 0x00001800U
#define	RCC_CFGR_PPRE1_DIV16 0x00001C00U
#define	RCC_CFGR_PPRE2_Pos (13U)
#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
#define	RCC_CFGR_PPRE2_DIV1 0x00000000U
#define	RCC_CFGR_PPRE2_DIV2 0x00008000U
#define	RCC_CFGR_PPRE2_DIV4 0x0000A000U
#define	RCC_CFGR_PPRE2_DIV8 0x0000C000U
#define	RCC_CFGR_PPRE2_DIV16 0x0000E000U
#define	RCC_CFGR_RTCPRE_Pos (16U)
#define	RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
#define	RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_MCO1_Pos (21U)
#define	RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
#define	RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
#define	RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
#define	RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
#define	RCC_CFGR_I2SSRC_Pos (23U)
#define	RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
#define	RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
#define	RCC_CFGR_MCO1PRE_Pos (24U)
#define	RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
#define	RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
#define	RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
#define	RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
#define	RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
#define	RCC_CFGR_MCO2PRE_Pos (27U)
#define	RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
#define	RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
#define	RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
#define	RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
#define	RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
#define	RCC_CFGR_MCO2_Pos (30U)
#define	RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
#define	RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
#define	RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
#define	RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
#define	RCC_CIR_LSIRDYF_Pos (0U)
#define	RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
#define	RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
#define	RCC_CIR_LSERDYF_Pos (1U)
#define	RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
#define	RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
#define	RCC_CIR_HSIRDYF_Pos (2U)
#define	RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
#define	RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
#define	RCC_CIR_HSERDYF_Pos (3U)
#define	RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
#define	RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
#define	RCC_CIR_PLLRDYF_Pos (4U)
#define	RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
#define	RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
#define	RCC_CIR_PLLI2SRDYF_Pos (5U)
#define	RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
#define	RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
#define	RCC_CIR_CSSF_Pos (7U)
#define	RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
#define	RCC_CIR_CSSF RCC_CIR_CSSF_Msk
#define	RCC_CIR_LSIRDYIE_Pos (8U)
#define	RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
#define	RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
#define	RCC_CIR_LSERDYIE_Pos (9U)
#define	RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
#define	RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
#define	RCC_CIR_HSIRDYIE_Pos (10U)
#define	RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
#define	RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
#define	RCC_CIR_HSERDYIE_Pos (11U)
#define	RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
#define	RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
#define	RCC_CIR_PLLRDYIE_Pos (12U)
#define	RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
#define	RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
#define	RCC_CIR_PLLI2SRDYIE_Pos (13U)
#define	RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
#define	RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
#define	RCC_CIR_LSIRDYC_Pos (16U)
#define	RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
#define	RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
#define	RCC_CIR_LSERDYC_Pos (17U)
#define	RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
#define	RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
#define	RCC_CIR_HSIRDYC_Pos (18U)
#define	RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
#define	RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
#define	RCC_CIR_HSERDYC_Pos (19U)
#define	RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
#define	RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
#define	RCC_CIR_PLLRDYC_Pos (20U)
#define	RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
#define	RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
#define	RCC_CIR_PLLI2SRDYC_Pos (21U)
#define	RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
#define	RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
#define	RCC_CIR_CSSC_Pos (23U)
#define	RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
#define	RCC_CIR_CSSC RCC_CIR_CSSC_Msk
#define	RCC_AHB1RSTR_GPIOARST_Pos (0U)
#define	RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
#define	RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
#define	RCC_AHB1RSTR_GPIOBRST_Pos (1U)
#define	RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
#define	RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
#define	RCC_AHB1RSTR_GPIOCRST_Pos (2U)
#define	RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
#define	RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
#define	RCC_AHB1RSTR_GPIODRST_Pos (3U)
#define	RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
#define	RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
#define	RCC_AHB1RSTR_GPIOERST_Pos (4U)
#define	RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
#define	RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
#define	RCC_AHB1RSTR_GPIOFRST_Pos (5U)
#define	RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
#define	RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
#define	RCC_AHB1RSTR_GPIOGRST_Pos (6U)
#define	RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
#define	RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
#define	RCC_AHB1RSTR_GPIOHRST_Pos (7U)
#define	RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
#define	RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
#define	RCC_AHB1RSTR_GPIOIRST_Pos (8U)
#define	RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
#define	RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
#define	RCC_AHB1RSTR_CRCRST_Pos (12U)
#define	RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
#define	RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
#define	RCC_AHB1RSTR_DMA1RST_Pos (21U)
#define	RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
#define	RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define	RCC_AHB1RSTR_DMA2RST_Pos (22U)
#define	RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
#define	RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define	RCC_AHB1RSTR_ETHMACRST_Pos (25U)
#define	RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
#define	RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
#define	RCC_AHB1RSTR_OTGHRST_Pos (29U)
#define	RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
#define	RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
#define	RCC_AHB2RSTR_DCMIRST_Pos (0U)
#define	RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
#define	RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
#define	RCC_AHB2RSTR_RNGRST_Pos (6U)
#define	RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
#define	RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
#define	RCC_AHB2RSTR_OTGFSRST_Pos (7U)
#define	RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
#define	RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
#define	RCC_AHB3RSTR_FSMCRST_Pos (0U)
#define	RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
#define	RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
#define	RCC_APB1RSTR_TIM2RST_Pos (0U)
#define	RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
#define	RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
#define	RCC_APB1RSTR_TIM3RST_Pos (1U)
#define	RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
#define	RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
#define	RCC_APB1RSTR_TIM4RST_Pos (2U)
#define	RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
#define	RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
#define	RCC_APB1RSTR_TIM5RST_Pos (3U)
#define	RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
#define	RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
#define	RCC_APB1RSTR_TIM6RST_Pos (4U)
#define	RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
#define	RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
#define	RCC_APB1RSTR_TIM7RST_Pos (5U)
#define	RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
#define	RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
#define	RCC_APB1RSTR_TIM12RST_Pos (6U)
#define	RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
#define	RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
#define	RCC_APB1RSTR_TIM13RST_Pos (7U)
#define	RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
#define	RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
#define	RCC_APB1RSTR_TIM14RST_Pos (8U)
#define	RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
#define	RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
#define	RCC_APB1RSTR_WWDGRST_Pos (11U)
#define	RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
#define	RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
#define	RCC_APB1RSTR_SPI2RST_Pos (14U)
#define	RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
#define	RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
#define	RCC_APB1RSTR_SPI3RST_Pos (15U)
#define	RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
#define	RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
#define	RCC_APB1RSTR_USART2RST_Pos (17U)
#define	RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
#define	RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
#define	RCC_APB1RSTR_USART3RST_Pos (18U)
#define	RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
#define	RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
#define	RCC_APB1RSTR_UART4RST_Pos (19U)
#define	RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
#define	RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
#define	RCC_APB1RSTR_UART5RST_Pos (20U)
#define	RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
#define	RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
#define	RCC_APB1RSTR_I2C1RST_Pos (21U)
#define	RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
#define	RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
#define	RCC_APB1RSTR_I2C2RST_Pos (22U)
#define	RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
#define	RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
#define	RCC_APB1RSTR_I2C3RST_Pos (23U)
#define	RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
#define	RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
#define	RCC_APB1RSTR_CAN1RST_Pos (25U)
#define	RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
#define	RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
#define	RCC_APB1RSTR_CAN2RST_Pos (26U)
#define	RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
#define	RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
#define	RCC_APB1RSTR_PWRRST_Pos (28U)
#define	RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
#define	RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
#define	RCC_APB1RSTR_DACRST_Pos (29U)
#define	RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
#define	RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
#define	RCC_APB2RSTR_TIM1RST_Pos (0U)
#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define	RCC_APB2RSTR_TIM8RST_Pos (1U)
#define	RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
#define	RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define	RCC_APB2RSTR_USART1RST_Pos (4U)
#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define	RCC_APB2RSTR_USART6RST_Pos (5U)
#define	RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
#define	RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
#define	RCC_APB2RSTR_ADCRST_Pos (8U)
#define	RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
#define	RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
#define	RCC_APB2RSTR_SDIORST_Pos (11U)
#define	RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
#define	RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
#define	RCC_APB2RSTR_SPI1RST_Pos (12U)
#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define	RCC_APB2RSTR_SYSCFGRST_Pos (14U)
#define	RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
#define	RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define	RCC_APB2RSTR_TIM9RST_Pos (16U)
#define	RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
#define	RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
#define	RCC_APB2RSTR_TIM10RST_Pos (17U)
#define	RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
#define	RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
#define	RCC_APB2RSTR_TIM11RST_Pos (18U)
#define	RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
#define	RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
#define	RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
#define	RCC_AHB1ENR_GPIOAEN_Pos (0U)
#define	RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
#define	RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
#define	RCC_AHB1ENR_GPIOBEN_Pos (1U)
#define	RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
#define	RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
#define	RCC_AHB1ENR_GPIOCEN_Pos (2U)
#define	RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
#define	RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
#define	RCC_AHB1ENR_GPIODEN_Pos (3U)
#define	RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
#define	RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
#define	RCC_AHB1ENR_GPIOEEN_Pos (4U)
#define	RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
#define	RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
#define	RCC_AHB1ENR_GPIOFEN_Pos (5U)
#define	RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
#define	RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
#define	RCC_AHB1ENR_GPIOGEN_Pos (6U)
#define	RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
#define	RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
#define	RCC_AHB1ENR_GPIOHEN_Pos (7U)
#define	RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
#define	RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
#define	RCC_AHB1ENR_GPIOIEN_Pos (8U)
#define	RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
#define	RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
#define	RCC_AHB1ENR_CRCEN_Pos (12U)
#define	RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
#define	RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
#define	RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
#define	RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
#define	RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
#define	RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
#define	RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
#define	RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
#define	RCC_AHB1ENR_DMA1EN_Pos (21U)
#define	RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
#define	RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define	RCC_AHB1ENR_DMA2EN_Pos (22U)
#define	RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
#define	RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define	RCC_AHB1ENR_ETHMACEN_Pos (25U)
#define	RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
#define	RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
#define	RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
#define	RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
#define	RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
#define	RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
#define	RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
#define	RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
#define	RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
#define	RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
#define	RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
#define	RCC_AHB1ENR_OTGHSEN_Pos (29U)
#define	RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
#define	RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
#define	RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
#define	RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
#define	RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
#define	RCC_AHB2_SUPPORT
#define	RCC_AHB2ENR_DCMIEN_Pos (0U)
#define	RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
#define	RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
#define	RCC_AHB2ENR_RNGEN_Pos (6U)
#define	RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
#define	RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
#define	RCC_AHB2ENR_OTGFSEN_Pos (7U)
#define	RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
#define	RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
#define	RCC_AHB3_SUPPORT
#define	RCC_AHB3ENR_FSMCEN_Pos (0U)
#define	RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
#define	RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
#define	RCC_APB1ENR_TIM2EN_Pos (0U)
#define	RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
#define	RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
#define	RCC_APB1ENR_TIM3EN_Pos (1U)
#define	RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
#define	RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
#define	RCC_APB1ENR_TIM4EN_Pos (2U)
#define	RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
#define	RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
#define	RCC_APB1ENR_TIM5EN_Pos (3U)
#define	RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
#define	RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
#define	RCC_APB1ENR_TIM6EN_Pos (4U)
#define	RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
#define	RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
#define	RCC_APB1ENR_TIM7EN_Pos (5U)
#define	RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
#define	RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
#define	RCC_APB1ENR_TIM12EN_Pos (6U)
#define	RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
#define	RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
#define	RCC_APB1ENR_TIM13EN_Pos (7U)
#define	RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
#define	RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
#define	RCC_APB1ENR_TIM14EN_Pos (8U)
#define	RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
#define	RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
#define	RCC_APB1ENR_WWDGEN_Pos (11U)
#define	RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
#define	RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
#define	RCC_APB1ENR_SPI2EN_Pos (14U)
#define	RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
#define	RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
#define	RCC_APB1ENR_SPI3EN_Pos (15U)
#define	RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
#define	RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
#define	RCC_APB1ENR_USART2EN_Pos (17U)
#define	RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
#define	RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
#define	RCC_APB1ENR_USART3EN_Pos (18U)
#define	RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
#define	RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
#define	RCC_APB1ENR_UART4EN_Pos (19U)
#define	RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
#define	RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
#define	RCC_APB1ENR_UART5EN_Pos (20U)
#define	RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
#define	RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
#define	RCC_APB1ENR_I2C1EN_Pos (21U)
#define	RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
#define	RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
#define	RCC_APB1ENR_I2C2EN_Pos (22U)
#define	RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
#define	RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
#define	RCC_APB1ENR_I2C3EN_Pos (23U)
#define	RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
#define	RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
#define	RCC_APB1ENR_CAN1EN_Pos (25U)
#define	RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
#define	RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
#define	RCC_APB1ENR_CAN2EN_Pos (26U)
#define	RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
#define	RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
#define	RCC_APB1ENR_PWREN_Pos (28U)
#define	RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
#define	RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
#define	RCC_APB1ENR_DACEN_Pos (29U)
#define	RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
#define	RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
#define	RCC_APB2ENR_TIM1EN_Pos (0U)
#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define	RCC_APB2ENR_TIM8EN_Pos (1U)
#define	RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
#define	RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define	RCC_APB2ENR_USART1EN_Pos (4U)
#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define	RCC_APB2ENR_USART6EN_Pos (5U)
#define	RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
#define	RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
#define	RCC_APB2ENR_ADC1EN_Pos (8U)
#define	RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
#define	RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
#define	RCC_APB2ENR_ADC2EN_Pos (9U)
#define	RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
#define	RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
#define	RCC_APB2ENR_ADC3EN_Pos (10U)
#define	RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
#define	RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
#define	RCC_APB2ENR_SDIOEN_Pos (11U)
#define	RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
#define	RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
#define	RCC_APB2ENR_SPI1EN_Pos (12U)
#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define	RCC_APB2ENR_SYSCFGEN_Pos (14U)
#define	RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
#define	RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define	RCC_APB2ENR_TIM9EN_Pos (16U)
#define	RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
#define	RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
#define	RCC_APB2ENR_TIM10EN_Pos (17U)
#define	RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
#define	RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
#define	RCC_APB2ENR_TIM11EN_Pos (18U)
#define	RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
#define	RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
#define	RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
#define	RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
#define	RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
#define	RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
#define	RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
#define	RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
#define	RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
#define	RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
#define	RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
#define	RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
#define	RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
#define	RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
#define	RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
#define	RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
#define	RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
#define	RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
#define	RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
#define	RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
#define	RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
#define	RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
#define	RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
#define	RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
#define	RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
#define	RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
#define	RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
#define	RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
#define	RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
#define	RCC_AHB1LPENR_CRCLPEN_Pos (12U)
#define	RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
#define	RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
#define	RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
#define	RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
#define	RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
#define	RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
#define	RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
#define	RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
#define	RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
#define	RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
#define	RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
#define	RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
#define	RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
#define	RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
#define	RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
#define	RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
#define	RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
#define	RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
#define	RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
#define	RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
#define	RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
#define	RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
#define	RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
#define	RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
#define	RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
#define	RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
#define	RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
#define	RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
#define	RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
#define	RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
#define	RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
#define	RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
#define	RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
#define	RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
#define	RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
#define	RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
#define	RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
#define	RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
#define	RCC_AHB2LPENR_DCMILPEN_Pos (0U)
#define	RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
#define	RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
#define	RCC_AHB2LPENR_RNGLPEN_Pos (6U)
#define	RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
#define	RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
#define	RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
#define	RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
#define	RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
#define	RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
#define	RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
#define	RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
#define	RCC_APB1LPENR_TIM2LPEN_Pos (0U)
#define	RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
#define	RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
#define	RCC_APB1LPENR_TIM3LPEN_Pos (1U)
#define	RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
#define	RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
#define	RCC_APB1LPENR_TIM4LPEN_Pos (2U)
#define	RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
#define	RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
#define	RCC_APB1LPENR_TIM5LPEN_Pos (3U)
#define	RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
#define	RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
#define	RCC_APB1LPENR_TIM6LPEN_Pos (4U)
#define	RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
#define	RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
#define	RCC_APB1LPENR_TIM7LPEN_Pos (5U)
#define	RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
#define	RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
#define	RCC_APB1LPENR_TIM12LPEN_Pos (6U)
#define	RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
#define	RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
#define	RCC_APB1LPENR_TIM13LPEN_Pos (7U)
#define	RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
#define	RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
#define	RCC_APB1LPENR_TIM14LPEN_Pos (8U)
#define	RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
#define	RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
#define	RCC_APB1LPENR_WWDGLPEN_Pos (11U)
#define	RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
#define	RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
#define	RCC_APB1LPENR_SPI2LPEN_Pos (14U)
#define	RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
#define	RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
#define	RCC_APB1LPENR_SPI3LPEN_Pos (15U)
#define	RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
#define	RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
#define	RCC_APB1LPENR_USART2LPEN_Pos (17U)
#define	RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
#define	RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
#define	RCC_APB1LPENR_USART3LPEN_Pos (18U)
#define	RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
#define	RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
#define	RCC_APB1LPENR_UART4LPEN_Pos (19U)
#define	RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
#define	RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
#define	RCC_APB1LPENR_UART5LPEN_Pos (20U)
#define	RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
#define	RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
#define	RCC_APB1LPENR_I2C1LPEN_Pos (21U)
#define	RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
#define	RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
#define	RCC_APB1LPENR_I2C2LPEN_Pos (22U)
#define	RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
#define	RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
#define	RCC_APB1LPENR_I2C3LPEN_Pos (23U)
#define	RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
#define	RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
#define	RCC_APB1LPENR_CAN1LPEN_Pos (25U)
#define	RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
#define	RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
#define	RCC_APB1LPENR_CAN2LPEN_Pos (26U)
#define	RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
#define	RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
#define	RCC_APB1LPENR_PWRLPEN_Pos (28U)
#define	RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
#define	RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
#define	RCC_APB1LPENR_DACLPEN_Pos (29U)
#define	RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
#define	RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
#define	RCC_APB2LPENR_TIM1LPEN_Pos (0U)
#define	RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
#define	RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
#define	RCC_APB2LPENR_TIM8LPEN_Pos (1U)
#define	RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
#define	RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
#define	RCC_APB2LPENR_USART1LPEN_Pos (4U)
#define	RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
#define	RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
#define	RCC_APB2LPENR_USART6LPEN_Pos (5U)
#define	RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
#define	RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
#define	RCC_APB2LPENR_ADC1LPEN_Pos (8U)
#define	RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
#define	RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
#define	RCC_APB2LPENR_ADC2LPEN_Pos (9U)
#define	RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
#define	RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
#define	RCC_APB2LPENR_ADC3LPEN_Pos (10U)
#define	RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
#define	RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
#define	RCC_APB2LPENR_SDIOLPEN_Pos (11U)
#define	RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
#define	RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
#define	RCC_APB2LPENR_SPI1LPEN_Pos (12U)
#define	RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
#define	RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
#define	RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
#define	RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
#define	RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
#define	RCC_APB2LPENR_TIM9LPEN_Pos (16U)
#define	RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
#define	RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
#define	RCC_APB2LPENR_TIM10LPEN_Pos (17U)
#define	RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
#define	RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
#define	RCC_APB2LPENR_TIM11LPEN_Pos (18U)
#define	RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
#define	RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
#define	RCC_BDCR_LSEON_Pos (0U)
#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define	RCC_BDCR_LSERDY_Pos (1U)
#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define	RCC_BDCR_LSEBYP_Pos (2U)
#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define	RCC_BDCR_RTCSEL_Pos (8U)
#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
#define	RCC_BDCR_RTCEN_Pos (15U)
#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define	RCC_BDCR_BDRST_Pos (16U)
#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define	RCC_CSR_LSION_Pos (0U)
#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
#define	RCC_CSR_LSION RCC_CSR_LSION_Msk
#define	RCC_CSR_LSIRDY_Pos (1U)
#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define	RCC_CSR_RMVF_Pos (24U)
#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define	RCC_CSR_BORRSTF_Pos (25U)
#define	RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
#define	RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define	RCC_CSR_PINRSTF_Pos (26U)
#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define	RCC_CSR_PORRSTF_Pos (27U)
#define	RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
#define	RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
#define	RCC_CSR_SFTRSTF_Pos (28U)
#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define	RCC_CSR_IWDGRSTF_Pos (29U)
#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define	RCC_CSR_WWDGRSTF_Pos (30U)
#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define	RCC_CSR_LPWRRSTF_Pos (31U)
#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
#define	RCC_CSR_PADRSTF RCC_CSR_PINRSTF
#define	RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
#define	RCC_SSCGR_MODPER_Pos (0U)
#define	RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
#define	RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
#define	RCC_SSCGR_INCSTEP_Pos (13U)
#define	RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
#define	RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
#define	RCC_SSCGR_SPREADSEL_Pos (30U)
#define	RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
#define	RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
#define	RCC_SSCGR_SSCGEN_Pos (31U)
#define	RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
#define	RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
#define	RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
#define	RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
#define	RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
#define	RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
#define	RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#define	RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#define	RNG_CR_RNGEN_Pos (2U)
#define	RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
#define	RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define	RNG_CR_IE_Pos (3U)
#define	RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
#define	RNG_CR_IE RNG_CR_IE_Msk
#define	RNG_SR_DRDY_Pos (0U)
#define	RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
#define	RNG_SR_DRDY RNG_SR_DRDY_Msk
#define	RNG_SR_CECS_Pos (1U)
#define	RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
#define	RNG_SR_CECS RNG_SR_CECS_Msk
#define	RNG_SR_SECS_Pos (2U)
#define	RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
#define	RNG_SR_SECS RNG_SR_SECS_Msk
#define	RNG_SR_CEIS_Pos (5U)
#define	RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
#define	RNG_SR_CEIS RNG_SR_CEIS_Msk
#define	RNG_SR_SEIS_Pos (6U)
#define	RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
#define	RNG_SR_SEIS RNG_SR_SEIS_Msk
#define	RTC_TAMPER2_SUPPORT
#define	RTC_AF2_SUPPORT
#define	RTC_TR_PM_Pos (22U)
#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
#define	RTC_TR_PM RTC_TR_PM_Msk
#define	RTC_TR_HT_Pos (20U)
#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
#define	RTC_TR_HT RTC_TR_HT_Msk
#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
#define	RTC_TR_HU_Pos (16U)
#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
#define	RTC_TR_HU RTC_TR_HU_Msk
#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
#define	RTC_TR_MNT_Pos (12U)
#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
#define	RTC_TR_MNT RTC_TR_MNT_Msk
#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
#define	RTC_TR_MNU_Pos (8U)
#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
#define	RTC_TR_MNU RTC_TR_MNU_Msk
#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
#define	RTC_TR_ST_Pos (4U)
#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
#define	RTC_TR_ST RTC_TR_ST_Msk
#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
#define	RTC_TR_SU_Pos (0U)
#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
#define	RTC_TR_SU RTC_TR_SU_Msk
#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
#define	RTC_DR_YT_Pos (20U)
#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
#define	RTC_DR_YT RTC_DR_YT_Msk
#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
#define	RTC_DR_YU_Pos (16U)
#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
#define	RTC_DR_YU RTC_DR_YU_Msk
#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
#define	RTC_DR_WDU_Pos (13U)
#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
#define	RTC_DR_WDU RTC_DR_WDU_Msk
#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
#define	RTC_DR_MT_Pos (12U)
#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
#define	RTC_DR_MT RTC_DR_MT_Msk
#define	RTC_DR_MU_Pos (8U)
#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
#define	RTC_DR_MU RTC_DR_MU_Msk
#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
#define	RTC_DR_DT_Pos (4U)
#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
#define	RTC_DR_DT RTC_DR_DT_Msk
#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
#define	RTC_DR_DU_Pos (0U)
#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
#define	RTC_DR_DU RTC_DR_DU_Msk
#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
#define	RTC_CR_COE_Pos (23U)
#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
#define	RTC_CR_COE RTC_CR_COE_Msk
#define	RTC_CR_OSEL_Pos (21U)
#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
#define	RTC_CR_OSEL RTC_CR_OSEL_Msk
#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
#define	RTC_CR_POL_Pos (20U)
#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
#define	RTC_CR_POL RTC_CR_POL_Msk
#define	RTC_CR_COSEL_Pos (19U)
#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
#define	RTC_CR_COSEL RTC_CR_COSEL_Msk
#define	RTC_CR_BKP_Pos (18U)
#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
#define	RTC_CR_BKP RTC_CR_BKP_Msk
#define	RTC_CR_SUB1H_Pos (17U)
#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define	RTC_CR_ADD1H_Pos (16U)
#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define	RTC_CR_TSIE_Pos (15U)
#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
#define	RTC_CR_TSIE RTC_CR_TSIE_Msk
#define	RTC_CR_WUTIE_Pos (14U)
#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define	RTC_CR_ALRBIE_Pos (13U)
#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define	RTC_CR_ALRAIE_Pos (12U)
#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define	RTC_CR_TSE_Pos (11U)
#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
#define	RTC_CR_TSE RTC_CR_TSE_Msk
#define	RTC_CR_WUTE_Pos (10U)
#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
#define	RTC_CR_WUTE RTC_CR_WUTE_Msk
#define	RTC_CR_ALRBE_Pos (9U)
#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define	RTC_CR_ALRAE_Pos (8U)
#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define	RTC_CR_DCE_Pos (7U)
#define	RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
#define	RTC_CR_DCE RTC_CR_DCE_Msk
#define	RTC_CR_FMT_Pos (6U)
#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
#define	RTC_CR_FMT RTC_CR_FMT_Msk
#define	RTC_CR_BYPSHAD_Pos (5U)
#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define	RTC_CR_REFCKON_Pos (4U)
#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define	RTC_CR_TSEDGE_Pos (3U)
#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define	RTC_CR_WUCKSEL_Pos (0U)
#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
#define	RTC_CR_BCK RTC_CR_BKP
#define	RTC_ISR_RECALPF_Pos (16U)
#define	RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
#define	RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
#define	RTC_ISR_TAMP1F_Pos (13U)
#define	RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
#define	RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
#define	RTC_ISR_TAMP2F_Pos (14U)
#define	RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
#define	RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
#define	RTC_ISR_TSOVF_Pos (12U)
#define	RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
#define	RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
#define	RTC_ISR_TSF_Pos (11U)
#define	RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
#define	RTC_ISR_TSF RTC_ISR_TSF_Msk
#define	RTC_ISR_WUTF_Pos (10U)
#define	RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
#define	RTC_ISR_WUTF RTC_ISR_WUTF_Msk
#define	RTC_ISR_ALRBF_Pos (9U)
#define	RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
#define	RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
#define	RTC_ISR_ALRAF_Pos (8U)
#define	RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
#define	RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
#define	RTC_ISR_INIT_Pos (7U)
#define	RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
#define	RTC_ISR_INIT RTC_ISR_INIT_Msk
#define	RTC_ISR_INITF_Pos (6U)
#define	RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
#define	RTC_ISR_INITF RTC_ISR_INITF_Msk
#define	RTC_ISR_RSF_Pos (5U)
#define	RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
#define	RTC_ISR_RSF RTC_ISR_RSF_Msk
#define	RTC_ISR_INITS_Pos (4U)
#define	RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
#define	RTC_ISR_INITS RTC_ISR_INITS_Msk
#define	RTC_ISR_SHPF_Pos (3U)
#define	RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
#define	RTC_ISR_SHPF RTC_ISR_SHPF_Msk
#define	RTC_ISR_WUTWF_Pos (2U)
#define	RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
#define	RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
#define	RTC_ISR_ALRBWF_Pos (1U)
#define	RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
#define	RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
#define	RTC_ISR_ALRAWF_Pos (0U)
#define	RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
#define	RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
#define	RTC_PRER_PREDIV_A_Pos (16U)
#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define	RTC_PRER_PREDIV_S_Pos (0U)
#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
#define	RTC_WUTR_WUT_Pos (0U)
#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk
#define	RTC_CALIBR_DCS_Pos (7U)
#define	RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
#define	RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
#define	RTC_CALIBR_DC_Pos (0U)
#define	RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
#define	RTC_CALIBR_DC RTC_CALIBR_DC_Msk
#define	RTC_ALRMAR_MSK4_Pos (31U)
#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define	RTC_ALRMAR_WDSEL_Pos (30U)
#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define	RTC_ALRMAR_DT_Pos (28U)
#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
#define	RTC_ALRMAR_DU_Pos (24U)
#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
#define	RTC_ALRMAR_MSK3_Pos (23U)
#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define	RTC_ALRMAR_PM_Pos (22U)
#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define	RTC_ALRMAR_HT_Pos (20U)
#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
#define	RTC_ALRMAR_HU_Pos (16U)
#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
#define	RTC_ALRMAR_MSK2_Pos (15U)
#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define	RTC_ALRMAR_MNT_Pos (12U)
#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
#define	RTC_ALRMAR_MNU_Pos (8U)
#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
#define	RTC_ALRMAR_MSK1_Pos (7U)
#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define	RTC_ALRMAR_ST_Pos (4U)
#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
#define	RTC_ALRMAR_SU_Pos (0U)
#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
#define	RTC_ALRMBR_MSK4_Pos (31U)
#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define	RTC_ALRMBR_WDSEL_Pos (30U)
#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define	RTC_ALRMBR_DT_Pos (28U)
#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
#define	RTC_ALRMBR_DU_Pos (24U)
#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
#define	RTC_ALRMBR_MSK3_Pos (23U)
#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define	RTC_ALRMBR_PM_Pos (22U)
#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define	RTC_ALRMBR_HT_Pos (20U)
#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
#define	RTC_ALRMBR_HU_Pos (16U)
#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
#define	RTC_ALRMBR_MSK2_Pos (15U)
#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define	RTC_ALRMBR_MNT_Pos (12U)
#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
#define	RTC_ALRMBR_MNU_Pos (8U)
#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
#define	RTC_ALRMBR_MSK1_Pos (7U)
#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define	RTC_ALRMBR_ST_Pos (4U)
#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
#define	RTC_ALRMBR_SU_Pos (0U)
#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
#define	RTC_WPR_KEY_Pos (0U)
#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
#define	RTC_WPR_KEY RTC_WPR_KEY_Msk
#define	RTC_SSR_SS_Pos (0U)
#define	RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
#define	RTC_SSR_SS RTC_SSR_SS_Msk
#define	RTC_SHIFTR_SUBFS_Pos (0U)
#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define	RTC_SHIFTR_ADD1S_Pos (31U)
#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
#define	RTC_TSTR_PM_Pos (22U)
#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
#define	RTC_TSTR_PM RTC_TSTR_PM_Msk
#define	RTC_TSTR_HT_Pos (20U)
#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
#define	RTC_TSTR_HT RTC_TSTR_HT_Msk
#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
#define	RTC_TSTR_HU_Pos (16U)
#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
#define	RTC_TSTR_HU RTC_TSTR_HU_Msk
#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
#define	RTC_TSTR_MNT_Pos (12U)
#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
#define	RTC_TSTR_MNU_Pos (8U)
#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
#define	RTC_TSTR_ST_Pos (4U)
#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
#define	RTC_TSTR_ST RTC_TSTR_ST_Msk
#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
#define	RTC_TSTR_SU_Pos (0U)
#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
#define	RTC_TSTR_SU RTC_TSTR_SU_Msk
#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
#define	RTC_TSDR_WDU_Pos (13U)
#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
#define	RTC_TSDR_MT_Pos (12U)
#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
#define	RTC_TSDR_MT RTC_TSDR_MT_Msk
#define	RTC_TSDR_MU_Pos (8U)
#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
#define	RTC_TSDR_MU RTC_TSDR_MU_Msk
#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
#define	RTC_TSDR_DT_Pos (4U)
#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
#define	RTC_TSDR_DT RTC_TSDR_DT_Msk
#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
#define	RTC_TSDR_DU_Pos (0U)
#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
#define	RTC_TSDR_DU RTC_TSDR_DU_Msk
#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
#define	RTC_TSSSR_SS_Pos (0U)
#define	RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk
#define	RTC_CALR_CALP_Pos (15U)
#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
#define	RTC_CALR_CALP RTC_CALR_CALP_Msk
#define	RTC_CALR_CALW8_Pos (14U)
#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define	RTC_CALR_CALW16_Pos (13U)
#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define	RTC_CALR_CALM_Pos (0U)
#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM RTC_CALR_CALM_Msk
#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
#define	RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
#define	RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
#define	RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
#define	RTC_TAFCR_TSINSEL_Pos (17U)
#define	RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
#define	RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
#define	RTC_TAFCR_TAMP1INSEL_Pos (16U)
#define	RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
#define	RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
#define	RTC_TAFCR_TAMPPUDIS_Pos (15U)
#define	RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
#define	RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
#define	RTC_TAFCR_TAMPPRCH_Pos (13U)
#define	RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
#define	RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
#define	RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
#define	RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
#define	RTC_TAFCR_TAMPFLT_Pos (11U)
#define	RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
#define	RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
#define	RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
#define	RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
#define	RTC_TAFCR_TAMPFREQ_Pos (8U)
#define	RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
#define	RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
#define	RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
#define	RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
#define	RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
#define	RTC_TAFCR_TAMPTS_Pos (7U)
#define	RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
#define	RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
#define	RTC_TAFCR_TAMP2TRG_Pos (4U)
#define	RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
#define	RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
#define	RTC_TAFCR_TAMP2E_Pos (3U)
#define	RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
#define	RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
#define	RTC_TAFCR_TAMPIE_Pos (2U)
#define	RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
#define	RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
#define	RTC_TAFCR_TAMP1TRG_Pos (1U)
#define	RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
#define	RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
#define	RTC_TAFCR_TAMP1E_Pos (0U)
#define	RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
#define	RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
#define	RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
#define	RTC_ALRMASSR_MASKSS_Pos (24U)
#define	RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
#define	RTC_ALRMASSR_SS_Pos (0U)
#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
#define	RTC_ALRMBSSR_MASKSS_Pos (24U)
#define	RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
#define	RTC_ALRMBSSR_SS_Pos (0U)
#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
#define	RTC_BKP0R_Pos (0U)
#define	RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
#define	RTC_BKP0R RTC_BKP0R_Msk
#define	RTC_BKP1R_Pos (0U)
#define	RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
#define	RTC_BKP1R RTC_BKP1R_Msk
#define	RTC_BKP2R_Pos (0U)
#define	RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
#define	RTC_BKP2R RTC_BKP2R_Msk
#define	RTC_BKP3R_Pos (0U)
#define	RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
#define	RTC_BKP3R RTC_BKP3R_Msk
#define	RTC_BKP4R_Pos (0U)
#define	RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
#define	RTC_BKP4R RTC_BKP4R_Msk
#define	RTC_BKP5R_Pos (0U)
#define	RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
#define	RTC_BKP5R RTC_BKP5R_Msk
#define	RTC_BKP6R_Pos (0U)
#define	RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
#define	RTC_BKP6R RTC_BKP6R_Msk
#define	RTC_BKP7R_Pos (0U)
#define	RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
#define	RTC_BKP7R RTC_BKP7R_Msk
#define	RTC_BKP8R_Pos (0U)
#define	RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
#define	RTC_BKP8R RTC_BKP8R_Msk
#define	RTC_BKP9R_Pos (0U)
#define	RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
#define	RTC_BKP9R RTC_BKP9R_Msk
#define	RTC_BKP10R_Pos (0U)
#define	RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
#define	RTC_BKP10R RTC_BKP10R_Msk
#define	RTC_BKP11R_Pos (0U)
#define	RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
#define	RTC_BKP11R RTC_BKP11R_Msk
#define	RTC_BKP12R_Pos (0U)
#define	RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
#define	RTC_BKP12R RTC_BKP12R_Msk
#define	RTC_BKP13R_Pos (0U)
#define	RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
#define	RTC_BKP13R RTC_BKP13R_Msk
#define	RTC_BKP14R_Pos (0U)
#define	RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
#define	RTC_BKP14R RTC_BKP14R_Msk
#define	RTC_BKP15R_Pos (0U)
#define	RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
#define	RTC_BKP15R RTC_BKP15R_Msk
#define	RTC_BKP16R_Pos (0U)
#define	RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
#define	RTC_BKP16R RTC_BKP16R_Msk
#define	RTC_BKP17R_Pos (0U)
#define	RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
#define	RTC_BKP17R RTC_BKP17R_Msk
#define	RTC_BKP18R_Pos (0U)
#define	RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
#define	RTC_BKP18R RTC_BKP18R_Msk
#define	RTC_BKP19R_Pos (0U)
#define	RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
#define	RTC_BKP19R RTC_BKP19R_Msk
#define	RTC_BKP_NUMBER 0x000000014U
#define	SDIO_POWER_PWRCTRL_Pos (0U)
#define	SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
#define	SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
#define	SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
#define	SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
#define	SDIO_CLKCR_CLKDIV_Pos (0U)
#define	SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
#define	SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
#define	SDIO_CLKCR_CLKEN_Pos (8U)
#define	SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
#define	SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
#define	SDIO_CLKCR_PWRSAV_Pos (9U)
#define	SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
#define	SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
#define	SDIO_CLKCR_BYPASS_Pos (10U)
#define	SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
#define	SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
#define	SDIO_CLKCR_WIDBUS_Pos (11U)
#define	SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
#define	SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
#define	SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
#define	SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
#define	SDIO_CLKCR_NEGEDGE_Pos (13U)
#define	SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
#define	SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
#define	SDIO_CLKCR_HWFC_EN_Pos (14U)
#define	SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
#define	SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
#define	SDIO_ARG_CMDARG_Pos (0U)
#define	SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
#define	SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
#define	SDIO_CMD_CMDINDEX_Pos (0U)
#define	SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
#define	SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
#define	SDIO_CMD_WAITRESP_Pos (6U)
#define	SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
#define	SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
#define	SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
#define	SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
#define	SDIO_CMD_WAITINT_Pos (8U)
#define	SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
#define	SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
#define	SDIO_CMD_WAITPEND_Pos (9U)
#define	SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
#define	SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
#define	SDIO_CMD_CPSMEN_Pos (10U)
#define	SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
#define	SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
#define	SDIO_CMD_SDIOSUSPEND_Pos (11U)
#define	SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
#define	SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
#define	SDIO_CMD_ENCMDCOMPL_Pos (12U)
#define	SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
#define	SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
#define	SDIO_CMD_NIEN_Pos (13U)
#define	SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
#define	SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
#define	SDIO_CMD_CEATACMD_Pos (14U)
#define	SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
#define	SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
#define	SDIO_RESPCMD_RESPCMD_Pos (0U)
#define	SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
#define	SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
#define	SDIO_RESP0_CARDSTATUS0_Pos (0U)
#define	SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
#define	SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
#define	SDIO_RESP1_CARDSTATUS1_Pos (0U)
#define	SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
#define	SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
#define	SDIO_RESP2_CARDSTATUS2_Pos (0U)
#define	SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
#define	SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
#define	SDIO_RESP3_CARDSTATUS3_Pos (0U)
#define	SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
#define	SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
#define	SDIO_RESP4_CARDSTATUS4_Pos (0U)
#define	SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
#define	SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
#define	SDIO_DTIMER_DATATIME_Pos (0U)
#define	SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
#define	SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
#define	SDIO_DLEN_DATALENGTH_Pos (0U)
#define	SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
#define	SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
#define	SDIO_DCTRL_DTEN_Pos (0U)
#define	SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
#define	SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
#define	SDIO_DCTRL_DTDIR_Pos (1U)
#define	SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
#define	SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
#define	SDIO_DCTRL_DTMODE_Pos (2U)
#define	SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
#define	SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
#define	SDIO_DCTRL_DMAEN_Pos (3U)
#define	SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
#define	SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
#define	SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
#define	SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
#define	SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
#define	SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
#define	SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
#define	SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
#define	SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
#define	SDIO_DCTRL_RWSTART_Pos (8U)
#define	SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
#define	SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
#define	SDIO_DCTRL_RWSTOP_Pos (9U)
#define	SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
#define	SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
#define	SDIO_DCTRL_RWMOD_Pos (10U)
#define	SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
#define	SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
#define	SDIO_DCTRL_SDIOEN_Pos (11U)
#define	SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
#define	SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
#define	SDIO_DCOUNT_DATACOUNT_Pos (0U)
#define	SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
#define	SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
#define	SDIO_STA_CCRCFAIL_Pos (0U)
#define	SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
#define	SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
#define	SDIO_STA_DCRCFAIL_Pos (1U)
#define	SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
#define	SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
#define	SDIO_STA_CTIMEOUT_Pos (2U)
#define	SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
#define	SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
#define	SDIO_STA_DTIMEOUT_Pos (3U)
#define	SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
#define	SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
#define	SDIO_STA_TXUNDERR_Pos (4U)
#define	SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
#define	SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
#define	SDIO_STA_RXOVERR_Pos (5U)
#define	SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
#define	SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
#define	SDIO_STA_CMDREND_Pos (6U)
#define	SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
#define	SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
#define	SDIO_STA_CMDSENT_Pos (7U)
#define	SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
#define	SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
#define	SDIO_STA_DATAEND_Pos (8U)
#define	SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
#define	SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
#define	SDIO_STA_STBITERR_Pos (9U)
#define	SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
#define	SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
#define	SDIO_STA_DBCKEND_Pos (10U)
#define	SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
#define	SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
#define	SDIO_STA_CMDACT_Pos (11U)
#define	SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
#define	SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
#define	SDIO_STA_TXACT_Pos (12U)
#define	SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
#define	SDIO_STA_TXACT SDIO_STA_TXACT_Msk
#define	SDIO_STA_RXACT_Pos (13U)
#define	SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
#define	SDIO_STA_RXACT SDIO_STA_RXACT_Msk
#define	SDIO_STA_TXFIFOHE_Pos (14U)
#define	SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
#define	SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
#define	SDIO_STA_RXFIFOHF_Pos (15U)
#define	SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
#define	SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
#define	SDIO_STA_TXFIFOF_Pos (16U)
#define	SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
#define	SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
#define	SDIO_STA_RXFIFOF_Pos (17U)
#define	SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
#define	SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
#define	SDIO_STA_TXFIFOE_Pos (18U)
#define	SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
#define	SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
#define	SDIO_STA_RXFIFOE_Pos (19U)
#define	SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
#define	SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
#define	SDIO_STA_TXDAVL_Pos (20U)
#define	SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
#define	SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
#define	SDIO_STA_RXDAVL_Pos (21U)
#define	SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
#define	SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
#define	SDIO_STA_SDIOIT_Pos (22U)
#define	SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
#define	SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
#define	SDIO_STA_CEATAEND_Pos (23U)
#define	SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
#define	SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
#define	SDIO_ICR_CCRCFAILC_Pos (0U)
#define	SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
#define	SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
#define	SDIO_ICR_DCRCFAILC_Pos (1U)
#define	SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
#define	SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
#define	SDIO_ICR_CTIMEOUTC_Pos (2U)
#define	SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
#define	SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
#define	SDIO_ICR_DTIMEOUTC_Pos (3U)
#define	SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
#define	SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
#define	SDIO_ICR_TXUNDERRC_Pos (4U)
#define	SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
#define	SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
#define	SDIO_ICR_RXOVERRC_Pos (5U)
#define	SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
#define	SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
#define	SDIO_ICR_CMDRENDC_Pos (6U)
#define	SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
#define	SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
#define	SDIO_ICR_CMDSENTC_Pos (7U)
#define	SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
#define	SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
#define	SDIO_ICR_DATAENDC_Pos (8U)
#define	SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
#define	SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
#define	SDIO_ICR_STBITERRC_Pos (9U)
#define	SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
#define	SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
#define	SDIO_ICR_DBCKENDC_Pos (10U)
#define	SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
#define	SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
#define	SDIO_ICR_SDIOITC_Pos (22U)
#define	SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
#define	SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
#define	SDIO_ICR_CEATAENDC_Pos (23U)
#define	SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
#define	SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
#define	SDIO_MASK_CCRCFAILIE_Pos (0U)
#define	SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
#define	SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
#define	SDIO_MASK_DCRCFAILIE_Pos (1U)
#define	SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
#define	SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
#define	SDIO_MASK_CTIMEOUTIE_Pos (2U)
#define	SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
#define	SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
#define	SDIO_MASK_DTIMEOUTIE_Pos (3U)
#define	SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
#define	SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
#define	SDIO_MASK_TXUNDERRIE_Pos (4U)
#define	SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
#define	SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
#define	SDIO_MASK_RXOVERRIE_Pos (5U)
#define	SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
#define	SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
#define	SDIO_MASK_CMDRENDIE_Pos (6U)
#define	SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
#define	SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
#define	SDIO_MASK_CMDSENTIE_Pos (7U)
#define	SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
#define	SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
#define	SDIO_MASK_DATAENDIE_Pos (8U)
#define	SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
#define	SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
#define	SDIO_MASK_STBITERRIE_Pos (9U)
#define	SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
#define	SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
#define	SDIO_MASK_DBCKENDIE_Pos (10U)
#define	SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
#define	SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
#define	SDIO_MASK_CMDACTIE_Pos (11U)
#define	SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
#define	SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
#define	SDIO_MASK_TXACTIE_Pos (12U)
#define	SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
#define	SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
#define	SDIO_MASK_RXACTIE_Pos (13U)
#define	SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
#define	SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
#define	SDIO_MASK_TXFIFOHEIE_Pos (14U)
#define	SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
#define	SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
#define	SDIO_MASK_RXFIFOHFIE_Pos (15U)
#define	SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
#define	SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
#define	SDIO_MASK_TXFIFOFIE_Pos (16U)
#define	SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
#define	SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
#define	SDIO_MASK_RXFIFOFIE_Pos (17U)
#define	SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
#define	SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
#define	SDIO_MASK_TXFIFOEIE_Pos (18U)
#define	SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
#define	SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
#define	SDIO_MASK_RXFIFOEIE_Pos (19U)
#define	SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
#define	SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
#define	SDIO_MASK_TXDAVLIE_Pos (20U)
#define	SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
#define	SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
#define	SDIO_MASK_RXDAVLIE_Pos (21U)
#define	SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
#define	SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
#define	SDIO_MASK_SDIOITIE_Pos (22U)
#define	SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
#define	SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
#define	SDIO_MASK_CEATAENDIE_Pos (23U)
#define	SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
#define	SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
#define	SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
#define	SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
#define	SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
#define	SDIO_FIFO_FIFODATA_Pos (0U)
#define	SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
#define	SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
#define	SPI_I2S_FULLDUPLEX_SUPPORT
#define	SPI_CR1_CPHA_Pos (0U)
#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk
#define	SPI_CR1_CPOL_Pos (1U)
#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk
#define	SPI_CR1_MSTR_Pos (2U)
#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk
#define	SPI_CR1_BR_Pos (3U)
#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
#define	SPI_CR1_BR SPI_CR1_BR_Msk
#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
#define	SPI_CR1_SPE_Pos (6U)
#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
#define	SPI_CR1_SPE SPI_CR1_SPE_Msk
#define	SPI_CR1_LSBFIRST_Pos (7U)
#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
#define	SPI_CR1_SSI_Pos (8U)
#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
#define	SPI_CR1_SSI SPI_CR1_SSI_Msk
#define	SPI_CR1_SSM_Pos (9U)
#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
#define	SPI_CR1_SSM SPI_CR1_SSM_Msk
#define	SPI_CR1_RXONLY_Pos (10U)
#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
#define	SPI_CR1_DFF_Pos (11U)
#define	SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
#define	SPI_CR1_DFF SPI_CR1_DFF_Msk
#define	SPI_CR1_CRCNEXT_Pos (12U)
#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
#define	SPI_CR1_CRCEN_Pos (13U)
#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
#define	SPI_CR1_BIDIOE_Pos (14U)
#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
#define	SPI_CR1_BIDIMODE_Pos (15U)
#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
#define	SPI_CR2_RXDMAEN_Pos (0U)
#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
#define	SPI_CR2_TXDMAEN_Pos (1U)
#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
#define	SPI_CR2_SSOE_Pos (2U)
#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk
#define	SPI_CR2_FRF_Pos (4U)
#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
#define	SPI_CR2_FRF SPI_CR2_FRF_Msk
#define	SPI_CR2_ERRIE_Pos (5U)
#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
#define	SPI_CR2_RXNEIE_Pos (6U)
#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
#define	SPI_CR2_TXEIE_Pos (7U)
#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
#define	SPI_SR_RXNE_Pos (0U)
#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
#define	SPI_SR_RXNE SPI_SR_RXNE_Msk
#define	SPI_SR_TXE_Pos (1U)
#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
#define	SPI_SR_TXE SPI_SR_TXE_Msk
#define	SPI_SR_CHSIDE_Pos (2U)
#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
#define	SPI_SR_UDR_Pos (3U)
#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
#define	SPI_SR_UDR SPI_SR_UDR_Msk
#define	SPI_SR_CRCERR_Pos (4U)
#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk
#define	SPI_SR_MODF_Pos (5U)
#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
#define	SPI_SR_MODF SPI_SR_MODF_Msk
#define	SPI_SR_OVR_Pos (6U)
#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
#define	SPI_SR_OVR SPI_SR_OVR_Msk
#define	SPI_SR_BSY_Pos (7U)
#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
#define	SPI_SR_BSY SPI_SR_BSY_Msk
#define	SPI_SR_FRE_Pos (8U)
#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
#define	SPI_SR_FRE SPI_SR_FRE_Msk
#define	SPI_DR_DR_Pos (0U)
#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
#define	SPI_DR_DR SPI_DR_DR_Msk
#define	SPI_CRCPR_CRCPOLY_Pos (0U)
#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
#define	SPI_RXCRCR_RXCRC_Pos (0U)
#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
#define	SPI_TXCRCR_TXCRC_Pos (0U)
#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
#define	SPI_I2SCFGR_CHLEN_Pos (0U)
#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
#define	SPI_I2SCFGR_DATLEN_Pos (1U)
#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
#define	SPI_I2SCFGR_CKPOL_Pos (3U)
#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
#define	SPI_I2SCFGR_I2SSTD_Pos (4U)
#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
#define	SPI_I2SCFGR_I2SCFG_Pos (8U)
#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
#define	SPI_I2SCFGR_I2SE_Pos (10U)
#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
#define	SPI_I2SCFGR_I2SMOD_Pos (11U)
#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
#define	SPI_I2SPR_I2SDIV_Pos (0U)
#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
#define	SPI_I2SPR_ODD_Pos (8U)
#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
#define	SPI_I2SPR_MCKOE_Pos (9U)
#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
#define	SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define	SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
#define	SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
#define	SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
#define	SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
#define	SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
#define	SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
#define	SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
#define	SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
#define	SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define	SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
#define	SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
#define	SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define	SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
#define	SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
#define	SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define	SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
#define	SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
#define	SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define	SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
#define	SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
#define	SYSCFG_EXTICR1_EXTI0_PA 0x0000U
	EXTI0 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PB 0x0001U
#define	SYSCFG_EXTICR1_EXTI0_PC 0x0002U
#define	SYSCFG_EXTICR1_EXTI0_PD 0x0003U
#define	SYSCFG_EXTICR1_EXTI0_PE 0x0004U
#define	SYSCFG_EXTICR1_EXTI0_PF 0x0005U
#define	SYSCFG_EXTICR1_EXTI0_PG 0x0006U
#define	SYSCFG_EXTICR1_EXTI0_PH 0x0007U
#define	SYSCFG_EXTICR1_EXTI0_PI 0x0008U
#define	SYSCFG_EXTICR1_EXTI1_PA 0x0000U
	EXTI1 configuration.
#define	SYSCFG_EXTICR1_EXTI1_PB 0x0010U
#define	SYSCFG_EXTICR1_EXTI1_PC 0x0020U
#define	SYSCFG_EXTICR1_EXTI1_PD 0x0030U
#define	SYSCFG_EXTICR1_EXTI1_PE 0x0040U
#define	SYSCFG_EXTICR1_EXTI1_PF 0x0050U
#define	SYSCFG_EXTICR1_EXTI1_PG 0x0060U
#define	SYSCFG_EXTICR1_EXTI1_PH 0x0070U
#define	SYSCFG_EXTICR1_EXTI1_PI 0x0080U
#define	SYSCFG_EXTICR1_EXTI2_PA 0x0000U
	EXTI2 configuration.
#define	SYSCFG_EXTICR1_EXTI2_PB 0x0100U
#define	SYSCFG_EXTICR1_EXTI2_PC 0x0200U
#define	SYSCFG_EXTICR1_EXTI2_PD 0x0300U
#define	SYSCFG_EXTICR1_EXTI2_PE 0x0400U
#define	SYSCFG_EXTICR1_EXTI2_PF 0x0500U
#define	SYSCFG_EXTICR1_EXTI2_PG 0x0600U
#define	SYSCFG_EXTICR1_EXTI2_PH 0x0700U
#define	SYSCFG_EXTICR1_EXTI2_PI 0x0800U
#define	SYSCFG_EXTICR1_EXTI3_PA 0x0000U
	EXTI3 configuration.
#define	SYSCFG_EXTICR1_EXTI3_PB 0x1000U
#define	SYSCFG_EXTICR1_EXTI3_PC 0x2000U
#define	SYSCFG_EXTICR1_EXTI3_PD 0x3000U
#define	SYSCFG_EXTICR1_EXTI3_PE 0x4000U
#define	SYSCFG_EXTICR1_EXTI3_PF 0x5000U
#define	SYSCFG_EXTICR1_EXTI3_PG 0x6000U
#define	SYSCFG_EXTICR1_EXTI3_PH 0x7000U
#define	SYSCFG_EXTICR1_EXTI3_PI 0x8000U
#define	SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define	SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
#define	SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
#define	SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define	SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
#define	SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
#define	SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define	SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
#define	SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
#define	SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define	SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
#define	SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
#define	SYSCFG_EXTICR2_EXTI4_PA 0x0000U
	EXTI4 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PB 0x0001U
#define	SYSCFG_EXTICR2_EXTI4_PC 0x0002U
#define	SYSCFG_EXTICR2_EXTI4_PD 0x0003U
#define	SYSCFG_EXTICR2_EXTI4_PE 0x0004U
#define	SYSCFG_EXTICR2_EXTI4_PF 0x0005U
#define	SYSCFG_EXTICR2_EXTI4_PG 0x0006U
#define	SYSCFG_EXTICR2_EXTI4_PH 0x0007U
#define	SYSCFG_EXTICR2_EXTI4_PI 0x0008U
#define	SYSCFG_EXTICR2_EXTI5_PA 0x0000U
	EXTI5 configuration.
#define	SYSCFG_EXTICR2_EXTI5_PB 0x0010U
#define	SYSCFG_EXTICR2_EXTI5_PC 0x0020U
#define	SYSCFG_EXTICR2_EXTI5_PD 0x0030U
#define	SYSCFG_EXTICR2_EXTI5_PE 0x0040U
#define	SYSCFG_EXTICR2_EXTI5_PF 0x0050U
#define	SYSCFG_EXTICR2_EXTI5_PG 0x0060U
#define	SYSCFG_EXTICR2_EXTI5_PH 0x0070U
#define	SYSCFG_EXTICR2_EXTI5_PI 0x0080U
#define	SYSCFG_EXTICR2_EXTI6_PA 0x0000U
	EXTI6 configuration.
#define	SYSCFG_EXTICR2_EXTI6_PB 0x0100U
#define	SYSCFG_EXTICR2_EXTI6_PC 0x0200U
#define	SYSCFG_EXTICR2_EXTI6_PD 0x0300U
#define	SYSCFG_EXTICR2_EXTI6_PE 0x0400U
#define	SYSCFG_EXTICR2_EXTI6_PF 0x0500U
#define	SYSCFG_EXTICR2_EXTI6_PG 0x0600U
#define	SYSCFG_EXTICR2_EXTI6_PH 0x0700U
#define	SYSCFG_EXTICR2_EXTI6_PI 0x0800U
#define	SYSCFG_EXTICR2_EXTI7_PA 0x0000U
	EXTI7 configuration.
#define	SYSCFG_EXTICR2_EXTI7_PB 0x1000U
#define	SYSCFG_EXTICR2_EXTI7_PC 0x2000U
#define	SYSCFG_EXTICR2_EXTI7_PD 0x3000U
#define	SYSCFG_EXTICR2_EXTI7_PE 0x4000U
#define	SYSCFG_EXTICR2_EXTI7_PF 0x5000U
#define	SYSCFG_EXTICR2_EXTI7_PG 0x6000U
#define	SYSCFG_EXTICR2_EXTI7_PH 0x7000U
#define	SYSCFG_EXTICR2_EXTI7_PI 0x8000U
#define	SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define	SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
#define	SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
#define	SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define	SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
#define	SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
#define	SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define	SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
#define	SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
#define	SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define	SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
#define	SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
#define	SYSCFG_EXTICR3_EXTI8_PA 0x0000U
	EXTI8 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PB 0x0001U
#define	SYSCFG_EXTICR3_EXTI8_PC 0x0002U
#define	SYSCFG_EXTICR3_EXTI8_PD 0x0003U
#define	SYSCFG_EXTICR3_EXTI8_PE 0x0004U
#define	SYSCFG_EXTICR3_EXTI8_PF 0x0005U
#define	SYSCFG_EXTICR3_EXTI8_PG 0x0006U
#define	SYSCFG_EXTICR3_EXTI8_PH 0x0007U
#define	SYSCFG_EXTICR3_EXTI8_PI 0x0008U
#define	SYSCFG_EXTICR3_EXTI9_PA 0x0000U
	EXTI9 configuration.
#define	SYSCFG_EXTICR3_EXTI9_PB 0x0010U
#define	SYSCFG_EXTICR3_EXTI9_PC 0x0020U
#define	SYSCFG_EXTICR3_EXTI9_PD 0x0030U
#define	SYSCFG_EXTICR3_EXTI9_PE 0x0040U
#define	SYSCFG_EXTICR3_EXTI9_PF 0x0050U
#define	SYSCFG_EXTICR3_EXTI9_PG 0x0060U
#define	SYSCFG_EXTICR3_EXTI9_PH 0x0070U
#define	SYSCFG_EXTICR3_EXTI9_PI 0x0080U
#define	SYSCFG_EXTICR3_EXTI10_PA 0x0000U
	EXTI10 configuration.
#define	SYSCFG_EXTICR3_EXTI10_PB 0x0100U
#define	SYSCFG_EXTICR3_EXTI10_PC 0x0200U
#define	SYSCFG_EXTICR3_EXTI10_PD 0x0300U
#define	SYSCFG_EXTICR3_EXTI10_PE 0x0400U
#define	SYSCFG_EXTICR3_EXTI10_PF 0x0500U
#define	SYSCFG_EXTICR3_EXTI10_PG 0x0600U
#define	SYSCFG_EXTICR3_EXTI10_PH 0x0700U
#define	SYSCFG_EXTICR3_EXTI10_PI 0x0800U
#define	SYSCFG_EXTICR3_EXTI11_PA 0x0000U
	EXTI11 configuration.
#define	SYSCFG_EXTICR3_EXTI11_PB 0x1000U
#define	SYSCFG_EXTICR3_EXTI11_PC 0x2000U
#define	SYSCFG_EXTICR3_EXTI11_PD 0x3000U
#define	SYSCFG_EXTICR3_EXTI11_PE 0x4000U
#define	SYSCFG_EXTICR3_EXTI11_PF 0x5000U
#define	SYSCFG_EXTICR3_EXTI11_PG 0x6000U
#define	SYSCFG_EXTICR3_EXTI11_PH 0x7000U
#define	SYSCFG_EXTICR3_EXTI11_PI 0x8000U
#define	SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define	SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
#define	SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
#define	SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define	SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
#define	SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
#define	SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define	SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
#define	SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
#define	SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define	SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
#define	SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
#define	SYSCFG_EXTICR4_EXTI12_PA 0x0000U
	EXTI12 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PB 0x0001U
#define	SYSCFG_EXTICR4_EXTI12_PC 0x0002U
#define	SYSCFG_EXTICR4_EXTI12_PD 0x0003U
#define	SYSCFG_EXTICR4_EXTI12_PE 0x0004U
#define	SYSCFG_EXTICR4_EXTI12_PF 0x0005U
#define	SYSCFG_EXTICR4_EXTI12_PG 0x0006U
#define	SYSCFG_EXTICR4_EXTI12_PH 0x0007U
#define	SYSCFG_EXTICR4_EXTI13_PA 0x0000U
	EXTI13 configuration.
#define	SYSCFG_EXTICR4_EXTI13_PB 0x0010U
#define	SYSCFG_EXTICR4_EXTI13_PC 0x0020U
#define	SYSCFG_EXTICR4_EXTI13_PD 0x0030U
#define	SYSCFG_EXTICR4_EXTI13_PE 0x0040U
#define	SYSCFG_EXTICR4_EXTI13_PF 0x0050U
#define	SYSCFG_EXTICR4_EXTI13_PG 0x0060U
#define	SYSCFG_EXTICR4_EXTI13_PH 0x0070U
#define	SYSCFG_EXTICR4_EXTI14_PA 0x0000U
	EXTI14 configuration.
#define	SYSCFG_EXTICR4_EXTI14_PB 0x0100U
#define	SYSCFG_EXTICR4_EXTI14_PC 0x0200U
#define	SYSCFG_EXTICR4_EXTI14_PD 0x0300U
#define	SYSCFG_EXTICR4_EXTI14_PE 0x0400U
#define	SYSCFG_EXTICR4_EXTI14_PF 0x0500U
#define	SYSCFG_EXTICR4_EXTI14_PG 0x0600U
#define	SYSCFG_EXTICR4_EXTI14_PH 0x0700U
#define	SYSCFG_EXTICR4_EXTI15_PA 0x0000U
	EXTI15 configuration.
#define	SYSCFG_EXTICR4_EXTI15_PB 0x1000U
#define	SYSCFG_EXTICR4_EXTI15_PC 0x2000U
#define	SYSCFG_EXTICR4_EXTI15_PD 0x3000U
#define	SYSCFG_EXTICR4_EXTI15_PE 0x4000U
#define	SYSCFG_EXTICR4_EXTI15_PF 0x5000U
#define	SYSCFG_EXTICR4_EXTI15_PG 0x6000U
#define	SYSCFG_EXTICR4_EXTI15_PH 0x7000U
#define	SYSCFG_CMPCR_CMP_PD_Pos (0U)
#define	SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
#define	SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
#define	SYSCFG_CMPCR_READY_Pos (8U)
#define	SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
#define	SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
#define	TIM_CR1_CEN_Pos (0U)
#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
#define	TIM_CR1_CEN TIM_CR1_CEN_Msk
#define	TIM_CR1_UDIS_Pos (1U)
#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk
#define	TIM_CR1_URS_Pos (2U)
#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
#define	TIM_CR1_URS TIM_CR1_URS_Msk
#define	TIM_CR1_OPM_Pos (3U)
#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
#define	TIM_CR1_OPM TIM_CR1_OPM_Msk
#define	TIM_CR1_DIR_Pos (4U)
#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
#define	TIM_CR1_DIR TIM_CR1_DIR_Msk
#define	TIM_CR1_CMS_Pos (5U)
#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
#define	TIM_CR1_CMS TIM_CR1_CMS_Msk
#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
#define	TIM_CR1_ARPE_Pos (7U)
#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk
#define	TIM_CR1_CKD_Pos (8U)
#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
#define	TIM_CR1_CKD TIM_CR1_CKD_Msk
#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
#define	TIM_CR2_CCPC_Pos (0U)
#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk
#define	TIM_CR2_CCUS_Pos (2U)
#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk
#define	TIM_CR2_CCDS_Pos (3U)
#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk
#define	TIM_CR2_MMS_Pos (4U)
#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
#define	TIM_CR2_MMS TIM_CR2_MMS_Msk
#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
#define	TIM_CR2_TI1S_Pos (7U)
#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk
#define	TIM_CR2_OIS1_Pos (8U)
#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
#define	TIM_CR2_OIS1N_Pos (9U)
#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
#define	TIM_CR2_OIS2_Pos (10U)
#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
#define	TIM_CR2_OIS2N_Pos (11U)
#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
#define	TIM_CR2_OIS3_Pos (12U)
#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
#define	TIM_CR2_OIS3N_Pos (13U)
#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
#define	TIM_CR2_OIS4_Pos (14U)
#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
#define	TIM_SMCR_SMS_Pos (0U)
#define	TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk
#define	TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
#define	TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
#define	TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
#define	TIM_SMCR_TS_Pos (4U)
#define	TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
#define	TIM_SMCR_TS TIM_SMCR_TS_Msk
#define	TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
#define	TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
#define	TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
#define	TIM_SMCR_MSM_Pos (7U)
#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk
#define	TIM_SMCR_ETF_Pos (8U)
#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk
#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
#define	TIM_SMCR_ETPS_Pos (12U)
#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
#define	TIM_SMCR_ECE_Pos (14U)
#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk
#define	TIM_SMCR_ETP_Pos (15U)
#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk
#define	TIM_DIER_UIE_Pos (0U)
#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
#define	TIM_DIER_UIE TIM_DIER_UIE_Msk
#define	TIM_DIER_CC1IE_Pos (1U)
#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
#define	TIM_DIER_CC2IE_Pos (2U)
#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
#define	TIM_DIER_CC3IE_Pos (3U)
#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
#define	TIM_DIER_CC4IE_Pos (4U)
#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
#define	TIM_DIER_COMIE_Pos (5U)
#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk
#define	TIM_DIER_TIE_Pos (6U)
#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
#define	TIM_DIER_TIE TIM_DIER_TIE_Msk
#define	TIM_DIER_BIE_Pos (7U)
#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
#define	TIM_DIER_BIE TIM_DIER_BIE_Msk
#define	TIM_DIER_UDE_Pos (8U)
#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
#define	TIM_DIER_UDE TIM_DIER_UDE_Msk
#define	TIM_DIER_CC1DE_Pos (9U)
#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
#define	TIM_DIER_CC2DE_Pos (10U)
#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
#define	TIM_DIER_CC3DE_Pos (11U)
#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
#define	TIM_DIER_CC4DE_Pos (12U)
#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
#define	TIM_DIER_COMDE_Pos (13U)
#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk
#define	TIM_DIER_TDE_Pos (14U)
#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
#define	TIM_DIER_TDE TIM_DIER_TDE_Msk
#define	TIM_SR_UIF_Pos (0U)
#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
#define	TIM_SR_UIF TIM_SR_UIF_Msk
#define	TIM_SR_CC1IF_Pos (1U)
#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk
#define	TIM_SR_CC2IF_Pos (2U)
#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk
#define	TIM_SR_CC3IF_Pos (3U)
#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk
#define	TIM_SR_CC4IF_Pos (4U)
#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk
#define	TIM_SR_COMIF_Pos (5U)
#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
#define	TIM_SR_COMIF TIM_SR_COMIF_Msk
#define	TIM_SR_TIF_Pos (6U)
#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
#define	TIM_SR_TIF TIM_SR_TIF_Msk
#define	TIM_SR_BIF_Pos (7U)
#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
#define	TIM_SR_BIF TIM_SR_BIF_Msk
#define	TIM_SR_CC1OF_Pos (9U)
#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk
#define	TIM_SR_CC2OF_Pos (10U)
#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk
#define	TIM_SR_CC3OF_Pos (11U)
#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk
#define	TIM_SR_CC4OF_Pos (12U)
#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk
#define	TIM_EGR_UG_Pos (0U)
#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
#define	TIM_EGR_UG TIM_EGR_UG_Msk
#define	TIM_EGR_CC1G_Pos (1U)
#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk
#define	TIM_EGR_CC2G_Pos (2U)
#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk
#define	TIM_EGR_CC3G_Pos (3U)
#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk
#define	TIM_EGR_CC4G_Pos (4U)
#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk
#define	TIM_EGR_COMG_Pos (5U)
#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
#define	TIM_EGR_COMG TIM_EGR_COMG_Msk
#define	TIM_EGR_TG_Pos (6U)
#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
#define	TIM_EGR_TG TIM_EGR_TG_Msk
#define	TIM_EGR_BG_Pos (7U)
#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
#define	TIM_EGR_BG TIM_EGR_BG_Msk
#define	TIM_CCMR1_CC1S_Pos (0U)
#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
#define	TIM_CCMR1_OC1FE_Pos (2U)
#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
#define	TIM_CCMR1_OC1PE_Pos (3U)
#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
#define	TIM_CCMR1_OC1M_Pos (4U)
#define	TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
#define	TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
#define	TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
#define	TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
#define	TIM_CCMR1_OC1CE_Pos (7U)
#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
#define	TIM_CCMR1_CC2S_Pos (8U)
#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
#define	TIM_CCMR1_OC2FE_Pos (10U)
#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
#define	TIM_CCMR1_OC2PE_Pos (11U)
#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
#define	TIM_CCMR1_OC2M_Pos (12U)
#define	TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
#define	TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
#define	TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
#define	TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
#define	TIM_CCMR1_OC2CE_Pos (15U)
#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
#define	TIM_CCMR1_IC1PSC_Pos (2U)
#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
#define	TIM_CCMR1_IC1F_Pos (4U)
#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
#define	TIM_CCMR1_IC2PSC_Pos (10U)
#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
#define	TIM_CCMR1_IC2F_Pos (12U)
#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
#define	TIM_CCMR2_CC3S_Pos (0U)
#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
#define	TIM_CCMR2_OC3FE_Pos (2U)
#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
#define	TIM_CCMR2_OC3PE_Pos (3U)
#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
#define	TIM_CCMR2_OC3M_Pos (4U)
#define	TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
#define	TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
#define	TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
#define	TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
#define	TIM_CCMR2_OC3CE_Pos (7U)
#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
#define	TIM_CCMR2_CC4S_Pos (8U)
#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
#define	TIM_CCMR2_OC4FE_Pos (10U)
#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
#define	TIM_CCMR2_OC4PE_Pos (11U)
#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
#define	TIM_CCMR2_OC4M_Pos (12U)
#define	TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
#define	TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
#define	TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
#define	TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
#define	TIM_CCMR2_OC4CE_Pos (15U)
#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
#define	TIM_CCMR2_IC3PSC_Pos (2U)
#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
#define	TIM_CCMR2_IC3F_Pos (4U)
#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
#define	TIM_CCMR2_IC4PSC_Pos (10U)
#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
#define	TIM_CCMR2_IC4F_Pos (12U)
#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
#define	TIM_CCER_CC1E_Pos (0U)
#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk
#define	TIM_CCER_CC1P_Pos (1U)
#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk
#define	TIM_CCER_CC1NE_Pos (2U)
#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
#define	TIM_CCER_CC1NP_Pos (3U)
#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
#define	TIM_CCER_CC2E_Pos (4U)
#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk
#define	TIM_CCER_CC2P_Pos (5U)
#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk
#define	TIM_CCER_CC2NE_Pos (6U)
#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
#define	TIM_CCER_CC2NP_Pos (7U)
#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
#define	TIM_CCER_CC3E_Pos (8U)
#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk
#define	TIM_CCER_CC3P_Pos (9U)
#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk
#define	TIM_CCER_CC3NE_Pos (10U)
#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
#define	TIM_CCER_CC3NP_Pos (11U)
#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
#define	TIM_CCER_CC4E_Pos (12U)
#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk
#define	TIM_CCER_CC4P_Pos (13U)
#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk
#define	TIM_CCER_CC4NP_Pos (15U)
#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
#define	TIM_CNT_CNT_Pos (0U)
#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
#define	TIM_CNT_CNT TIM_CNT_CNT_Msk
#define	TIM_PSC_PSC_Pos (0U)
#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
#define	TIM_PSC_PSC TIM_PSC_PSC_Msk
#define	TIM_ARR_ARR_Pos (0U)
#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
#define	TIM_ARR_ARR TIM_ARR_ARR_Msk
#define	TIM_RCR_REP_Pos (0U)
#define	TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
#define	TIM_RCR_REP TIM_RCR_REP_Msk
#define	TIM_CCR1_CCR1_Pos (0U)
#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
#define	TIM_CCR2_CCR2_Pos (0U)
#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
#define	TIM_CCR3_CCR3_Pos (0U)
#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
#define	TIM_CCR4_CCR4_Pos (0U)
#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
#define	TIM_BDTR_DTG_Pos (0U)
#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk
#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
#define	TIM_BDTR_LOCK_Pos (8U)
#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
#define	TIM_BDTR_OSSI_Pos (10U)
#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
#define	TIM_BDTR_OSSR_Pos (11U)
#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
#define	TIM_BDTR_BKE_Pos (12U)
#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk
#define	TIM_BDTR_BKP_Pos (13U)
#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk
#define	TIM_BDTR_AOE_Pos (14U)
#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk
#define	TIM_BDTR_MOE_Pos (15U)
#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk
#define	TIM_DCR_DBA_Pos (0U)
#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBA TIM_DCR_DBA_Msk
#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
#define	TIM_DCR_DBL_Pos (8U)
#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
#define	TIM_DCR_DBL TIM_DCR_DBL_Msk
#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
#define	TIM_DMAR_DMAB_Pos (0U)
#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
#define	TIM_OR_TI1_RMP_Pos (0U)
#define	TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
#define	TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
#define	TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
#define	TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
#define	TIM_OR_TI4_RMP_Pos (6U)
#define	TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
#define	TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
#define	TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
#define	TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
#define	TIM_OR_ITR1_RMP_Pos (10U)
#define	TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
#define	TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
#define	TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
#define	TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
#define	USART_SR_PE_Pos (0U)
#define	USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
#define	USART_SR_PE USART_SR_PE_Msk
#define	USART_SR_FE_Pos (1U)
#define	USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
#define	USART_SR_FE USART_SR_FE_Msk
#define	USART_SR_NE_Pos (2U)
#define	USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
#define	USART_SR_NE USART_SR_NE_Msk
#define	USART_SR_ORE_Pos (3U)
#define	USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
#define	USART_SR_ORE USART_SR_ORE_Msk
#define	USART_SR_IDLE_Pos (4U)
#define	USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
#define	USART_SR_IDLE USART_SR_IDLE_Msk
#define	USART_SR_RXNE_Pos (5U)
#define	USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
#define	USART_SR_RXNE USART_SR_RXNE_Msk
#define	USART_SR_TC_Pos (6U)
#define	USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
#define	USART_SR_TC USART_SR_TC_Msk
#define	USART_SR_TXE_Pos (7U)
#define	USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
#define	USART_SR_TXE USART_SR_TXE_Msk
#define	USART_SR_LBD_Pos (8U)
#define	USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
#define	USART_SR_LBD USART_SR_LBD_Msk
#define	USART_SR_CTS_Pos (9U)
#define	USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
#define	USART_SR_CTS USART_SR_CTS_Msk
#define	USART_DR_DR_Pos (0U)
#define	USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
#define	USART_DR_DR USART_DR_DR_Msk
#define	USART_BRR_DIV_Fraction_Pos (0U)
#define	USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
#define	USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
#define	USART_BRR_DIV_Mantissa_Pos (4U)
#define	USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
#define	USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
#define	USART_CR1_SBK_Pos (0U)
#define	USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
#define	USART_CR1_SBK USART_CR1_SBK_Msk
#define	USART_CR1_RWU_Pos (1U)
#define	USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
#define	USART_CR1_RWU USART_CR1_RWU_Msk
#define	USART_CR1_RE_Pos (2U)
#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
#define	USART_CR1_RE USART_CR1_RE_Msk
#define	USART_CR1_TE_Pos (3U)
#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
#define	USART_CR1_TE USART_CR1_TE_Msk
#define	USART_CR1_IDLEIE_Pos (4U)
#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
#define	USART_CR1_RXNEIE_Pos (5U)
#define	USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
#define	USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
#define	USART_CR1_TCIE_Pos (6U)
#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
#define	USART_CR1_TCIE USART_CR1_TCIE_Msk
#define	USART_CR1_TXEIE_Pos (7U)
#define	USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
#define	USART_CR1_TXEIE USART_CR1_TXEIE_Msk
#define	USART_CR1_PEIE_Pos (8U)
#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
#define	USART_CR1_PEIE USART_CR1_PEIE_Msk
#define	USART_CR1_PS_Pos (9U)
#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
#define	USART_CR1_PS USART_CR1_PS_Msk
#define	USART_CR1_PCE_Pos (10U)
#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
#define	USART_CR1_PCE USART_CR1_PCE_Msk
#define	USART_CR1_WAKE_Pos (11U)
#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
#define	USART_CR1_WAKE USART_CR1_WAKE_Msk
#define	USART_CR1_M_Pos (12U)
#define	USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
#define	USART_CR1_M USART_CR1_M_Msk
#define	USART_CR1_UE_Pos (13U)
#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
#define	USART_CR1_UE USART_CR1_UE_Msk
#define	USART_CR1_OVER8_Pos (15U)
#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk
#define	USART_CR2_ADD_Pos (0U)
#define	USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
#define	USART_CR2_ADD USART_CR2_ADD_Msk
#define	USART_CR2_LBDL_Pos (5U)
#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
#define	USART_CR2_LBDL USART_CR2_LBDL_Msk
#define	USART_CR2_LBDIE_Pos (6U)
#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk
#define	USART_CR2_LBCL_Pos (8U)
#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
#define	USART_CR2_LBCL USART_CR2_LBCL_Msk
#define	USART_CR2_CPHA_Pos (9U)
#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
#define	USART_CR2_CPHA USART_CR2_CPHA_Msk
#define	USART_CR2_CPOL_Pos (10U)
#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
#define	USART_CR2_CPOL USART_CR2_CPOL_Msk
#define	USART_CR2_CLKEN_Pos (11U)
#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk
#define	USART_CR2_STOP_Pos (12U)
#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
#define	USART_CR2_STOP USART_CR2_STOP_Msk
#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
#define	USART_CR2_LINEN_Pos (14U)
#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
#define	USART_CR2_LINEN USART_CR2_LINEN_Msk
#define	USART_CR3_EIE_Pos (0U)
#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
#define	USART_CR3_EIE USART_CR3_EIE_Msk
#define	USART_CR3_IREN_Pos (1U)
#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
#define	USART_CR3_IREN USART_CR3_IREN_Msk
#define	USART_CR3_IRLP_Pos (2U)
#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
#define	USART_CR3_IRLP USART_CR3_IRLP_Msk
#define	USART_CR3_HDSEL_Pos (3U)
#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk
#define	USART_CR3_NACK_Pos (4U)
#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
#define	USART_CR3_NACK USART_CR3_NACK_Msk
#define	USART_CR3_SCEN_Pos (5U)
#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
#define	USART_CR3_SCEN USART_CR3_SCEN_Msk
#define	USART_CR3_DMAR_Pos (6U)
#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
#define	USART_CR3_DMAR USART_CR3_DMAR_Msk
#define	USART_CR3_DMAT_Pos (7U)
#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
#define	USART_CR3_DMAT USART_CR3_DMAT_Msk
#define	USART_CR3_RTSE_Pos (8U)
#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
#define	USART_CR3_RTSE USART_CR3_RTSE_Msk
#define	USART_CR3_CTSE_Pos (9U)
#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
#define	USART_CR3_CTSE USART_CR3_CTSE_Msk
#define	USART_CR3_CTSIE_Pos (10U)
#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk
#define	USART_CR3_ONEBIT_Pos (11U)
#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
#define	USART_GTPR_PSC_Pos (0U)
#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC USART_GTPR_PSC_Msk
#define	USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
#define	USART_GTPR_GT_Pos (8U)
#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
#define	USART_GTPR_GT USART_GTPR_GT_Msk
#define	WWDG_CR_T_Pos (0U)
#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
#define	WWDG_CR_T WWDG_CR_T_Msk
#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
#define	WWDG_CR_T0 WWDG_CR_T_0
#define	WWDG_CR_T1 WWDG_CR_T_1
#define	WWDG_CR_T2 WWDG_CR_T_2
#define	WWDG_CR_T3 WWDG_CR_T_3
#define	WWDG_CR_T4 WWDG_CR_T_4
#define	WWDG_CR_T5 WWDG_CR_T_5
#define	WWDG_CR_T6 WWDG_CR_T_6
#define	WWDG_CR_WDGA_Pos (7U)
#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk
#define	WWDG_CFR_W_Pos (0U)
#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W WWDG_CFR_W_Msk
#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
#define	WWDG_CFR_W0 WWDG_CFR_W_0
#define	WWDG_CFR_W1 WWDG_CFR_W_1
#define	WWDG_CFR_W2 WWDG_CFR_W_2
#define	WWDG_CFR_W3 WWDG_CFR_W_3
#define	WWDG_CFR_W4 WWDG_CFR_W_4
#define	WWDG_CFR_W5 WWDG_CFR_W_5
#define	WWDG_CFR_W6 WWDG_CFR_W_6
#define	WWDG_CFR_WDGTB_Pos (7U)
#define	WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
#define	WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
#define	WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
#define	WWDG_CFR_EWI_Pos (9U)
#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk
#define	WWDG_SR_EWIF_Pos (0U)
#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk
#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define	DBGMCU_IDCODE_REV_ID_Pos (16U)
#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define	DBGMCU_CR_DBG_STOP_Pos (1U)
#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define	DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define	DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
#define	DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define	DBGMCU_CR_TRACE_MODE_Pos (6U)
#define	DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
#define	DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define	DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
#define	DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
#define	DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
#define	DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
#define	DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
#define	DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
#define	DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
#define	DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
#define	DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
#define	DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
#define	DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
#define	DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
#define	ETH_MACCR_CSTF_Pos (25U)
#define	ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos)
#define	ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
#define	ETH_MACCR_WD_Pos (23U)
#define	ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
#define	ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
#define	ETH_MACCR_JD_Pos (22U)
#define	ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
#define	ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
#define	ETH_MACCR_IFG_Pos (17U)
#define	ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
#define	ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
#define	ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
#define	ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
#define	ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
#define	ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
#define	ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
#define	ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
#define	ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
#define	ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
#define	ETH_MACCR_CSD_Pos (16U)
#define	ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
#define	ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
#define	ETH_MACCR_FES_Pos (14U)
#define	ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
#define	ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
#define	ETH_MACCR_ROD_Pos (13U)
#define	ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
#define	ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
#define	ETH_MACCR_LM_Pos (12U)
#define	ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
#define	ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
#define	ETH_MACCR_DM_Pos (11U)
#define	ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
#define	ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
#define	ETH_MACCR_IPCO_Pos (10U)
#define	ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
#define	ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
#define	ETH_MACCR_RD_Pos (9U)
#define	ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
#define	ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
#define	ETH_MACCR_APCS_Pos (7U)
#define	ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
#define	ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
#define	ETH_MACCR_BL_Pos (5U)
#define	ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
#define	ETH_MACCR_BL
#define	ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
#define	ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
#define	ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
#define	ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
#define	ETH_MACCR_DC_Pos (4U)
#define	ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
#define	ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
#define	ETH_MACCR_TE_Pos (3U)
#define	ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
#define	ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
#define	ETH_MACCR_RE_Pos (2U)
#define	ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
#define	ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
#define	ETH_MACFFR_RA_Pos (31U)
#define	ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
#define	ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
#define	ETH_MACFFR_HPF_Pos (10U)
#define	ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
#define	ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
#define	ETH_MACFFR_SAF_Pos (9U)
#define	ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
#define	ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
#define	ETH_MACFFR_SAIF_Pos (8U)
#define	ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
#define	ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
#define	ETH_MACFFR_PCF_Pos (6U)
#define	ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
#define	ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
#define	ETH_MACFFR_PCF_BlockAll_Pos (6U)
#define	ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
#define	ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
#define	ETH_MACFFR_PCF_ForwardAll_Pos (7U)
#define	ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
#define	ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
#define	ETH_MACFFR_BFD_Pos (5U)
#define	ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
#define	ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
#define	ETH_MACFFR_PAM_Pos (4U)
#define	ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
#define	ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
#define	ETH_MACFFR_DAIF_Pos (3U)
#define	ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
#define	ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
#define	ETH_MACFFR_HM_Pos (2U)
#define	ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
#define	ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
#define	ETH_MACFFR_HU_Pos (1U)
#define	ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
#define	ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
#define	ETH_MACFFR_PM_Pos (0U)
#define	ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
#define	ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
#define	ETH_MACHTHR_HTH_Pos (0U)
#define	ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
#define	ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
#define	ETH_MACHTLR_HTL_Pos (0U)
#define	ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
#define	ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
#define	ETH_MACMIIAR_PA_Pos (11U)
#define	ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
#define	ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
#define	ETH_MACMIIAR_MR_Pos (6U)
#define	ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
#define	ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
#define	ETH_MACMIIAR_CR_Pos (2U)
#define	ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
#define	ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
#define	ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define	ETH_MACMIIAR_CR_Div62_Pos (2U)
#define	ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
#define	ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define	ETH_MACMIIAR_CR_Div16_Pos (3U)
#define	ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
#define	ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define	ETH_MACMIIAR_CR_Div26_Pos (2U)
#define	ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
#define	ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define	ETH_MACMIIAR_CR_Div102_Pos (4U)
#define	ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
#define	ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define	ETH_MACMIIAR_MW_Pos (1U)
#define	ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
#define	ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
#define	ETH_MACMIIAR_MB_Pos (0U)
#define	ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
#define	ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
#define	ETH_MACMIIDR_MD_Pos (0U)
#define	ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
#define	ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
#define	ETH_MACFCR_PT_Pos (16U)
#define	ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
#define	ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
#define	ETH_MACFCR_ZQPD_Pos (7U)
#define	ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
#define	ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
#define	ETH_MACFCR_PLT_Pos (4U)
#define	ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
#define	ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
#define	ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
#define	ETH_MACFCR_PLT_Minus28_Pos (4U)
#define	ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
#define	ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
#define	ETH_MACFCR_PLT_Minus144_Pos (5U)
#define	ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
#define	ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
#define	ETH_MACFCR_PLT_Minus256_Pos (4U)
#define	ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
#define	ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
#define	ETH_MACFCR_UPFD_Pos (3U)
#define	ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
#define	ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
#define	ETH_MACFCR_RFCE_Pos (2U)
#define	ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
#define	ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
#define	ETH_MACFCR_TFCE_Pos (1U)
#define	ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
#define	ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
#define	ETH_MACFCR_FCBBPA_Pos (0U)
#define	ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
#define	ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
#define	ETH_MACVLANTR_VLANTC_Pos (16U)
#define	ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
#define	ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
#define	ETH_MACVLANTR_VLANTI_Pos (0U)
#define	ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
#define	ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
#define	ETH_MACRWUFFR_D_Pos (0U)
#define	ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
#define	ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
#define	ETH_MACPMTCSR_WFFRPR_Pos (31U)
#define	ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
#define	ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
#define	ETH_MACPMTCSR_GU_Pos (9U)
#define	ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
#define	ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
#define	ETH_MACPMTCSR_WFR_Pos (6U)
#define	ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
#define	ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
#define	ETH_MACPMTCSR_MPR_Pos (5U)
#define	ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
#define	ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
#define	ETH_MACPMTCSR_WFE_Pos (2U)
#define	ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
#define	ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
#define	ETH_MACPMTCSR_MPE_Pos (1U)
#define	ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
#define	ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
#define	ETH_MACPMTCSR_PD_Pos (0U)
#define	ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
#define	ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
#define	ETH_MACDBGR_TFF_Pos (25U)
#define	ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
#define	ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
#define	ETH_MACDBGR_TFNE_Pos (24U)
#define	ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
#define	ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
#define	ETH_MACDBGR_TFWA_Pos (22U)
#define	ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
#define	ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
#define	ETH_MACDBGR_TFRS_Pos (20U)
#define	ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
#define	ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
#define	ETH_MACDBGR_TFRS_WRITING_Pos (20U)
#define	ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
#define	ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
#define	ETH_MACDBGR_TFRS_WAITING_Pos (21U)
#define	ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
#define	ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
#define	ETH_MACDBGR_TFRS_READ_Pos (20U)
#define	ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
#define	ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
#define	ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
#define	ETH_MACDBGR_MTP_Pos (19U)
#define	ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
#define	ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
#define	ETH_MACDBGR_MTFCS_Pos (17U)
#define	ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
#define	ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
#define	ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
#define	ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
#define	ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
#define	ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
#define	ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
#define	ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
#define	ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
#define	ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
#define	ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
#define	ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
#define	ETH_MACDBGR_MMTEA_Pos (16U)
#define	ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
#define	ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
#define	ETH_MACDBGR_RFFL_Pos (8U)
#define	ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
#define	ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
#define	ETH_MACDBGR_RFFL_FULL_Pos (8U)
#define	ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
#define	ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
#define	ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
#define	ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
#define	ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
#define	ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
#define	ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
#define	ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
#define	ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
#define	ETH_MACDBGR_RFRCS_Pos (5U)
#define	ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
#define	ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
#define	ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
#define	ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
#define	ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
#define	ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
#define	ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
#define	ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
#define	ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
#define	ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
#define	ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
#define	ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
#define	ETH_MACDBGR_RFWRA_Pos (4U)
#define	ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
#define	ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
#define	ETH_MACDBGR_MSFRWCS_Pos (1U)
#define	ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
#define	ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
#define	ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
#define	ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
#define	ETH_MACDBGR_MMRPEA_Pos (0U)
#define	ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
#define	ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
#define	ETH_MACSR_TSTS_Pos (9U)
#define	ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
#define	ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
#define	ETH_MACSR_MMCTS_Pos (6U)
#define	ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
#define	ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
#define	ETH_MACSR_MMMCRS_Pos (5U)
#define	ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
#define	ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
#define	ETH_MACSR_MMCS_Pos (4U)
#define	ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
#define	ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
#define	ETH_MACSR_PMTS_Pos (3U)
#define	ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
#define	ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
#define	ETH_MACIMR_TSTIM_Pos (9U)
#define	ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
#define	ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
#define	ETH_MACIMR_PMTIM_Pos (3U)
#define	ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
#define	ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
#define	ETH_MACA0HR_MACA0H_Pos (0U)
#define	ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
#define	ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
#define	ETH_MACA0LR_MACA0L_Pos (0U)
#define	ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
#define	ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
#define	ETH_MACA1HR_AE_Pos (31U)
#define	ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
#define	ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
#define	ETH_MACA1HR_SA_Pos (30U)
#define	ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
#define	ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
#define	ETH_MACA1HR_MBC_Pos (24U)
#define	ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
#define	ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define	ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define	ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define	ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define	ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define	ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define	ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
#define	ETH_MACA1HR_MACA1H_Pos (0U)
#define	ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
#define	ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
#define	ETH_MACA1LR_MACA1L_Pos (0U)
#define	ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
#define	ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
#define	ETH_MACA2HR_AE_Pos (31U)
#define	ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
#define	ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
#define	ETH_MACA2HR_SA_Pos (30U)
#define	ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
#define	ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
#define	ETH_MACA2HR_MBC_Pos (24U)
#define	ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
#define	ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
#define	ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define	ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define	ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define	ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define	ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define	ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
#define	ETH_MACA2HR_MACA2H_Pos (0U)
#define	ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
#define	ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
#define	ETH_MACA2LR_MACA2L_Pos (0U)
#define	ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
#define	ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
#define	ETH_MACA3HR_AE_Pos (31U)
#define	ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
#define	ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
#define	ETH_MACA3HR_SA_Pos (30U)
#define	ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
#define	ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
#define	ETH_MACA3HR_MBC_Pos (24U)
#define	ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
#define	ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
#define	ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define	ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define	ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define	ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define	ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define	ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
#define	ETH_MACA3HR_MACA3H_Pos (0U)
#define	ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
#define	ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
#define	ETH_MACA3LR_MACA3L_Pos (0U)
#define	ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
#define	ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
#define	ETH_MMCCR_MCFHP_Pos (5U)
#define	ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
#define	ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
#define	ETH_MMCCR_MCP_Pos (4U)
#define	ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
#define	ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
#define	ETH_MMCCR_MCF_Pos (3U)
#define	ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
#define	ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
#define	ETH_MMCCR_ROR_Pos (2U)
#define	ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
#define	ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
#define	ETH_MMCCR_CSR_Pos (1U)
#define	ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
#define	ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
#define	ETH_MMCCR_CR_Pos (0U)
#define	ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
#define	ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
#define	ETH_MMCRIR_RGUFS_Pos (17U)
#define	ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
#define	ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
#define	ETH_MMCRIR_RFAES_Pos (6U)
#define	ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
#define	ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
#define	ETH_MMCRIR_RFCES_Pos (5U)
#define	ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
#define	ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
#define	ETH_MMCTIR_TGFS_Pos (21U)
#define	ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
#define	ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
#define	ETH_MMCTIR_TGFMSCS_Pos (15U)
#define	ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
#define	ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
#define	ETH_MMCTIR_TGFSCS_Pos (14U)
#define	ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
#define	ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
#define	ETH_MMCRIMR_RGUFM_Pos (17U)
#define	ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
#define	ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define	ETH_MMCRIMR_RFAEM_Pos (6U)
#define	ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
#define	ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define	ETH_MMCRIMR_RFCEM_Pos (5U)
#define	ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
#define	ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
#define	ETH_MMCTIMR_TGFM_Pos (21U)
#define	ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
#define	ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define	ETH_MMCTIMR_TGFMSCM_Pos (15U)
#define	ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
#define	ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define	ETH_MMCTIMR_TGFSCM_Pos (14U)
#define	ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
#define	ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
#define	ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
#define	ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
#define	ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
#define	ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
#define	ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
#define	ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
#define	ETH_MMCTGFCR_TGFC_Pos (0U)
#define	ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
#define	ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
#define	ETH_MMCRFCECR_RFCEC_Pos (0U)
#define	ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
#define	ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
#define	ETH_MMCRFAECR_RFAEC_Pos (0U)
#define	ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
#define	ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
#define	ETH_MMCRGUFCR_RGUFC_Pos (0U)
#define	ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
#define	ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
#define	ETH_PTPTSCR_TSPFFMAE_Pos (18U)
#define	ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
#define	ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
#define	ETH_PTPTSCR_TSCNT_Pos (16U)
#define	ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
#define	ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
#define	ETH_PTPTSCR_TSSMRME_Pos (15U)
#define	ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
#define	ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
#define	ETH_PTPTSCR_TSSEME_Pos (14U)
#define	ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
#define	ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
#define	ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
#define	ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
#define	ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
#define	ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
#define	ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
#define	ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
#define	ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
#define	ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
#define	ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
#define	ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
#define	ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
#define	ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
#define	ETH_PTPTSCR_TSSSR_Pos (9U)
#define	ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
#define	ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
#define	ETH_PTPTSCR_TSSARFE_Pos (8U)
#define	ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
#define	ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
#define	ETH_PTPTSCR_TSARU_Pos (5U)
#define	ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
#define	ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
#define	ETH_PTPTSCR_TSITE_Pos (4U)
#define	ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
#define	ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
#define	ETH_PTPTSCR_TSSTU_Pos (3U)
#define	ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
#define	ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
#define	ETH_PTPTSCR_TSSTI_Pos (2U)
#define	ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
#define	ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
#define	ETH_PTPTSCR_TSFCU_Pos (1U)
#define	ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
#define	ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
#define	ETH_PTPTSCR_TSE_Pos (0U)
#define	ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
#define	ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
#define	ETH_PTPSSIR_STSSI_Pos (0U)
#define	ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
#define	ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
#define	ETH_PTPTSHR_STS_Pos (0U)
#define	ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
#define	ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
#define	ETH_PTPTSLR_STPNS_Pos (31U)
#define	ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
#define	ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
#define	ETH_PTPTSLR_STSS_Pos (0U)
#define	ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
#define	ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
#define	ETH_PTPTSHUR_TSUS_Pos (0U)
#define	ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
#define	ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
#define	ETH_PTPTSLUR_TSUPNS_Pos (31U)
#define	ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
#define	ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
#define	ETH_PTPTSLUR_TSUSS_Pos (0U)
#define	ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
#define	ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
#define	ETH_PTPTSAR_TSA_Pos (0U)
#define	ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
#define	ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
#define	ETH_PTPTTHR_TTSH_Pos (0U)
#define	ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
#define	ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
#define	ETH_PTPTTLR_TTSL_Pos (0U)
#define	ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
#define	ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
#define	ETH_PTPTSSR_TSTTR_Pos (5U)
#define	ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
#define	ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
#define	ETH_PTPTSSR_TSSO_Pos (4U)
#define	ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
#define	ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
#define	ETH_DMABMR_MB_Pos (26U)
#define	ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
#define	ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
#define	ETH_DMABMR_AAB_Pos (25U)
#define	ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
#define	ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
#define	ETH_DMABMR_FPM_Pos (24U)
#define	ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
#define	ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
#define	ETH_DMABMR_USP_Pos (23U)
#define	ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
#define	ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
#define	ETH_DMABMR_RDP_Pos (17U)
#define	ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
#define	ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
#define	ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define	ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define	ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define	ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define	ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define	ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define	ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define	ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define	ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define	ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define	ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define	ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define	ETH_DMABMR_FB_Pos (16U)
#define	ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
#define	ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
#define	ETH_DMABMR_RTPR_Pos (14U)
#define	ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
#define	ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
#define	ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
#define	ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
#define	ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
#define	ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
#define	ETH_DMABMR_PBL_Pos (8U)
#define	ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
#define	ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
#define	ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define	ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define	ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define	ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define	ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define	ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define	ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define	ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define	ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define	ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define	ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define	ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define	ETH_DMABMR_EDE_Pos (7U)
#define	ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
#define	ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
#define	ETH_DMABMR_DSL_Pos (2U)
#define	ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
#define	ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
#define	ETH_DMABMR_DA_Pos (1U)
#define	ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
#define	ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
#define	ETH_DMABMR_SR_Pos (0U)
#define	ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
#define	ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
#define	ETH_DMATPDR_TPD_Pos (0U)
#define	ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
#define	ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
#define	ETH_DMARPDR_RPD_Pos (0U)
#define	ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
#define	ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
#define	ETH_DMARDLAR_SRL_Pos (0U)
#define	ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
#define	ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
#define	ETH_DMATDLAR_STL_Pos (0U)
#define	ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
#define	ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
#define	ETH_DMASR_TSTS_Pos (29U)
#define	ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
#define	ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
#define	ETH_DMASR_PMTS_Pos (28U)
#define	ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
#define	ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
#define	ETH_DMASR_MMCS_Pos (27U)
#define	ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
#define	ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
#define	ETH_DMASR_EBS_Pos (23U)
#define	ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
#define	ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
#define	ETH_DMASR_EBS_DescAccess_Pos (25U)
#define	ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
#define	ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
#define	ETH_DMASR_EBS_ReadTransf_Pos (24U)
#define	ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
#define	ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
#define	ETH_DMASR_EBS_DataTransfTx_Pos (23U)
#define	ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
#define	ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
#define	ETH_DMASR_TPS_Pos (20U)
#define	ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
#define	ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
#define	ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
#define	ETH_DMASR_TPS_Fetching_Pos (20U)
#define	ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
#define	ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
#define	ETH_DMASR_TPS_Waiting_Pos (21U)
#define	ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
#define	ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
#define	ETH_DMASR_TPS_Reading_Pos (20U)
#define	ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
#define	ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
#define	ETH_DMASR_TPS_Suspended_Pos (21U)
#define	ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
#define	ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
#define	ETH_DMASR_TPS_Closing_Pos (20U)
#define	ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
#define	ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
#define	ETH_DMASR_RPS_Pos (17U)
#define	ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
#define	ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
#define	ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
#define	ETH_DMASR_RPS_Fetching_Pos (17U)
#define	ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
#define	ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
#define	ETH_DMASR_RPS_Waiting_Pos (17U)
#define	ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
#define	ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
#define	ETH_DMASR_RPS_Suspended_Pos (19U)
#define	ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
#define	ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
#define	ETH_DMASR_RPS_Closing_Pos (17U)
#define	ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
#define	ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
#define	ETH_DMASR_RPS_Queuing_Pos (17U)
#define	ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
#define	ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
#define	ETH_DMASR_NIS_Pos (16U)
#define	ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
#define	ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
#define	ETH_DMASR_AIS_Pos (15U)
#define	ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
#define	ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
#define	ETH_DMASR_ERS_Pos (14U)
#define	ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
#define	ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
#define	ETH_DMASR_FBES_Pos (13U)
#define	ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
#define	ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
#define	ETH_DMASR_ETS_Pos (10U)
#define	ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
#define	ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
#define	ETH_DMASR_RWTS_Pos (9U)
#define	ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
#define	ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
#define	ETH_DMASR_RPSS_Pos (8U)
#define	ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
#define	ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
#define	ETH_DMASR_RBUS_Pos (7U)
#define	ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
#define	ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
#define	ETH_DMASR_RS_Pos (6U)
#define	ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
#define	ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
#define	ETH_DMASR_TUS_Pos (5U)
#define	ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
#define	ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
#define	ETH_DMASR_ROS_Pos (4U)
#define	ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
#define	ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
#define	ETH_DMASR_TJTS_Pos (3U)
#define	ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
#define	ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
#define	ETH_DMASR_TBUS_Pos (2U)
#define	ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
#define	ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
#define	ETH_DMASR_TPSS_Pos (1U)
#define	ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
#define	ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
#define	ETH_DMASR_TS_Pos (0U)
#define	ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
#define	ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
#define	ETH_DMAOMR_DTCEFD_Pos (26U)
#define	ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
#define	ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
#define	ETH_DMAOMR_RSF_Pos (25U)
#define	ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
#define	ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
#define	ETH_DMAOMR_DFRF_Pos (24U)
#define	ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
#define	ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
#define	ETH_DMAOMR_TSF_Pos (21U)
#define	ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
#define	ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
#define	ETH_DMAOMR_FTF_Pos (20U)
#define	ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
#define	ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
#define	ETH_DMAOMR_TTC_Pos (14U)
#define	ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
#define	ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
#define	ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define	ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define	ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define	ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define	ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define	ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define	ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define	ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define	ETH_DMAOMR_ST_Pos (13U)
#define	ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
#define	ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
#define	ETH_DMAOMR_FEF_Pos (7U)
#define	ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
#define	ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
#define	ETH_DMAOMR_FUGF_Pos (6U)
#define	ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
#define	ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
#define	ETH_DMAOMR_RTC_Pos (3U)
#define	ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
#define	ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
#define	ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define	ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define	ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define	ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define	ETH_DMAOMR_OSF_Pos (2U)
#define	ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
#define	ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
#define	ETH_DMAOMR_SR_Pos (1U)
#define	ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
#define	ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
#define	ETH_DMAIER_NISE_Pos (16U)
#define	ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
#define	ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
#define	ETH_DMAIER_AISE_Pos (15U)
#define	ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
#define	ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
#define	ETH_DMAIER_ERIE_Pos (14U)
#define	ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
#define	ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
#define	ETH_DMAIER_FBEIE_Pos (13U)
#define	ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
#define	ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
#define	ETH_DMAIER_ETIE_Pos (10U)
#define	ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
#define	ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
#define	ETH_DMAIER_RWTIE_Pos (9U)
#define	ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
#define	ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
#define	ETH_DMAIER_RPSIE_Pos (8U)
#define	ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
#define	ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
#define	ETH_DMAIER_RBUIE_Pos (7U)
#define	ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
#define	ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
#define	ETH_DMAIER_RIE_Pos (6U)
#define	ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
#define	ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
#define	ETH_DMAIER_TUIE_Pos (5U)
#define	ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
#define	ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
#define	ETH_DMAIER_ROIE_Pos (4U)
#define	ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
#define	ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
#define	ETH_DMAIER_TJTIE_Pos (3U)
#define	ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
#define	ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
#define	ETH_DMAIER_TBUIE_Pos (2U)
#define	ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
#define	ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
#define	ETH_DMAIER_TPSIE_Pos (1U)
#define	ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
#define	ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
#define	ETH_DMAIER_TIE_Pos (0U)
#define	ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
#define	ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
#define	ETH_DMAMFBOCR_OFOC_Pos (28U)
#define	ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
#define	ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
#define	ETH_DMAMFBOCR_MFA_Pos (17U)
#define	ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
#define	ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
#define	ETH_DMAMFBOCR_OMFC_Pos (16U)
#define	ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
#define	ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
#define	ETH_DMAMFBOCR_MFC_Pos (0U)
#define	ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
#define	ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
#define	ETH_DMACHTDR_HTDAP_Pos (0U)
#define	ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
#define	ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
#define	ETH_DMACHRDR_HRDAP_Pos (0U)
#define	ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
#define	ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
#define	ETH_DMACHTBAR_HTBAP_Pos (0U)
#define	ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
#define	ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
#define	ETH_DMACHRBAR_HRBAP_Pos (0U)
#define	ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
#define	ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
#define	USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
#define	USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
#define	USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
#define	USB_OTG_GOTGCTL_SRQ_Pos (1U)
#define	USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
#define	USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
#define	USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
#define	USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
#define	USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
#define	USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
#define	USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
#define	USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
#define	USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
#define	USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
#define	USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
#define	USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
#define	USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
#define	USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
#define	USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
#define	USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
#define	USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
#define	USB_OTG_GOTGCTL_DBCT_Pos (17U)
#define	USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
#define	USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
#define	USB_OTG_GOTGCTL_ASVLD_Pos (18U)
#define	USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
#define	USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
#define	USB_OTG_GOTGCTL_BSVLD_Pos (19U)
#define	USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
#define	USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
#define	USB_OTG_HCFG_FSLSPCS_Pos (0U)
#define	USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
#define	USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
#define	USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
#define	USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
#define	USB_OTG_HCFG_FSLSS_Pos (2U)
#define	USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
#define	USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
#define	USB_OTG_DCFG_DSPD_Pos (0U)
#define	USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
#define	USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
#define	USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
#define	USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
#define	USB_OTG_DCFG_NZLSOHSK_Pos (2U)
#define	USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
#define	USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
#define	USB_OTG_DCFG_DAD_Pos (4U)
#define	USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
#define	USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
#define	USB_OTG_DCFG_PFIVL_Pos (11U)
#define	USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
#define	USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
#define	USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
#define	USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
#define	USB_OTG_DCFG_XCVRDLY_Pos (14U)
#define	USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
#define	USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
#define	USB_OTG_DCFG_ERRATIM_Pos (15U)
#define	USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
#define	USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
#define	USB_OTG_DCFG_PERSCHIVL_Pos (24U)
#define	USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
#define	USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
#define	USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
#define	USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
#define	USB_OTG_PCGCR_STPPCLK_Pos (0U)
#define	USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
#define	USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
#define	USB_OTG_PCGCR_GATEHCLK_Pos (1U)
#define	USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
#define	USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
#define	USB_OTG_PCGCR_PHYSUSP_Pos (4U)
#define	USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
#define	USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
#define	USB_OTG_GOTGINT_SEDET_Pos (2U)
#define	USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
#define	USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
#define	USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
#define	USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
#define	USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
#define	USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
#define	USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
#define	USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
#define	USB_OTG_GOTGINT_HNGDET_Pos (17U)
#define	USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
#define	USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
#define	USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
#define	USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
#define	USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
#define	USB_OTG_GOTGINT_DBCDNE_Pos (19U)
#define	USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
#define	USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
#define	USB_OTG_DCTL_RWUSIG_Pos (0U)
#define	USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
#define	USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
#define	USB_OTG_DCTL_SDIS_Pos (1U)
#define	USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
#define	USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
#define	USB_OTG_DCTL_GINSTS_Pos (2U)
#define	USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
#define	USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
#define	USB_OTG_DCTL_GONSTS_Pos (3U)
#define	USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
#define	USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
#define	USB_OTG_DCTL_TCTL_Pos (4U)
#define	USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
#define	USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
#define	USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
#define	USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
#define	USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
#define	USB_OTG_DCTL_SGINAK_Pos (7U)
#define	USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
#define	USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
#define	USB_OTG_DCTL_CGINAK_Pos (8U)
#define	USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
#define	USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
#define	USB_OTG_DCTL_SGONAK_Pos (9U)
#define	USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
#define	USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
#define	USB_OTG_DCTL_CGONAK_Pos (10U)
#define	USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
#define	USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
#define	USB_OTG_DCTL_POPRGDNE_Pos (11U)
#define	USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
#define	USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
#define	USB_OTG_HFIR_FRIVL_Pos (0U)
#define	USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
#define	USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
#define	USB_OTG_HFNUM_FRNUM_Pos (0U)
#define	USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
#define	USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
#define	USB_OTG_HFNUM_FTREM_Pos (16U)
#define	USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
#define	USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
#define	USB_OTG_DSTS_SUSPSTS_Pos (0U)
#define	USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
#define	USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
#define	USB_OTG_DSTS_ENUMSPD_Pos (1U)
#define	USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
#define	USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
#define	USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
#define	USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
#define	USB_OTG_DSTS_EERR_Pos (3U)
#define	USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
#define	USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
#define	USB_OTG_DSTS_FNSOF_Pos (8U)
#define	USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
#define	USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
#define	USB_OTG_GAHBCFG_GINT_Pos (0U)
#define	USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
#define	USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
#define	USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define	USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
#define	USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
#define	USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define	USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
#define	USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
#define	USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
#define	USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
#define	USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
#define	USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
#define	USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
#define	USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
#define	USB_OTG_GUSBCFG_TOCAL_Pos (0U)
#define	USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
#define	USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
#define	USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
#define	USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
#define	USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
#define	USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define	USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
#define	USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
#define	USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
#define	USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
#define	USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
#define	USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
#define	USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
#define	USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
#define	USB_OTG_GUSBCFG_TRDT_Pos (10U)
#define	USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
#define	USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
#define	USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
#define	USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
#define	USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
#define	USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
#define	USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
#define	USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
#define	USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
#define	USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
#define	USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
#define	USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
#define	USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
#define	USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
#define	USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
#define	USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
#define	USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
#define	USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
#define	USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
#define	USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
#define	USB_OTG_GUSBCFG_TSDPS_Pos (22U)
#define	USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
#define	USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
#define	USB_OTG_GUSBCFG_PCCI_Pos (23U)
#define	USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
#define	USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
#define	USB_OTG_GUSBCFG_PTCI_Pos (24U)
#define	USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
#define	USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
#define	USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
#define	USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
#define	USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
#define	USB_OTG_GUSBCFG_FHMOD_Pos (29U)
#define	USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
#define	USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
#define	USB_OTG_GUSBCFG_FDMOD_Pos (30U)
#define	USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
#define	USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
#define	USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
#define	USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
#define	USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
#define	USB_OTG_GRSTCTL_CSRST_Pos (0U)
#define	USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
#define	USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
#define	USB_OTG_GRSTCTL_HSRST_Pos (1U)
#define	USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
#define	USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
#define	USB_OTG_GRSTCTL_FCRST_Pos (2U)
#define	USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
#define	USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
#define	USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
#define	USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
#define	USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
#define	USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
#define	USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
#define	USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
#define	USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
#define	USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
#define	USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
#define	USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
#define	USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
#define	USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
#define	USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
#define	USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
#define	USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
#define	USB_OTG_DIEPMSK_XFRCM_Pos (0U)
#define	USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
#define	USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
#define	USB_OTG_DIEPMSK_EPDM_Pos (1U)
#define	USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
#define	USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
#define	USB_OTG_DIEPMSK_TOM_Pos (3U)
#define	USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
#define	USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
#define	USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
#define	USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
#define	USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
#define	USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
#define	USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
#define	USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
#define	USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
#define	USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
#define	USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
#define	USB_OTG_DIEPMSK_TXFURM_Pos (8U)
#define	USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
#define	USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
#define	USB_OTG_DIEPMSK_NAKM_Pos (13U)
#define	USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
#define	USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
#define	USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
#define	USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
#define	USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
#define	USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
#define	USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
#define	USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
#define	USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
#define	USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
#define	USB_OTG_HAINT_HAINT_Pos (0U)
#define	USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
#define	USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
#define	USB_OTG_DOEPMSK_XFRCM_Pos (0U)
#define	USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
#define	USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
#define	USB_OTG_DOEPMSK_EPDM_Pos (1U)
#define	USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
#define	USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
#define	USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
#define	USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
#define	USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
#define	USB_OTG_DOEPMSK_STUPM_Pos (3U)
#define	USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
#define	USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
#define	USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
#define	USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
#define	USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
#define	USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
#define	USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
#define	USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
#define	USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
#define	USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
#define	USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
#define	USB_OTG_DOEPMSK_OPEM_Pos (8U)
#define	USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
#define	USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
#define	USB_OTG_DOEPMSK_BOIM_Pos (9U)
#define	USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
#define	USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
#define	USB_OTG_DOEPMSK_BERRM_Pos (12U)
#define	USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
#define	USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
#define	USB_OTG_DOEPMSK_NAKM_Pos (13U)
#define	USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
#define	USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
#define	USB_OTG_DOEPMSK_NYETM_Pos (14U)
#define	USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
#define	USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
#define	USB_OTG_GINTSTS_CMOD_Pos (0U)
#define	USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
#define	USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
#define	USB_OTG_GINTSTS_MMIS_Pos (1U)
#define	USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
#define	USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
#define	USB_OTG_GINTSTS_OTGINT_Pos (2U)
#define	USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
#define	USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
#define	USB_OTG_GINTSTS_SOF_Pos (3U)
#define	USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
#define	USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
#define	USB_OTG_GINTSTS_RXFLVL_Pos (4U)
#define	USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
#define	USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
#define	USB_OTG_GINTSTS_NPTXFE_Pos (5U)
#define	USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
#define	USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
#define	USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
#define	USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
#define	USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
#define	USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
#define	USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
#define	USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
#define	USB_OTG_GINTSTS_ESUSP_Pos (10U)
#define	USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
#define	USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
#define	USB_OTG_GINTSTS_USBSUSP_Pos (11U)
#define	USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
#define	USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
#define	USB_OTG_GINTSTS_USBRST_Pos (12U)
#define	USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
#define	USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
#define	USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
#define	USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
#define	USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
#define	USB_OTG_GINTSTS_ISOODRP_Pos (14U)
#define	USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
#define	USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
#define	USB_OTG_GINTSTS_EOPF_Pos (15U)
#define	USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
#define	USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
#define	USB_OTG_GINTSTS_IEPINT_Pos (18U)
#define	USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
#define	USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
#define	USB_OTG_GINTSTS_OEPINT_Pos (19U)
#define	USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
#define	USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
#define	USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
#define	USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
#define	USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
#define	USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
#define	USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
#define	USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
#define	USB_OTG_GINTSTS_HPRTINT_Pos (24U)
#define	USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
#define	USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
#define	USB_OTG_GINTSTS_HCINT_Pos (25U)
#define	USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
#define	USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
#define	USB_OTG_GINTSTS_PTXFE_Pos (26U)
#define	USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
#define	USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
#define	USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
#define	USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
#define	USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
#define	USB_OTG_GINTSTS_DISCINT_Pos (29U)
#define	USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
#define	USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
#define	USB_OTG_GINTSTS_SRQINT_Pos (30U)
#define	USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
#define	USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
#define	USB_OTG_GINTSTS_WKUINT_Pos (31U)
#define	USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
#define	USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
#define	USB_OTG_GINTMSK_MMISM_Pos (1U)
#define	USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
#define	USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
#define	USB_OTG_GINTMSK_OTGINT_Pos (2U)
#define	USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
#define	USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
#define	USB_OTG_GINTMSK_SOFM_Pos (3U)
#define	USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
#define	USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
#define	USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
#define	USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
#define	USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
#define	USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
#define	USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
#define	USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
#define	USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
#define	USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
#define	USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
#define	USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
#define	USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
#define	USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
#define	USB_OTG_GINTMSK_ESUSPM_Pos (10U)
#define	USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
#define	USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
#define	USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
#define	USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
#define	USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
#define	USB_OTG_GINTMSK_USBRST_Pos (12U)
#define	USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
#define	USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
#define	USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
#define	USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
#define	USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
#define	USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
#define	USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
#define	USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
#define	USB_OTG_GINTMSK_EOPFM_Pos (15U)
#define	USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
#define	USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
#define	USB_OTG_GINTMSK_EPMISM_Pos (17U)
#define	USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
#define	USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
#define	USB_OTG_GINTMSK_IEPINT_Pos (18U)
#define	USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
#define	USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
#define	USB_OTG_GINTMSK_OEPINT_Pos (19U)
#define	USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
#define	USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
#define	USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
#define	USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
#define	USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
#define	USB_OTG_GINTMSK_FSUSPM_Pos (22U)
#define	USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
#define	USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
#define	USB_OTG_GINTMSK_PRTIM_Pos (24U)
#define	USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
#define	USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
#define	USB_OTG_GINTMSK_HCIM_Pos (25U)
#define	USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
#define	USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
#define	USB_OTG_GINTMSK_PTXFEM_Pos (26U)
#define	USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
#define	USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
#define	USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
#define	USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
#define	USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
#define	USB_OTG_GINTMSK_DISCINT_Pos (29U)
#define	USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
#define	USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
#define	USB_OTG_GINTMSK_SRQIM_Pos (30U)
#define	USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
#define	USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
#define	USB_OTG_GINTMSK_WUIM_Pos (31U)
#define	USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
#define	USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
#define	USB_OTG_DAINT_IEPINT_Pos (0U)
#define	USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
#define	USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
#define	USB_OTG_DAINT_OEPINT_Pos (16U)
#define	USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
#define	USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
#define	USB_OTG_HAINTMSK_HAINTM_Pos (0U)
#define	USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
#define	USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
#define	USB_OTG_GRXSTSP_EPNUM_Pos (0U)
#define	USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
#define	USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
#define	USB_OTG_GRXSTSP_BCNT_Pos (4U)
#define	USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
#define	USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
#define	USB_OTG_GRXSTSP_DPID_Pos (15U)
#define	USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
#define	USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
#define	USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
#define	USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
#define	USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
#define	USB_OTG_DAINTMSK_IEPM_Pos (0U)
#define	USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
#define	USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
#define	USB_OTG_DAINTMSK_OEPM_Pos (16U)
#define	USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
#define	USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
#define	USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define	USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
#define	USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
#define	USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
#define	USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
#define	USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
#define	USB_OTG_NPTXFSA_Pos (0U)
#define	USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
#define	USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
#define	USB_OTG_NPTXFD_Pos (16U)
#define	USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
#define	USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
#define	USB_OTG_TX0FSA_Pos (0U)
#define	USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
#define	USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
#define	USB_OTG_TX0FD_Pos (16U)
#define	USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
#define	USB_OTG_TX0FD USB_OTG_TX0FD_Msk
#define	USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
#define	USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
#define	USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
#define	USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
#define	USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
#define	USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
#define	USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
#define	USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
#define	USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
#define	USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
#define	USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
#define	USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
#define	USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
#define	USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
#define	USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
#define	USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
#define	USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
#define	USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
#define	USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
#define	USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
#define	USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
#define	USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
#define	USB_OTG_DTHRCTL_ARPEN_Pos (27U)
#define	USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
#define	USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
#define	USB_OTG_DEACHINT_IEP1INT_Pos (1U)
#define	USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
#define	USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
#define	USB_OTG_DEACHINT_OEP1INT_Pos (17U)
#define	USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
#define	USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
#define	USB_OTG_GCCFG_PWRDWN_Pos (16U)
#define	USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
#define	USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
#define	USB_OTG_GCCFG_I2CPADEN_Pos (17U)
#define	USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
#define	USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
#define	USB_OTG_GCCFG_VBUSASEN_Pos (18U)
#define	USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
#define	USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
#define	USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
#define	USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
#define	USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
#define	USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
#define	USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
#define	USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
#define	USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
#define	USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
#define	USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
#define	USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
#define	USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
#define	USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
#define	USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
#define	USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
#define	USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
#define	USB_OTG_CID_PRODUCT_ID_Pos (0U)
#define	USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
#define	USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
#define	USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
#define	USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
#define	USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
#define	USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
#define	USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
#define	USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
#define	USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
#define	USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
#define	USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
#define	USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
#define	USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
#define	USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
#define	USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
#define	USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
#define	USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
#define	USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
#define	USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
#define	USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
#define	USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
#define	USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
#define	USB_OTG_HPRT_PCSTS_Pos (0U)
#define	USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
#define	USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
#define	USB_OTG_HPRT_PCDET_Pos (1U)
#define	USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
#define	USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
#define	USB_OTG_HPRT_PENA_Pos (2U)
#define	USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
#define	USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
#define	USB_OTG_HPRT_PENCHNG_Pos (3U)
#define	USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
#define	USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
#define	USB_OTG_HPRT_POCA_Pos (4U)
#define	USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
#define	USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
#define	USB_OTG_HPRT_POCCHNG_Pos (5U)
#define	USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
#define	USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
#define	USB_OTG_HPRT_PRES_Pos (6U)
#define	USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
#define	USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
#define	USB_OTG_HPRT_PSUSP_Pos (7U)
#define	USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
#define	USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
#define	USB_OTG_HPRT_PRST_Pos (8U)
#define	USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
#define	USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
#define	USB_OTG_HPRT_PLSTS_Pos (10U)
#define	USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
#define	USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
#define	USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
#define	USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
#define	USB_OTG_HPRT_PPWR_Pos (12U)
#define	USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
#define	USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
#define	USB_OTG_HPRT_PTCTL_Pos (13U)
#define	USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
#define	USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
#define	USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
#define	USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
#define	USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
#define	USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
#define	USB_OTG_HPRT_PSPD_Pos (17U)
#define	USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
#define	USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
#define	USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
#define	USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
#define	USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
#define	USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
#define	USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
#define	USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
#define	USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
#define	USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
#define	USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
#define	USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
#define	USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
#define	USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
#define	USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
#define	USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
#define	USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
#define	USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
#define	USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
#define	USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
#define	USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
#define	USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
#define	USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
#define	USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
#define	USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
#define	USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
#define	USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
#define	USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
#define	USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
#define	USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
#define	USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
#define	USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
#define	USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
#define	USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
#define	USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
#define	USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
#define	USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
#define	USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
#define	USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
#define	USB_OTG_DIEPCTL_USBAEP_Pos (15U)
#define	USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
#define	USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
#define	USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
#define	USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
#define	USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
#define	USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
#define	USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
#define	USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
#define	USB_OTG_DIEPCTL_EPTYP_Pos (18U)
#define	USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
#define	USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
#define	USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
#define	USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
#define	USB_OTG_DIEPCTL_STALL_Pos (21U)
#define	USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
#define	USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
#define	USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
#define	USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
#define	USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
#define	USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
#define	USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
#define	USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
#define	USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
#define	USB_OTG_DIEPCTL_CNAK_Pos (26U)
#define	USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
#define	USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
#define	USB_OTG_DIEPCTL_SNAK_Pos (27U)
#define	USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
#define	USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
#define	USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
#define	USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
#define	USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
#define	USB_OTG_DIEPCTL_EPDIS_Pos (30U)
#define	USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
#define	USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
#define	USB_OTG_DIEPCTL_EPENA_Pos (31U)
#define	USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
#define	USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
#define	USB_OTG_HCCHAR_MPSIZ_Pos (0U)
#define	USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
#define	USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
#define	USB_OTG_HCCHAR_EPNUM_Pos (11U)
#define	USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
#define	USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
#define	USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
#define	USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
#define	USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
#define	USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
#define	USB_OTG_HCCHAR_EPDIR_Pos (15U)
#define	USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
#define	USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
#define	USB_OTG_HCCHAR_LSDEV_Pos (17U)
#define	USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
#define	USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
#define	USB_OTG_HCCHAR_EPTYP_Pos (18U)
#define	USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
#define	USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
#define	USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
#define	USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
#define	USB_OTG_HCCHAR_MC_Pos (20U)
#define	USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
#define	USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
#define	USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
#define	USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
#define	USB_OTG_HCCHAR_DAD_Pos (22U)
#define	USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
#define	USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
#define	USB_OTG_HCCHAR_ODDFRM_Pos (29U)
#define	USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
#define	USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
#define	USB_OTG_HCCHAR_CHDIS_Pos (30U)
#define	USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
#define	USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
#define	USB_OTG_HCCHAR_CHENA_Pos (31U)
#define	USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
#define	USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
#define	USB_OTG_HCSPLT_PRTADDR_Pos (0U)
#define	USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
#define	USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_Pos (7U)
#define	USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
#define	USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
#define	USB_OTG_HCSPLT_XACTPOS_Pos (14U)
#define	USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
#define	USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
#define	USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
#define	USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
#define	USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
#define	USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
#define	USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
#define	USB_OTG_HCSPLT_SPLITEN_Pos (31U)
#define	USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
#define	USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
#define	USB_OTG_HCINT_XFRC_Pos (0U)
#define	USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
#define	USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
#define	USB_OTG_HCINT_CHH_Pos (1U)
#define	USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
#define	USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
#define	USB_OTG_HCINT_AHBERR_Pos (2U)
#define	USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
#define	USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
#define	USB_OTG_HCINT_STALL_Pos (3U)
#define	USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
#define	USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
#define	USB_OTG_HCINT_NAK_Pos (4U)
#define	USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
#define	USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
#define	USB_OTG_HCINT_ACK_Pos (5U)
#define	USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
#define	USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
#define	USB_OTG_HCINT_NYET_Pos (6U)
#define	USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
#define	USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
#define	USB_OTG_HCINT_TXERR_Pos (7U)
#define	USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
#define	USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
#define	USB_OTG_HCINT_BBERR_Pos (8U)
#define	USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
#define	USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
#define	USB_OTG_HCINT_FRMOR_Pos (9U)
#define	USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
#define	USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
#define	USB_OTG_HCINT_DTERR_Pos (10U)
#define	USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
#define	USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
#define	USB_OTG_DIEPINT_XFRC_Pos (0U)
#define	USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
#define	USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
#define	USB_OTG_DIEPINT_EPDISD_Pos (1U)
#define	USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
#define	USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
#define	USB_OTG_DIEPINT_AHBERR_Pos (2U)
#define	USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
#define	USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
#define	USB_OTG_DIEPINT_TOC_Pos (3U)
#define	USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
#define	USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
#define	USB_OTG_DIEPINT_ITTXFE_Pos (4U)
#define	USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
#define	USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
#define	USB_OTG_DIEPINT_INEPNM_Pos (5U)
#define	USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
#define	USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
#define	USB_OTG_DIEPINT_INEPNE_Pos (6U)
#define	USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
#define	USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
#define	USB_OTG_DIEPINT_TXFE_Pos (7U)
#define	USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
#define	USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
#define	USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
#define	USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
#define	USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
#define	USB_OTG_DIEPINT_BNA_Pos (9U)
#define	USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
#define	USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
#define	USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
#define	USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
#define	USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
#define	USB_OTG_DIEPINT_BERR_Pos (12U)
#define	USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
#define	USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
#define	USB_OTG_DIEPINT_NAK_Pos (13U)
#define	USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
#define	USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
#define	USB_OTG_HCINTMSK_XFRCM_Pos (0U)
#define	USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
#define	USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
#define	USB_OTG_HCINTMSK_CHHM_Pos (1U)
#define	USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
#define	USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
#define	USB_OTG_HCINTMSK_AHBERR_Pos (2U)
#define	USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
#define	USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
#define	USB_OTG_HCINTMSK_STALLM_Pos (3U)
#define	USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
#define	USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
#define	USB_OTG_HCINTMSK_NAKM_Pos (4U)
#define	USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
#define	USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
#define	USB_OTG_HCINTMSK_ACKM_Pos (5U)
#define	USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
#define	USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
#define	USB_OTG_HCINTMSK_NYET_Pos (6U)
#define	USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
#define	USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
#define	USB_OTG_HCINTMSK_TXERRM_Pos (7U)
#define	USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
#define	USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
#define	USB_OTG_HCINTMSK_BBERRM_Pos (8U)
#define	USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
#define	USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
#define	USB_OTG_HCINTMSK_FRMORM_Pos (9U)
#define	USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
#define	USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
#define	USB_OTG_HCINTMSK_DTERRM_Pos (10U)
#define	USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
#define	USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
#define	USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
#define	USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
#define	USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
#define	USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
#define	USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
#define	USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
#define	USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
#define	USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
#define	USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
#define	USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
#define	USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
#define	USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
#define	USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
#define	USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
#define	USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
#define	USB_OTG_HCTSIZ_DOPING_Pos (31U)
#define	USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
#define	USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
#define	USB_OTG_HCTSIZ_DPID_Pos (29U)
#define	USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
#define	USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
#define	USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
#define	USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
#define	USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
#define	USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
#define	USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
#define	USB_OTG_HCDMA_DMAADDR_Pos (0U)
#define	USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
#define	USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
#define	USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
#define	USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
#define	USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
#define	USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
#define	USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
#define	USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
#define	USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
#define	USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
#define	USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
#define	USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
#define	USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
#define	USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /!< Maximum packet size /
#define	USB_OTG_DOEPCTL_USBAEP_Pos (15U)
#define	USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
#define	USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
#define	USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
#define	USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
#define	USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
#define	USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
#define	USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
#define	USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
#define	USB_OTG_DOEPCTL_EPTYP_Pos (18U)
#define	USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
#define	USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
#define	USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
#define	USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
#define	USB_OTG_DOEPCTL_SNPM_Pos (20U)
#define	USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
#define	USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
#define	USB_OTG_DOEPCTL_STALL_Pos (21U)
#define	USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
#define	USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
#define	USB_OTG_DOEPCTL_CNAK_Pos (26U)
#define	USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
#define	USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
#define	USB_OTG_DOEPCTL_SNAK_Pos (27U)
#define	USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
#define	USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
#define	USB_OTG_DOEPCTL_EPDIS_Pos (30U)
#define	USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
#define	USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
#define	USB_OTG_DOEPCTL_EPENA_Pos (31U)
#define	USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
#define	USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
#define	USB_OTG_DOEPINT_XFRC_Pos (0U)
#define	USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
#define	USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
#define	USB_OTG_DOEPINT_EPDISD_Pos (1U)
#define	USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
#define	USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
#define	USB_OTG_DOEPINT_AHBERR_Pos (2U)
#define	USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
#define	USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
#define	USB_OTG_DOEPINT_STUP_Pos (3U)
#define	USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
#define	USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
#define	USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define	USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
#define	USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
#define	USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
#define	USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
#define	USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
#define	USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define	USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
#define	USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
#define	USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
#define	USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
#define	USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
#define	USB_OTG_DOEPINT_NAK_Pos (13U)
#define	USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
#define	USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
#define	USB_OTG_DOEPINT_NYET_Pos (14U)
#define	USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
#define	USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
#define	USB_OTG_DOEPINT_STPKTRX_Pos (15U)
#define	USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
#define	USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
#define	USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
#define	USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
#define	USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
#define	USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
#define	USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
#define	USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
#define	USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
#define	USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
#define	USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
#define	USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
#define	USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
#define	USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
#define	USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
#define	USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
#define	USB_OTG_PCGCCTL_GATECLK_Pos (1U)
#define	USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
#define	USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
#define	USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
#define	USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
#define	USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
#define	USB_OTG_CHNUM_Pos (0U)
#define	USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
#define	USB_OTG_CHNUM USB_OTG_CHNUM_Msk
#define	USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
#define	USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
#define	USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
#define	USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
#define	USB_OTG_BCNT_Pos (4U)
#define	USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
#define	USB_OTG_BCNT USB_OTG_BCNT_Msk
#define	USB_OTG_DPID_Pos (15U)
#define	USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
#define	USB_OTG_DPID USB_OTG_DPID_Msk
#define	USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
#define	USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
#define	USB_OTG_PKTSTS_Pos (17U)
#define	USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
#define	USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
#define	USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
#define	USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
#define	USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
#define	USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
#define	USB_OTG_EPNUM_Pos (0U)
#define	USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
#define	USB_OTG_EPNUM USB_OTG_EPNUM_Msk
#define	USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
#define	USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
#define	USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
#define	USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
#define	USB_OTG_FRMNUM_Pos (21U)
#define	USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
#define	USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
#define	USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
#define	USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
#define	USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
#define	USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)

Detailed Description

Macro Definition Documentation

◆ ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk

ADCPRE[1:0] bits (ADC prescaler)

◆ ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)

0x00010000

◆ ADC_CCR_ADCPRE_1

#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)

0x00020000

◆ ADC_CCR_ADCPRE_Msk

#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)

0x00030000

◆ ADC_CCR_DDS

#define ADC_CCR_DDS ADC_CCR_DDS_Msk

DMA disable selection (Multi-ADC mode)

◆ ADC_CCR_DDS_Msk

#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)

0x00002000

◆ ADC_CCR_DELAY

#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk

DELAY[3:0] bits (Delay between 2 sampling phases)

◆ ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

0x00000100

◆ ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

0x00000200

◆ ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

0x00000400

◆ ADC_CCR_DELAY_3

#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

0x00000800

◆ ADC_CCR_DELAY_Msk

#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

0x00000F00

◆ ADC_CCR_DMA

#define ADC_CCR_DMA ADC_CCR_DMA_Msk

DMA[1:0] bits (Direct Memory Access mode for multimode)

◆ ADC_CCR_DMA_0

#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)

0x00004000

◆ ADC_CCR_DMA_1

#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)

0x00008000

◆ ADC_CCR_DMA_Msk

#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)

0x0000C000

◆ ADC_CCR_MULTI

#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk

MULTI[4:0] bits (Multi-ADC mode selection)

◆ ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)

0x00000001

◆ ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)

0x00000002

◆ ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)

0x00000004

◆ ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)

0x00000008

◆ ADC_CCR_MULTI_4

#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)

0x00000010

◆ ADC_CCR_MULTI_Msk

#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)

0x0000001F

◆ ADC_CCR_TSVREFE

#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk

Temperature Sensor and VREFINT Enable

◆ ADC_CCR_TSVREFE_Msk

#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)

0x00800000

◆ ADC_CCR_VBATE

#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk

VBAT Enable

◆ ADC_CCR_VBATE_Msk

#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)

0x00400000

◆ ADC_CDR_DATA1

#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk

1st data of a pair of regular conversions

◆ ADC_CDR_DATA1_Msk

#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)

0x0000FFFF

◆ ADC_CDR_DATA2

#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk

2nd data of a pair of regular conversions

◆ ADC_CDR_DATA2_Msk

#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)

0xFFFF0000

◆ ADC_CR1_AWDCH

#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk

AWDCH[4:0] bits (Analog watchdog channel select bits)

◆ ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)

0x00000001

◆ ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)

0x00000002

◆ ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)

0x00000004

◆ ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)

0x00000008

◆ ADC_CR1_AWDCH_4

#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)

0x00000010

◆ ADC_CR1_AWDCH_Msk

#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)

0x0000001F

◆ ADC_CR1_AWDEN

#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk

Analog watchdog enable on regular channels

◆ ADC_CR1_AWDEN_Msk

#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)

0x00800000

◆ ADC_CR1_AWDIE

#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk

AAnalog Watchdog interrupt enable

◆ ADC_CR1_AWDIE_Msk

#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)

0x00000040

◆ ADC_CR1_AWDSGL

#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk

Enable the watchdog on a single channel in scan mode

◆ ADC_CR1_AWDSGL_Msk

#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)

0x00000200

◆ ADC_CR1_DISCEN

#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk

Discontinuous mode on regular channels

◆ ADC_CR1_DISCEN_Msk

#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)

0x00000800

◆ ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk

DISCNUM[2:0] bits (Discontinuous mode channel count)

◆ ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)

0x00002000

◆ ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)

0x00004000

◆ ADC_CR1_DISCNUM_2

#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)

0x00008000

◆ ADC_CR1_DISCNUM_Msk

#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)

0x0000E000

◆ ADC_CR1_EOCIE

#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk

Interrupt enable for EOC

◆ ADC_CR1_EOCIE_Msk

#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)

0x00000020

◆ ADC_CR1_JAUTO

#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk

Automatic injected group conversion

◆ ADC_CR1_JAUTO_Msk

#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)

0x00000400

◆ ADC_CR1_JAWDEN

#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk

Analog watchdog enable on injected channels

◆ ADC_CR1_JAWDEN_Msk

#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)

0x00400000

◆ ADC_CR1_JDISCEN

#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk

Discontinuous mode on injected channels

◆ ADC_CR1_JDISCEN_Msk

#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)

0x00001000

◆ ADC_CR1_JEOCIE

#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk

Interrupt enable for injected channels

◆ ADC_CR1_JEOCIE_Msk

#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)

0x00000080

◆ ADC_CR1_OVRIE

#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk

overrun interrupt enable

◆ ADC_CR1_OVRIE_Msk

#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)

0x04000000

◆ ADC_CR1_RES

#define ADC_CR1_RES ADC_CR1_RES_Msk

RES[2:0] bits (Resolution)

◆ ADC_CR1_RES_0

#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)

0x01000000

◆ ADC_CR1_RES_1

#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)

0x02000000

◆ ADC_CR1_RES_Msk

#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)

0x03000000

◆ ADC_CR1_SCAN

#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk

Scan mode

◆ ADC_CR1_SCAN_Msk

#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)

0x00000100

◆ ADC_CR2_ADON

#define ADC_CR2_ADON ADC_CR2_ADON_Msk

A/D Converter ON / OFF

◆ ADC_CR2_ADON_Msk

#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)

0x00000001

◆ ADC_CR2_ALIGN

#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk

Data Alignment

◆ ADC_CR2_ALIGN_Msk

#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)

0x00000800

◆ ADC_CR2_CONT

#define ADC_CR2_CONT ADC_CR2_CONT_Msk

Continuous Conversion

◆ ADC_CR2_CONT_Msk

#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)

0x00000002

◆ ADC_CR2_DDS

#define ADC_CR2_DDS ADC_CR2_DDS_Msk

DMA disable selection (Single ADC)

◆ ADC_CR2_DDS_Msk

#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)

0x00000200

◆ ADC_CR2_DMA

#define ADC_CR2_DMA ADC_CR2_DMA_Msk

Direct Memory access mode

◆ ADC_CR2_DMA_Msk

#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)

0x00000100

◆ ADC_CR2_EOCS

#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk

End of conversion selection

◆ ADC_CR2_EOCS_Msk

#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)

0x00000400

◆ ADC_CR2_EXTEN

#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

◆ ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)

0x10000000

◆ ADC_CR2_EXTEN_1

#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)

0x20000000

◆ ADC_CR2_EXTEN_Msk

#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)

0x30000000

◆ ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk

EXTSEL[3:0] bits (External Event Select for regular group)

◆ ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)

0x01000000

◆ ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)

0x02000000

◆ ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)

0x04000000

◆ ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)

0x08000000

◆ ADC_CR2_EXTSEL_Msk

#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)

0x0F000000

◆ ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

◆ ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)

0x00100000

◆ ADC_CR2_JEXTEN_1

#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)

0x00200000

◆ ADC_CR2_JEXTEN_Msk

#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)

0x00300000

◆ ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk

JEXTSEL[3:0] bits (External event select for injected group)

◆ ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)

0x00010000

◆ ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)

0x00020000

◆ ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)

0x00040000

◆ ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)

0x00080000

◆ ADC_CR2_JEXTSEL_Msk

#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)

0x000F0000

◆ ADC_CR2_JSWSTART

#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk

Start Conversion of injected channels

◆ ADC_CR2_JSWSTART_Msk

#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)

0x00400000

◆ ADC_CR2_SWSTART

#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk

Start Conversion of regular channels

◆ ADC_CR2_SWSTART_Msk

#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)

0x40000000

◆ ADC_CSR_AWD1

#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk

ADC1 Analog watchdog flag

◆ ADC_CSR_AWD1_Msk

#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)

0x00000001

◆ ADC_CSR_AWD2

#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk

ADC2 Analog watchdog flag

◆ ADC_CSR_AWD2_Msk

#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)

0x00000100

◆ ADC_CSR_AWD3

#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk

ADC3 Analog watchdog flag

◆ ADC_CSR_AWD3_Msk

#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)

0x00010000

◆ ADC_CSR_EOC1

#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk

ADC1 End of conversion

◆ ADC_CSR_EOC1_Msk

#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)

0x00000002

◆ ADC_CSR_EOC2

#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk

ADC2 End of conversion

◆ ADC_CSR_EOC2_Msk

#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)

0x00000200

◆ ADC_CSR_EOC3

#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk

ADC3 End of conversion

◆ ADC_CSR_EOC3_Msk

#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)

0x00020000

◆ ADC_CSR_JEOC1

#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk

ADC1 Injected channel end of conversion

◆ ADC_CSR_JEOC1_Msk

#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)

0x00000004

◆ ADC_CSR_JEOC2

#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk

ADC2 Injected channel end of conversion

◆ ADC_CSR_JEOC2_Msk

#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)

0x00000400

◆ ADC_CSR_JEOC3

#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk

ADC3 Injected channel end of conversion

◆ ADC_CSR_JEOC3_Msk

#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)

0x00040000

◆ ADC_CSR_JSTRT1

#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk

ADC1 Injected channel Start flag

◆ ADC_CSR_JSTRT1_Msk

#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)

0x00000008

◆ ADC_CSR_JSTRT2

#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk

ADC2 Injected channel Start flag

◆ ADC_CSR_JSTRT2_Msk

#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)

0x00000800

◆ ADC_CSR_JSTRT3

#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk

ADC3 Injected channel Start flag

◆ ADC_CSR_JSTRT3_Msk

#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)

0x00080000

◆ ADC_CSR_OVR1

#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk

ADC1 DMA overrun flag

◆ ADC_CSR_OVR1_Msk

#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)

0x00000020

◆ ADC_CSR_OVR2

#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk

ADC2 DMA overrun flag

◆ ADC_CSR_OVR2_Msk

#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)

0x00002000

◆ ADC_CSR_OVR3

#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk

ADC3 DMA overrun flag

◆ ADC_CSR_OVR3_Msk

#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)

0x00200000

◆ ADC_CSR_STRT1

#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk

ADC1 Regular channel Start flag

◆ ADC_CSR_STRT1_Msk

#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)

0x00000010

◆ ADC_CSR_STRT2

#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk

ADC2 Regular channel Start flag

◆ ADC_CSR_STRT2_Msk

#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)

0x00001000

◆ ADC_CSR_STRT3

#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk

ADC3 Regular channel Start flag

◆ ADC_CSR_STRT3_Msk

#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)

0x00100000

◆ ADC_DR_ADC2DATA

#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk

ADC2 data

◆ ADC_DR_ADC2DATA_Msk

#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)

0xFFFF0000

◆ ADC_DR_DATA

#define ADC_DR_DATA ADC_DR_DATA_Msk

Regular data

◆ ADC_DR_DATA_Msk

#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)

0x0000FFFF

◆ ADC_HTR_HT

#define ADC_HTR_HT ADC_HTR_HT_Msk

Analog watchdog high threshold

◆ ADC_HTR_HT_Msk

#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)

0x00000FFF

◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

Injected data

◆ ADC_JDR1_JDATA_Msk

#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

Injected data

◆ ADC_JDR2_JDATA_Msk

#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

Injected data

◆ ADC_JDR3_JDATA_Msk

#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

Injected data

◆ ADC_JDR4_JDATA_Msk

#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

0x0000FFFF

◆ ADC_JOFR1_JOFFSET1

#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk

Data offset for injected channel 1

◆ ADC_JOFR1_JOFFSET1_Msk

#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)

0x00000FFF

◆ ADC_JOFR2_JOFFSET2

#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk

Data offset for injected channel 2

◆ ADC_JOFR2_JOFFSET2_Msk

#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)

0x00000FFF

◆ ADC_JOFR3_JOFFSET3

#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk

Data offset for injected channel 3

◆ ADC_JOFR3_JOFFSET3_Msk

#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)

0x00000FFF

◆ ADC_JOFR4_JOFFSET4

#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk

Data offset for injected channel 4

◆ ADC_JOFR4_JOFFSET4_Msk

#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)

0x00000FFF

◆ ADC_JSQR_JL

#define ADC_JSQR_JL ADC_JSQR_JL_Msk

JL[1:0] bits (Injected Sequence length)

◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

0x00100000

◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

0x00200000

◆ ADC_JSQR_JL_Msk

#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

0x00300000

◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

JSQ1[4:0] bits (1st conversion in injected sequence)

◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

0x00000001

◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

0x00000002

◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

0x00000004

◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

0x00000008

◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

0x00000010

◆ ADC_JSQR_JSQ1_Msk

#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

0x0000001F

◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

JSQ2[4:0] bits (2nd conversion in injected sequence)

◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

0x00000020

◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

0x00000040

◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

0x00000080

◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

0x00000100

◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

0x00000200

◆ ADC_JSQR_JSQ2_Msk

#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

0x000003E0

◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

JSQ3[4:0] bits (3rd conversion in injected sequence)

◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

0x00000400

◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

0x00000800

◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

0x00001000

◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

0x00002000

◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

0x00004000

◆ ADC_JSQR_JSQ3_Msk

#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

0x00007C00

◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

JSQ4[4:0] bits (4th conversion in injected sequence)

◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

0x00008000

◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

0x00010000

◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

0x00020000

◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

0x00040000

◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

0x00080000

◆ ADC_JSQR_JSQ4_Msk

#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

0x000F8000

◆ ADC_LTR_LT

#define ADC_LTR_LT ADC_LTR_LT_Msk

Analog watchdog low threshold

◆ ADC_LTR_LT_Msk

#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)

0x00000FFF

◆ ADC_MULTIMODE_SUPPORT

#define ADC_MULTIMODE_SUPPORT

ADC Multimode feature available on specific devices

◆ ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk

SMP10[2:0] bits (Channel 10 Sample time selection)

◆ ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)

0x00000001

◆ ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)

0x00000002

◆ ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)

0x00000004

◆ ADC_SMPR1_SMP10_Msk

#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)

0x00000007

◆ ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk

SMP11[2:0] bits (Channel 11 Sample time selection)

◆ ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)

0x00000008

◆ ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)

0x00000010

◆ ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)

0x00000020

◆ ADC_SMPR1_SMP11_Msk

#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)

0x00000038

◆ ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk

SMP12[2:0] bits (Channel 12 Sample time selection)

◆ ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)

0x00000040

◆ ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)

0x00000080

◆ ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)

0x00000100

◆ ADC_SMPR1_SMP12_Msk

#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)

0x000001C0

◆ ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk

SMP13[2:0] bits (Channel 13 Sample time selection)

◆ ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)

0x00000200

◆ ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)

0x00000400

◆ ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)

0x00000800

◆ ADC_SMPR1_SMP13_Msk

#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)

0x00000E00

◆ ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk

SMP14[2:0] bits (Channel 14 Sample time selection)

◆ ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)

0x00001000

◆ ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)

0x00002000

◆ ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)

0x00004000

◆ ADC_SMPR1_SMP14_Msk

#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)

0x00007000

◆ ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk

SMP15[2:0] bits (Channel 15 Sample time selection)

◆ ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)

0x00008000

◆ ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)

0x00010000

◆ ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)

0x00020000

◆ ADC_SMPR1_SMP15_Msk

#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)

0x00038000

◆ ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk

SMP16[2:0] bits (Channel 16 Sample time selection)

◆ ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)

0x00040000

◆ ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)

0x00080000

◆ ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)

0x00100000

◆ ADC_SMPR1_SMP16_Msk

#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)

0x001C0000

◆ ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk

SMP17[2:0] bits (Channel 17 Sample time selection)

◆ ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)

0x00200000

◆ ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)

0x00400000

◆ ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)

0x00800000

◆ ADC_SMPR1_SMP17_Msk

#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)

0x00E00000

◆ ADC_SMPR1_SMP18

#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk

SMP18[2:0] bits (Channel 18 Sample time selection)

◆ ADC_SMPR1_SMP18_0

#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)

0x01000000

◆ ADC_SMPR1_SMP18_1

#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)

0x02000000

◆ ADC_SMPR1_SMP18_2

#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)

0x04000000

◆ ADC_SMPR1_SMP18_Msk

#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)

0x07000000

◆ ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk

SMP0[2:0] bits (Channel 0 Sample time selection)

◆ ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)

0x00000001

◆ ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)

0x00000002

◆ ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)

0x00000004

◆ ADC_SMPR2_SMP0_Msk

#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)

0x00000007

◆ ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk

SMP1[2:0] bits (Channel 1 Sample time selection)

◆ ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)

0x00000008

◆ ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)

0x00000010

◆ ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)

0x00000020

◆ ADC_SMPR2_SMP1_Msk

#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)

0x00000038

◆ ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk

SMP2[2:0] bits (Channel 2 Sample time selection)

◆ ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)

0x00000040

◆ ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)

0x00000080

◆ ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)

0x00000100

◆ ADC_SMPR2_SMP2_Msk

#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)

0x000001C0

◆ ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk

SMP3[2:0] bits (Channel 3 Sample time selection)

◆ ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)

0x00000200

◆ ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)

0x00000400

◆ ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)

0x00000800

◆ ADC_SMPR2_SMP3_Msk

#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)

0x00000E00

◆ ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk

SMP4[2:0] bits (Channel 4 Sample time selection)

◆ ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)

0x00001000

◆ ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)

0x00002000

◆ ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)

0x00004000

◆ ADC_SMPR2_SMP4_Msk

#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)

0x00007000

◆ ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk

SMP5[2:0] bits (Channel 5 Sample time selection)

◆ ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)

0x00008000

◆ ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)

0x00010000

◆ ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)

0x00020000

◆ ADC_SMPR2_SMP5_Msk

#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)

0x00038000

◆ ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk

SMP6[2:0] bits (Channel 6 Sample time selection)

◆ ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)

0x00040000

◆ ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)

0x00080000

◆ ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)

0x00100000

◆ ADC_SMPR2_SMP6_Msk

#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)

0x001C0000

◆ ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk

SMP7[2:0] bits (Channel 7 Sample time selection)

◆ ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)

0x00200000

◆ ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)

0x00400000

◆ ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)

0x00800000

◆ ADC_SMPR2_SMP7_Msk

#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)

0x00E00000

◆ ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk

SMP8[2:0] bits (Channel 8 Sample time selection)

◆ ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)

0x01000000

◆ ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)

0x02000000

◆ ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)

0x04000000

◆ ADC_SMPR2_SMP8_Msk

#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)

0x07000000

◆ ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk

SMP9[2:0] bits (Channel 9 Sample time selection)

◆ ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)

0x08000000

◆ ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)

0x10000000

◆ ADC_SMPR2_SMP9_2

#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)

0x20000000

◆ ADC_SMPR2_SMP9_Msk

#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)

0x38000000

◆ ADC_SQR1_L

#define ADC_SQR1_L ADC_SQR1_L_Msk

L[3:0] bits (Regular channel sequence length)

◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

0x00100000

◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

0x00200000

◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

0x00400000

◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

0x00800000

◆ ADC_SQR1_L_Msk

#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

0x00F00000

◆ ADC_SQR1_SQ13

#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk

SQ13[4:0] bits (13th conversion in regular sequence)

◆ ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)

0x00000001

◆ ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)

0x00000002

◆ ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)

0x00000004

◆ ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)

0x00000008

◆ ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)

0x00000010

◆ ADC_SQR1_SQ13_Msk

#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)

0x0000001F

◆ ADC_SQR1_SQ14

#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk

SQ14[4:0] bits (14th conversion in regular sequence)

◆ ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)

0x00000020

◆ ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)

0x00000040

◆ ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)

0x00000080

◆ ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)

0x00000100

◆ ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)

0x00000200

◆ ADC_SQR1_SQ14_Msk

#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)

0x000003E0

◆ ADC_SQR1_SQ15

#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk

SQ15[4:0] bits (15th conversion in regular sequence)

◆ ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)

0x00000400

◆ ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)

0x00000800

◆ ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)

0x00001000

◆ ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)

0x00002000

◆ ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)

0x00004000

◆ ADC_SQR1_SQ15_Msk

#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)

0x00007C00

◆ ADC_SQR1_SQ16

#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk

SQ16[4:0] bits (16th conversion in regular sequence)

◆ ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)

0x00008000

◆ ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)

0x00010000

◆ ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)

0x00020000

◆ ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)

0x00040000

◆ ADC_SQR1_SQ16_4

#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)

0x00080000

◆ ADC_SQR1_SQ16_Msk

#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)

0x000F8000

◆ ADC_SQR2_SQ10

#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk

SQ10[4:0] bits (10th conversion in regular sequence)

◆ ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)

0x00008000

◆ ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)

0x00010000

◆ ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)

0x00020000

◆ ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)

0x00040000

◆ ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)

0x00080000

◆ ADC_SQR2_SQ10_Msk

#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)

0x000F8000

◆ ADC_SQR2_SQ11

#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk

SQ11[4:0] bits (11th conversion in regular sequence)

◆ ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)

0x00100000

◆ ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)

0x00200000

◆ ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)

0x00400000

◆ ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)

0x00800000

◆ ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)

0x01000000

◆ ADC_SQR2_SQ11_Msk

#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)

0x01F00000

◆ ADC_SQR2_SQ12

#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk

SQ12[4:0] bits (12th conversion in regular sequence)

◆ ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)

0x02000000

◆ ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)

0x04000000

◆ ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)

0x08000000

◆ ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)

0x10000000

◆ ADC_SQR2_SQ12_4

#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)

0x20000000

◆ ADC_SQR2_SQ12_Msk

#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)

0x3E000000

◆ ADC_SQR2_SQ7

#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

SQ7[4:0] bits (7th conversion in regular sequence)

◆ ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

0x00000001

◆ ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

0x00000002

◆ ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

0x00000004

◆ ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

0x00000008

◆ ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

0x00000010

◆ ADC_SQR2_SQ7_Msk

#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

0x0000001F

◆ ADC_SQR2_SQ8

#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

SQ8[4:0] bits (8th conversion in regular sequence)

◆ ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

0x00000020

◆ ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

0x00000040

◆ ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

0x00000080

◆ ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

0x00000100

◆ ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

0x00000200

◆ ADC_SQR2_SQ8_Msk

#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

0x000003E0

◆ ADC_SQR2_SQ9

#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

SQ9[4:0] bits (9th conversion in regular sequence)

◆ ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

0x00000400

◆ ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

0x00000800

◆ ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

0x00001000

◆ ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

0x00002000

◆ ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

0x00004000

◆ ADC_SQR2_SQ9_Msk

#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

0x00007C00

◆ ADC_SQR3_SQ1

#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk

SQ1[4:0] bits (1st conversion in regular sequence)

◆ ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)

0x00000001

◆ ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)

0x00000002

◆ ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)

0x00000004

◆ ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)

0x00000008

◆ ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)

0x00000010

◆ ADC_SQR3_SQ1_Msk

#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)

0x0000001F

◆ ADC_SQR3_SQ2

#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk

SQ2[4:0] bits (2nd conversion in regular sequence)

◆ ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)

0x00000020

◆ ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)

0x00000040

◆ ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)

0x00000080

◆ ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)

0x00000100

◆ ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)

0x00000200

◆ ADC_SQR3_SQ2_Msk

#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)

0x000003E0

◆ ADC_SQR3_SQ3

#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk

SQ3[4:0] bits (3rd conversion in regular sequence)

◆ ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)

0x00000400

◆ ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)

0x00000800

◆ ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)

0x00001000

◆ ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)

0x00002000

◆ ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)

0x00004000

◆ ADC_SQR3_SQ3_Msk

#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)

0x00007C00

◆ ADC_SQR3_SQ4

#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk

SQ4[4:0] bits (4th conversion in regular sequence)

◆ ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)

0x00008000

◆ ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)

0x00010000

◆ ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)

0x00020000

◆ ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)

0x00040000

◆ ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)

0x00080000

◆ ADC_SQR3_SQ4_Msk

#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)

0x000F8000

◆ ADC_SQR3_SQ5

#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk

SQ5[4:0] bits (5th conversion in regular sequence)

◆ ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)

0x00100000

◆ ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)

0x00200000

◆ ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)

0x00400000

◆ ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)

0x00800000

◆ ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)

0x01000000

◆ ADC_SQR3_SQ5_Msk

#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)

0x01F00000

◆ ADC_SQR3_SQ6

#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk

SQ6[4:0] bits (6th conversion in regular sequence)

◆ ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)

0x02000000

◆ ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)

0x04000000

◆ ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)

0x08000000

◆ ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)

0x10000000

◆ ADC_SQR3_SQ6_4

#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)

0x20000000

◆ ADC_SQR3_SQ6_Msk

#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)

0x3E000000

◆ ADC_SR_AWD

#define ADC_SR_AWD ADC_SR_AWD_Msk

Analog watchdog flag

◆ ADC_SR_AWD_Msk

#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)

0x00000001

◆ ADC_SR_EOC

#define ADC_SR_EOC ADC_SR_EOC_Msk

End of conversion

◆ ADC_SR_EOC_Msk

#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)

0x00000002

◆ ADC_SR_JEOC

#define ADC_SR_JEOC ADC_SR_JEOC_Msk

Injected channel end of conversion

◆ ADC_SR_JEOC_Msk

#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)

0x00000004

◆ ADC_SR_JSTRT

#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk

Injected channel Start flag

◆ ADC_SR_JSTRT_Msk

#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)

0x00000008

◆ ADC_SR_OVR

#define ADC_SR_OVR ADC_SR_OVR_Msk

Overrun flag

◆ ADC_SR_OVR_Msk

#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)

0x00000020

◆ ADC_SR_STRT

#define ADC_SR_STRT ADC_SR_STRT_Msk

Regular channel Start flag

◆ ADC_SR_STRT_Msk

#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)

0x00000010

◆ CAN_BTR_BRP

#define CAN_BTR_BRP CAN_BTR_BRP_Msk

Baud Rate Prescaler

◆ CAN_BTR_BRP_Msk

#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)

0x000003FF

◆ CAN_BTR_LBKM

#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk

Loop Back Mode (Debug)

◆ CAN_BTR_LBKM_Msk

#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)

0x40000000

◆ CAN_BTR_SILM

#define CAN_BTR_SILM CAN_BTR_SILM_Msk

Silent Mode Mailbox registers

◆ CAN_BTR_SILM_Msk

#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)

0x80000000

◆ CAN_BTR_SJW

#define CAN_BTR_SJW CAN_BTR_SJW_Msk

Resynchronization Jump Width

◆ CAN_BTR_SJW_0

#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)

0x01000000

◆ CAN_BTR_SJW_1

#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)

0x02000000

◆ CAN_BTR_SJW_Msk

#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)

0x03000000

◆ CAN_BTR_TS1

#define CAN_BTR_TS1 CAN_BTR_TS1_Msk

Time Segment 1

◆ CAN_BTR_TS1_0

#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)

0x00010000

◆ CAN_BTR_TS1_1

#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)

0x00020000

◆ CAN_BTR_TS1_2

#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)

0x00040000

◆ CAN_BTR_TS1_3

#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)

0x00080000

◆ CAN_BTR_TS1_Msk

#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)

0x000F0000

◆ CAN_BTR_TS2

#define CAN_BTR_TS2 CAN_BTR_TS2_Msk

Time Segment 2

◆ CAN_BTR_TS2_0

#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)

0x00100000

◆ CAN_BTR_TS2_1

#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)

0x00200000

◆ CAN_BTR_TS2_2

#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)

0x00400000

◆ CAN_BTR_TS2_Msk

#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)

0x00700000

◆ CAN_ESR_BOFF

#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk

Bus-Off Flag

◆ CAN_ESR_BOFF_Msk

#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)

0x00000004

◆ CAN_ESR_EPVF

#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk

Error Passive Flag

◆ CAN_ESR_EPVF_Msk

#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)

0x00000002

◆ CAN_ESR_EWGF

#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk

Error Warning Flag

◆ CAN_ESR_EWGF_Msk

#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)

0x00000001

◆ CAN_ESR_LEC

#define CAN_ESR_LEC CAN_ESR_LEC_Msk

LEC[2:0] bits (Last Error Code)

◆ CAN_ESR_LEC_0

#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)

0x00000010

◆ CAN_ESR_LEC_1

#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)

0x00000020

◆ CAN_ESR_LEC_2

#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)

0x00000040

◆ CAN_ESR_LEC_Msk

#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)

0x00000070

◆ CAN_ESR_REC

#define CAN_ESR_REC CAN_ESR_REC_Msk

Receive Error Counter

◆ CAN_ESR_REC_Msk

#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)

0xFF000000

◆ CAN_ESR_TEC

#define CAN_ESR_TEC CAN_ESR_TEC_Msk

Least significant byte of the 9-bit Transmit Error Counter

◆ CAN_ESR_TEC_Msk

#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)

0x00FF0000

◆ CAN_F0R1_FB0

#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk

Filter bit 0

◆ CAN_F0R1_FB0_Msk

#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)

0x00000001

◆ CAN_F0R1_FB1

#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk

Filter bit 1

◆ CAN_F0R1_FB10

#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk

Filter bit 10

◆ CAN_F0R1_FB10_Msk

#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)

0x00000400

◆ CAN_F0R1_FB11

#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk

Filter bit 11

◆ CAN_F0R1_FB11_Msk

#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)

0x00000800

◆ CAN_F0R1_FB12

#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk

Filter bit 12

◆ CAN_F0R1_FB12_Msk

#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)

0x00001000

◆ CAN_F0R1_FB13

#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk

Filter bit 13

◆ CAN_F0R1_FB13_Msk

#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)

0x00002000

◆ CAN_F0R1_FB14

#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk

Filter bit 14

◆ CAN_F0R1_FB14_Msk

#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)

0x00004000

◆ CAN_F0R1_FB15

#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk

Filter bit 15

◆ CAN_F0R1_FB15_Msk

#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)

0x00008000

◆ CAN_F0R1_FB16

#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk

Filter bit 16

◆ CAN_F0R1_FB16_Msk

#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)

0x00010000

◆ CAN_F0R1_FB17

#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk

Filter bit 17

◆ CAN_F0R1_FB17_Msk

#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)

0x00020000

◆ CAN_F0R1_FB18

#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk

Filter bit 18

◆ CAN_F0R1_FB18_Msk

#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)

0x00040000

◆ CAN_F0R1_FB19

#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk

Filter bit 19

◆ CAN_F0R1_FB19_Msk

#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)

0x00080000

◆ CAN_F0R1_FB1_Msk

#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)

0x00000002

◆ CAN_F0R1_FB2

#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk

Filter bit 2

◆ CAN_F0R1_FB20

#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk

Filter bit 20

◆ CAN_F0R1_FB20_Msk

#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)

0x00100000

◆ CAN_F0R1_FB21

#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk

Filter bit 21

◆ CAN_F0R1_FB21_Msk

#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)

0x00200000

◆ CAN_F0R1_FB22

#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk

Filter bit 22

◆ CAN_F0R1_FB22_Msk

#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)

0x00400000

◆ CAN_F0R1_FB23

#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk

Filter bit 23

◆ CAN_F0R1_FB23_Msk

#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)

0x00800000

◆ CAN_F0R1_FB24

#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk

Filter bit 24

◆ CAN_F0R1_FB24_Msk

#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)

0x01000000

◆ CAN_F0R1_FB25

#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk

Filter bit 25

◆ CAN_F0R1_FB25_Msk

#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)

0x02000000

◆ CAN_F0R1_FB26

#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk

Filter bit 26

◆ CAN_F0R1_FB26_Msk

#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)

0x04000000

◆ CAN_F0R1_FB27

#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk

Filter bit 27

◆ CAN_F0R1_FB27_Msk

#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)

0x08000000

◆ CAN_F0R1_FB28

#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk

Filter bit 28

◆ CAN_F0R1_FB28_Msk

#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)

0x10000000

◆ CAN_F0R1_FB29

#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk

Filter bit 29

◆ CAN_F0R1_FB29_Msk

#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)

0x20000000

◆ CAN_F0R1_FB2_Msk

#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)

0x00000004

◆ CAN_F0R1_FB3

#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk

Filter bit 3

◆ CAN_F0R1_FB30

#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk

Filter bit 30

◆ CAN_F0R1_FB30_Msk

#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)

0x40000000

◆ CAN_F0R1_FB31

#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk

Filter bit 31

◆ CAN_F0R1_FB31_Msk

#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)

0x80000000

◆ CAN_F0R1_FB3_Msk

#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)

0x00000008

◆ CAN_F0R1_FB4

#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk

Filter bit 4

◆ CAN_F0R1_FB4_Msk

#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)

0x00000010

◆ CAN_F0R1_FB5

#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk

Filter bit 5

◆ CAN_F0R1_FB5_Msk

#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)

0x00000020

◆ CAN_F0R1_FB6

#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk

Filter bit 6

◆ CAN_F0R1_FB6_Msk

#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)

0x00000040

◆ CAN_F0R1_FB7

#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk

Filter bit 7

◆ CAN_F0R1_FB7_Msk

#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)

0x00000080

◆ CAN_F0R1_FB8

#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk

Filter bit 8

◆ CAN_F0R1_FB8_Msk

#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)

0x00000100

◆ CAN_F0R1_FB9

#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk

Filter bit 9

◆ CAN_F0R1_FB9_Msk

#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)

0x00000200

◆ CAN_F0R2_FB0

#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk

Filter bit 0

◆ CAN_F0R2_FB0_Msk

#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)

0x00000001

◆ CAN_F0R2_FB1

#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk

Filter bit 1

◆ CAN_F0R2_FB10

#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk

Filter bit 10

◆ CAN_F0R2_FB10_Msk

#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)

0x00000400

◆ CAN_F0R2_FB11

#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk

Filter bit 11

◆ CAN_F0R2_FB11_Msk

#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)

0x00000800

◆ CAN_F0R2_FB12

#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk

Filter bit 12

◆ CAN_F0R2_FB12_Msk

#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)

0x00001000

◆ CAN_F0R2_FB13

#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk

Filter bit 13

◆ CAN_F0R2_FB13_Msk

#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)

0x00002000

◆ CAN_F0R2_FB14

#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk

Filter bit 14

◆ CAN_F0R2_FB14_Msk

#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)

0x00004000

◆ CAN_F0R2_FB15

#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk

Filter bit 15

◆ CAN_F0R2_FB15_Msk

#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)

0x00008000

◆ CAN_F0R2_FB16

#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk

Filter bit 16

◆ CAN_F0R2_FB16_Msk

#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)

0x00010000

◆ CAN_F0R2_FB17

#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk

Filter bit 17

◆ CAN_F0R2_FB17_Msk

#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)

0x00020000

◆ CAN_F0R2_FB18

#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk

Filter bit 18

◆ CAN_F0R2_FB18_Msk

#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)

0x00040000

◆ CAN_F0R2_FB19

#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk

Filter bit 19

◆ CAN_F0R2_FB19_Msk

#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)

0x00080000

◆ CAN_F0R2_FB1_Msk

#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)

0x00000002

◆ CAN_F0R2_FB2

#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk

Filter bit 2

◆ CAN_F0R2_FB20

#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk

Filter bit 20

◆ CAN_F0R2_FB20_Msk

#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)

0x00100000

◆ CAN_F0R2_FB21

#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk

Filter bit 21

◆ CAN_F0R2_FB21_Msk

#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)

0x00200000

◆ CAN_F0R2_FB22

#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk

Filter bit 22

◆ CAN_F0R2_FB22_Msk

#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)

0x00400000

◆ CAN_F0R2_FB23

#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk

Filter bit 23

◆ CAN_F0R2_FB23_Msk

#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)

0x00800000

◆ CAN_F0R2_FB24

#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk

Filter bit 24

◆ CAN_F0R2_FB24_Msk

#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)

0x01000000

◆ CAN_F0R2_FB25

#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk

Filter bit 25

◆ CAN_F0R2_FB25_Msk

#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)

0x02000000

◆ CAN_F0R2_FB26

#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk

Filter bit 26

◆ CAN_F0R2_FB26_Msk

#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)

0x04000000

◆ CAN_F0R2_FB27

#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk

Filter bit 27

◆ CAN_F0R2_FB27_Msk

#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)

0x08000000

◆ CAN_F0R2_FB28

#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk

Filter bit 28

◆ CAN_F0R2_FB28_Msk

#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)

0x10000000

◆ CAN_F0R2_FB29

#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk

Filter bit 29

◆ CAN_F0R2_FB29_Msk

#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)

0x20000000

◆ CAN_F0R2_FB2_Msk

#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)

0x00000004

◆ CAN_F0R2_FB3

#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk

Filter bit 3

◆ CAN_F0R2_FB30

#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk

Filter bit 30

◆ CAN_F0R2_FB30_Msk

#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)

0x40000000

◆ CAN_F0R2_FB31

#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk

Filter bit 31

◆ CAN_F0R2_FB31_Msk

#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)

0x80000000

◆ CAN_F0R2_FB3_Msk

#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)

0x00000008

◆ CAN_F0R2_FB4

#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk

Filter bit 4

◆ CAN_F0R2_FB4_Msk

#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)

0x00000010

◆ CAN_F0R2_FB5

#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk

Filter bit 5

◆ CAN_F0R2_FB5_Msk

#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)

0x00000020

◆ CAN_F0R2_FB6

#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk

Filter bit 6

◆ CAN_F0R2_FB6_Msk

#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)

0x00000040

◆ CAN_F0R2_FB7

#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk

Filter bit 7

◆ CAN_F0R2_FB7_Msk

#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)

0x00000080

◆ CAN_F0R2_FB8

#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk

Filter bit 8

◆ CAN_F0R2_FB8_Msk

#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)

0x00000100

◆ CAN_F0R2_FB9

#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk

Filter bit 9

◆ CAN_F0R2_FB9_Msk

#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)

0x00000200

◆ CAN_F10R1_FB0

#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk

Filter bit 0

◆ CAN_F10R1_FB0_Msk

#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)

0x00000001

◆ CAN_F10R1_FB1

#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk

Filter bit 1

◆ CAN_F10R1_FB10

#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk

Filter bit 10

◆ CAN_F10R1_FB10_Msk

#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)

0x00000400

◆ CAN_F10R1_FB11

#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk

Filter bit 11

◆ CAN_F10R1_FB11_Msk

#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)

0x00000800

◆ CAN_F10R1_FB12

#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk

Filter bit 12

◆ CAN_F10R1_FB12_Msk

#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)

0x00001000

◆ CAN_F10R1_FB13

#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk

Filter bit 13

◆ CAN_F10R1_FB13_Msk

#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)

0x00002000

◆ CAN_F10R1_FB14

#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk

Filter bit 14

◆ CAN_F10R1_FB14_Msk

#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)

0x00004000

◆ CAN_F10R1_FB15

#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk

Filter bit 15

◆ CAN_F10R1_FB15_Msk

#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)

0x00008000

◆ CAN_F10R1_FB16

#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk

Filter bit 16

◆ CAN_F10R1_FB16_Msk

#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)

0x00010000

◆ CAN_F10R1_FB17

#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk

Filter bit 17

◆ CAN_F10R1_FB17_Msk

#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)

0x00020000

◆ CAN_F10R1_FB18

#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk

Filter bit 18

◆ CAN_F10R1_FB18_Msk

#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)

0x00040000

◆ CAN_F10R1_FB19

#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk

Filter bit 19

◆ CAN_F10R1_FB19_Msk

#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)

0x00080000

◆ CAN_F10R1_FB1_Msk

#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)

0x00000002

◆ CAN_F10R1_FB2

#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk

Filter bit 2

◆ CAN_F10R1_FB20

#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk

Filter bit 20

◆ CAN_F10R1_FB20_Msk

#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)

0x00100000

◆ CAN_F10R1_FB21

#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk

Filter bit 21

◆ CAN_F10R1_FB21_Msk

#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)

0x00200000

◆ CAN_F10R1_FB22

#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk

Filter bit 22

◆ CAN_F10R1_FB22_Msk

#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)

0x00400000

◆ CAN_F10R1_FB23

#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk

Filter bit 23

◆ CAN_F10R1_FB23_Msk

#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)

0x00800000

◆ CAN_F10R1_FB24

#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk

Filter bit 24

◆ CAN_F10R1_FB24_Msk

#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)

0x01000000

◆ CAN_F10R1_FB25

#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk

Filter bit 25

◆ CAN_F10R1_FB25_Msk

#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)

0x02000000

◆ CAN_F10R1_FB26

#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk

Filter bit 26

◆ CAN_F10R1_FB26_Msk

#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)

0x04000000

◆ CAN_F10R1_FB27

#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk

Filter bit 27

◆ CAN_F10R1_FB27_Msk

#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)

0x08000000

◆ CAN_F10R1_FB28

#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk

Filter bit 28

◆ CAN_F10R1_FB28_Msk

#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)

0x10000000

◆ CAN_F10R1_FB29

#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk

Filter bit 29

◆ CAN_F10R1_FB29_Msk

#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)

0x20000000

◆ CAN_F10R1_FB2_Msk

#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)

0x00000004

◆ CAN_F10R1_FB3

#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk

Filter bit 3

◆ CAN_F10R1_FB30

#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk

Filter bit 30

◆ CAN_F10R1_FB30_Msk

#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)

0x40000000

◆ CAN_F10R1_FB31

#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk

Filter bit 31

◆ CAN_F10R1_FB31_Msk

#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)

0x80000000

◆ CAN_F10R1_FB3_Msk

#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)

0x00000008

◆ CAN_F10R1_FB4

#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk

Filter bit 4

◆ CAN_F10R1_FB4_Msk

#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)

0x00000010

◆ CAN_F10R1_FB5

#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk

Filter bit 5

◆ CAN_F10R1_FB5_Msk

#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)

0x00000020

◆ CAN_F10R1_FB6

#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk

Filter bit 6

◆ CAN_F10R1_FB6_Msk

#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)

0x00000040

◆ CAN_F10R1_FB7

#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk

Filter bit 7

◆ CAN_F10R1_FB7_Msk

#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)

0x00000080

◆ CAN_F10R1_FB8

#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk

Filter bit 8

◆ CAN_F10R1_FB8_Msk

#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)

0x00000100

◆ CAN_F10R1_FB9

#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk

Filter bit 9

◆ CAN_F10R1_FB9_Msk

#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)

0x00000200

◆ CAN_F10R2_FB0

#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk

Filter bit 0

◆ CAN_F10R2_FB0_Msk

#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)

0x00000001

◆ CAN_F10R2_FB1

#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk

Filter bit 1

◆ CAN_F10R2_FB10

#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk

Filter bit 10

◆ CAN_F10R2_FB10_Msk

#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)

0x00000400

◆ CAN_F10R2_FB11

#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk

Filter bit 11

◆ CAN_F10R2_FB11_Msk

#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)

0x00000800

◆ CAN_F10R2_FB12

#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk

Filter bit 12

◆ CAN_F10R2_FB12_Msk

#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)

0x00001000

◆ CAN_F10R2_FB13

#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk

Filter bit 13

◆ CAN_F10R2_FB13_Msk

#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)

0x00002000

◆ CAN_F10R2_FB14

#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk

Filter bit 14

◆ CAN_F10R2_FB14_Msk

#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)

0x00004000

◆ CAN_F10R2_FB15

#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk

Filter bit 15

◆ CAN_F10R2_FB15_Msk

#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)

0x00008000

◆ CAN_F10R2_FB16

#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk

Filter bit 16

◆ CAN_F10R2_FB16_Msk

#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)

0x00010000

◆ CAN_F10R2_FB17

#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk

Filter bit 17

◆ CAN_F10R2_FB17_Msk

#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)

0x00020000

◆ CAN_F10R2_FB18

#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk

Filter bit 18

◆ CAN_F10R2_FB18_Msk

#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)

0x00040000

◆ CAN_F10R2_FB19

#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk

Filter bit 19

◆ CAN_F10R2_FB19_Msk

#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)

0x00080000

◆ CAN_F10R2_FB1_Msk

#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)

0x00000002

◆ CAN_F10R2_FB2

#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk

Filter bit 2

◆ CAN_F10R2_FB20

#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk

Filter bit 20

◆ CAN_F10R2_FB20_Msk

#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)

0x00100000

◆ CAN_F10R2_FB21

#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk

Filter bit 21

◆ CAN_F10R2_FB21_Msk

#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)

0x00200000

◆ CAN_F10R2_FB22

#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk

Filter bit 22

◆ CAN_F10R2_FB22_Msk

#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)

0x00400000

◆ CAN_F10R2_FB23

#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk

Filter bit 23

◆ CAN_F10R2_FB23_Msk

#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)

0x00800000

◆ CAN_F10R2_FB24

#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk

Filter bit 24

◆ CAN_F10R2_FB24_Msk

#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)

0x01000000

◆ CAN_F10R2_FB25

#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk

Filter bit 25

◆ CAN_F10R2_FB25_Msk

#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)

0x02000000

◆ CAN_F10R2_FB26

#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk

Filter bit 26

◆ CAN_F10R2_FB26_Msk

#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)

0x04000000

◆ CAN_F10R2_FB27

#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk

Filter bit 27

◆ CAN_F10R2_FB27_Msk

#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)

0x08000000

◆ CAN_F10R2_FB28

#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk

Filter bit 28

◆ CAN_F10R2_FB28_Msk

#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)

0x10000000

◆ CAN_F10R2_FB29

#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk

Filter bit 29

◆ CAN_F10R2_FB29_Msk

#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)

0x20000000

◆ CAN_F10R2_FB2_Msk

#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)

0x00000004

◆ CAN_F10R2_FB3

#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk

Filter bit 3

◆ CAN_F10R2_FB30

#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk

Filter bit 30

◆ CAN_F10R2_FB30_Msk

#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)

0x40000000

◆ CAN_F10R2_FB31

#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk

Filter bit 31

◆ CAN_F10R2_FB31_Msk

#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)

0x80000000

◆ CAN_F10R2_FB3_Msk

#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)

0x00000008

◆ CAN_F10R2_FB4

#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk

Filter bit 4

◆ CAN_F10R2_FB4_Msk

#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)

0x00000010

◆ CAN_F10R2_FB5

#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk

Filter bit 5

◆ CAN_F10R2_FB5_Msk

#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)

0x00000020

◆ CAN_F10R2_FB6

#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk

Filter bit 6

◆ CAN_F10R2_FB6_Msk

#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)

0x00000040

◆ CAN_F10R2_FB7

#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk

Filter bit 7

◆ CAN_F10R2_FB7_Msk

#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)

0x00000080

◆ CAN_F10R2_FB8

#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk

Filter bit 8

◆ CAN_F10R2_FB8_Msk

#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)

0x00000100

◆ CAN_F10R2_FB9

#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk

Filter bit 9

◆ CAN_F10R2_FB9_Msk

#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)

0x00000200

◆ CAN_F11R1_FB0

#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk

Filter bit 0

◆ CAN_F11R1_FB0_Msk

#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)

0x00000001

◆ CAN_F11R1_FB1

#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk

Filter bit 1

◆ CAN_F11R1_FB10

#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk

Filter bit 10

◆ CAN_F11R1_FB10_Msk

#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)

0x00000400

◆ CAN_F11R1_FB11

#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk

Filter bit 11

◆ CAN_F11R1_FB11_Msk

#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)

0x00000800

◆ CAN_F11R1_FB12

#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk

Filter bit 12

◆ CAN_F11R1_FB12_Msk

#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)

0x00001000

◆ CAN_F11R1_FB13

#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk

Filter bit 13

◆ CAN_F11R1_FB13_Msk

#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)

0x00002000

◆ CAN_F11R1_FB14

#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk

Filter bit 14

◆ CAN_F11R1_FB14_Msk

#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)

0x00004000

◆ CAN_F11R1_FB15

#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk

Filter bit 15

◆ CAN_F11R1_FB15_Msk

#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)

0x00008000

◆ CAN_F11R1_FB16

#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk

Filter bit 16

◆ CAN_F11R1_FB16_Msk

#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)

0x00010000

◆ CAN_F11R1_FB17

#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk

Filter bit 17

◆ CAN_F11R1_FB17_Msk

#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)

0x00020000

◆ CAN_F11R1_FB18

#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk

Filter bit 18

◆ CAN_F11R1_FB18_Msk

#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)

0x00040000

◆ CAN_F11R1_FB19

#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk

Filter bit 19

◆ CAN_F11R1_FB19_Msk

#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)

0x00080000

◆ CAN_F11R1_FB1_Msk

#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)

0x00000002

◆ CAN_F11R1_FB2

#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk

Filter bit 2

◆ CAN_F11R1_FB20

#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk

Filter bit 20

◆ CAN_F11R1_FB20_Msk

#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)

0x00100000

◆ CAN_F11R1_FB21

#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk

Filter bit 21

◆ CAN_F11R1_FB21_Msk

#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)

0x00200000

◆ CAN_F11R1_FB22

#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk

Filter bit 22

◆ CAN_F11R1_FB22_Msk

#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)

0x00400000

◆ CAN_F11R1_FB23

#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk

Filter bit 23

◆ CAN_F11R1_FB23_Msk

#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)

0x00800000

◆ CAN_F11R1_FB24

#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk

Filter bit 24

◆ CAN_F11R1_FB24_Msk

#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)

0x01000000

◆ CAN_F11R1_FB25

#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk

Filter bit 25

◆ CAN_F11R1_FB25_Msk

#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)

0x02000000

◆ CAN_F11R1_FB26

#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk

Filter bit 26

◆ CAN_F11R1_FB26_Msk

#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)

0x04000000

◆ CAN_F11R1_FB27

#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk

Filter bit 27

◆ CAN_F11R1_FB27_Msk

#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)

0x08000000

◆ CAN_F11R1_FB28

#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk

Filter bit 28

◆ CAN_F11R1_FB28_Msk

#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)

0x10000000

◆ CAN_F11R1_FB29

#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk

Filter bit 29

◆ CAN_F11R1_FB29_Msk

#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)

0x20000000

◆ CAN_F11R1_FB2_Msk

#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)

0x00000004

◆ CAN_F11R1_FB3

#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk

Filter bit 3

◆ CAN_F11R1_FB30

#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk

Filter bit 30

◆ CAN_F11R1_FB30_Msk

#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)

0x40000000

◆ CAN_F11R1_FB31

#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk

Filter bit 31

◆ CAN_F11R1_FB31_Msk

#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)

0x80000000

◆ CAN_F11R1_FB3_Msk

#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)

0x00000008

◆ CAN_F11R1_FB4

#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk

Filter bit 4

◆ CAN_F11R1_FB4_Msk

#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)

0x00000010

◆ CAN_F11R1_FB5

#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk

Filter bit 5

◆ CAN_F11R1_FB5_Msk

#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)

0x00000020

◆ CAN_F11R1_FB6

#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk

Filter bit 6

◆ CAN_F11R1_FB6_Msk

#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)

0x00000040

◆ CAN_F11R1_FB7

#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk

Filter bit 7

◆ CAN_F11R1_FB7_Msk

#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)

0x00000080

◆ CAN_F11R1_FB8

#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk

Filter bit 8

◆ CAN_F11R1_FB8_Msk

#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)

0x00000100

◆ CAN_F11R1_FB9

#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk

Filter bit 9

◆ CAN_F11R1_FB9_Msk

#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)

0x00000200

◆ CAN_F11R2_FB0

#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk

Filter bit 0

◆ CAN_F11R2_FB0_Msk

#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)

0x00000001

◆ CAN_F11R2_FB1

#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk

Filter bit 1

◆ CAN_F11R2_FB10

#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk

Filter bit 10

◆ CAN_F11R2_FB10_Msk

#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)

0x00000400

◆ CAN_F11R2_FB11

#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk

Filter bit 11

◆ CAN_F11R2_FB11_Msk

#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)

0x00000800

◆ CAN_F11R2_FB12

#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk

Filter bit 12

◆ CAN_F11R2_FB12_Msk

#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)

0x00001000

◆ CAN_F11R2_FB13

#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk

Filter bit 13

◆ CAN_F11R2_FB13_Msk

#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)

0x00002000

◆ CAN_F11R2_FB14

#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk

Filter bit 14

◆ CAN_F11R2_FB14_Msk

#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)

0x00004000

◆ CAN_F11R2_FB15

#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk

Filter bit 15

◆ CAN_F11R2_FB15_Msk

#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)

0x00008000

◆ CAN_F11R2_FB16

#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk

Filter bit 16

◆ CAN_F11R2_FB16_Msk

#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)

0x00010000

◆ CAN_F11R2_FB17

#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk

Filter bit 17

◆ CAN_F11R2_FB17_Msk

#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)

0x00020000

◆ CAN_F11R2_FB18

#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk

Filter bit 18

◆ CAN_F11R2_FB18_Msk

#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)

0x00040000

◆ CAN_F11R2_FB19

#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk

Filter bit 19

◆ CAN_F11R2_FB19_Msk

#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)

0x00080000

◆ CAN_F11R2_FB1_Msk

#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)

0x00000002

◆ CAN_F11R2_FB2

#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk

Filter bit 2

◆ CAN_F11R2_FB20

#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk

Filter bit 20

◆ CAN_F11R2_FB20_Msk

#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)

0x00100000

◆ CAN_F11R2_FB21

#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk

Filter bit 21

◆ CAN_F11R2_FB21_Msk

#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)

0x00200000

◆ CAN_F11R2_FB22

#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk

Filter bit 22

◆ CAN_F11R2_FB22_Msk

#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)

0x00400000

◆ CAN_F11R2_FB23

#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk

Filter bit 23

◆ CAN_F11R2_FB23_Msk

#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)

0x00800000

◆ CAN_F11R2_FB24

#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk

Filter bit 24

◆ CAN_F11R2_FB24_Msk

#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)

0x01000000

◆ CAN_F11R2_FB25

#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk

Filter bit 25

◆ CAN_F11R2_FB25_Msk

#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)

0x02000000

◆ CAN_F11R2_FB26

#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk

Filter bit 26

◆ CAN_F11R2_FB26_Msk

#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)

0x04000000

◆ CAN_F11R2_FB27

#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk

Filter bit 27

◆ CAN_F11R2_FB27_Msk

#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)

0x08000000

◆ CAN_F11R2_FB28

#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk

Filter bit 28

◆ CAN_F11R2_FB28_Msk

#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)

0x10000000

◆ CAN_F11R2_FB29

#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk

Filter bit 29

◆ CAN_F11R2_FB29_Msk

#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)

0x20000000

◆ CAN_F11R2_FB2_Msk

#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)

0x00000004

◆ CAN_F11R2_FB3

#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk

Filter bit 3

◆ CAN_F11R2_FB30

#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk

Filter bit 30

◆ CAN_F11R2_FB30_Msk

#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)

0x40000000

◆ CAN_F11R2_FB31

#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk

Filter bit 31

◆ CAN_F11R2_FB31_Msk

#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)

0x80000000

◆ CAN_F11R2_FB3_Msk

#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)

0x00000008

◆ CAN_F11R2_FB4

#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk

Filter bit 4

◆ CAN_F11R2_FB4_Msk

#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)

0x00000010

◆ CAN_F11R2_FB5

#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk

Filter bit 5

◆ CAN_F11R2_FB5_Msk

#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)

0x00000020

◆ CAN_F11R2_FB6

#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk

Filter bit 6

◆ CAN_F11R2_FB6_Msk

#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)

0x00000040

◆ CAN_F11R2_FB7

#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk

Filter bit 7

◆ CAN_F11R2_FB7_Msk

#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)

0x00000080

◆ CAN_F11R2_FB8

#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk

Filter bit 8

◆ CAN_F11R2_FB8_Msk

#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)

0x00000100

◆ CAN_F11R2_FB9

#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk

Filter bit 9

◆ CAN_F11R2_FB9_Msk

#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)

0x00000200

◆ CAN_F12R1_FB0

#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk

Filter bit 0

◆ CAN_F12R1_FB0_Msk

#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)

0x00000001

◆ CAN_F12R1_FB1

#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk

Filter bit 1

◆ CAN_F12R1_FB10

#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk

Filter bit 10

◆ CAN_F12R1_FB10_Msk

#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)

0x00000400

◆ CAN_F12R1_FB11

#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk

Filter bit 11

◆ CAN_F12R1_FB11_Msk

#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)

0x00000800

◆ CAN_F12R1_FB12

#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk

Filter bit 12

◆ CAN_F12R1_FB12_Msk

#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)

0x00001000

◆ CAN_F12R1_FB13

#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk

Filter bit 13

◆ CAN_F12R1_FB13_Msk

#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)

0x00002000

◆ CAN_F12R1_FB14

#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk

Filter bit 14

◆ CAN_F12R1_FB14_Msk

#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)

0x00004000

◆ CAN_F12R1_FB15

#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk

Filter bit 15

◆ CAN_F12R1_FB15_Msk

#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)

0x00008000

◆ CAN_F12R1_FB16

#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk

Filter bit 16

◆ CAN_F12R1_FB16_Msk

#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)

0x00010000

◆ CAN_F12R1_FB17

#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk

Filter bit 17

◆ CAN_F12R1_FB17_Msk

#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)

0x00020000

◆ CAN_F12R1_FB18

#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk

Filter bit 18

◆ CAN_F12R1_FB18_Msk

#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)

0x00040000

◆ CAN_F12R1_FB19

#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk

Filter bit 19

◆ CAN_F12R1_FB19_Msk

#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)

0x00080000

◆ CAN_F12R1_FB1_Msk

#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)

0x00000002

◆ CAN_F12R1_FB2

#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk

Filter bit 2

◆ CAN_F12R1_FB20

#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk

Filter bit 20

◆ CAN_F12R1_FB20_Msk

#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)

0x00100000

◆ CAN_F12R1_FB21

#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk

Filter bit 21

◆ CAN_F12R1_FB21_Msk

#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)

0x00200000

◆ CAN_F12R1_FB22

#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk

Filter bit 22

◆ CAN_F12R1_FB22_Msk

#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)

0x00400000

◆ CAN_F12R1_FB23

#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk

Filter bit 23

◆ CAN_F12R1_FB23_Msk

#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)

0x00800000

◆ CAN_F12R1_FB24

#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk

Filter bit 24

◆ CAN_F12R1_FB24_Msk

#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)

0x01000000

◆ CAN_F12R1_FB25

#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk

Filter bit 25

◆ CAN_F12R1_FB25_Msk

#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)

0x02000000

◆ CAN_F12R1_FB26

#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk

Filter bit 26

◆ CAN_F12R1_FB26_Msk

#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)

0x04000000

◆ CAN_F12R1_FB27

#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk

Filter bit 27

◆ CAN_F12R1_FB27_Msk

#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)

0x08000000

◆ CAN_F12R1_FB28

#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk

Filter bit 28

◆ CAN_F12R1_FB28_Msk

#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)

0x10000000

◆ CAN_F12R1_FB29

#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk

Filter bit 29

◆ CAN_F12R1_FB29_Msk

#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)

0x20000000

◆ CAN_F12R1_FB2_Msk

#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)

0x00000004

◆ CAN_F12R1_FB3

#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk

Filter bit 3

◆ CAN_F12R1_FB30

#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk

Filter bit 30

◆ CAN_F12R1_FB30_Msk

#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)

0x40000000

◆ CAN_F12R1_FB31

#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk

Filter bit 31

◆ CAN_F12R1_FB31_Msk

#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)

0x80000000

◆ CAN_F12R1_FB3_Msk

#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)

0x00000008

◆ CAN_F12R1_FB4

#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk

Filter bit 4

◆ CAN_F12R1_FB4_Msk

#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)

0x00000010

◆ CAN_F12R1_FB5

#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk

Filter bit 5

◆ CAN_F12R1_FB5_Msk

#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)

0x00000020

◆ CAN_F12R1_FB6

#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk

Filter bit 6

◆ CAN_F12R1_FB6_Msk

#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)

0x00000040

◆ CAN_F12R1_FB7

#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk

Filter bit 7

◆ CAN_F12R1_FB7_Msk

#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)

0x00000080

◆ CAN_F12R1_FB8

#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk

Filter bit 8

◆ CAN_F12R1_FB8_Msk

#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)

0x00000100

◆ CAN_F12R1_FB9

#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk

Filter bit 9

◆ CAN_F12R1_FB9_Msk

#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)

0x00000200

◆ CAN_F12R2_FB0

#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk

Filter bit 0

◆ CAN_F12R2_FB0_Msk

#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)

0x00000001

◆ CAN_F12R2_FB1

#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk

Filter bit 1

◆ CAN_F12R2_FB10

#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk

Filter bit 10

◆ CAN_F12R2_FB10_Msk

#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)

0x00000400

◆ CAN_F12R2_FB11

#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk

Filter bit 11

◆ CAN_F12R2_FB11_Msk

#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)

0x00000800

◆ CAN_F12R2_FB12

#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk

Filter bit 12

◆ CAN_F12R2_FB12_Msk

#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)

0x00001000

◆ CAN_F12R2_FB13

#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk

Filter bit 13

◆ CAN_F12R2_FB13_Msk

#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)

0x00002000

◆ CAN_F12R2_FB14

#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk

Filter bit 14

◆ CAN_F12R2_FB14_Msk

#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)

0x00004000

◆ CAN_F12R2_FB15

#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk

Filter bit 15

◆ CAN_F12R2_FB15_Msk

#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)

0x00008000

◆ CAN_F12R2_FB16

#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk

Filter bit 16

◆ CAN_F12R2_FB16_Msk

#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)

0x00010000

◆ CAN_F12R2_FB17

#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk

Filter bit 17

◆ CAN_F12R2_FB17_Msk

#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)

0x00020000

◆ CAN_F12R2_FB18

#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk

Filter bit 18

◆ CAN_F12R2_FB18_Msk

#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)

0x00040000

◆ CAN_F12R2_FB19

#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk

Filter bit 19

◆ CAN_F12R2_FB19_Msk

#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)

0x00080000

◆ CAN_F12R2_FB1_Msk

#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)

0x00000002

◆ CAN_F12R2_FB2

#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk

Filter bit 2

◆ CAN_F12R2_FB20

#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk

Filter bit 20

◆ CAN_F12R2_FB20_Msk

#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)

0x00100000

◆ CAN_F12R2_FB21

#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk

Filter bit 21

◆ CAN_F12R2_FB21_Msk

#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)

0x00200000

◆ CAN_F12R2_FB22

#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk

Filter bit 22

◆ CAN_F12R2_FB22_Msk

#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)

0x00400000

◆ CAN_F12R2_FB23

#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk

Filter bit 23

◆ CAN_F12R2_FB23_Msk

#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)

0x00800000

◆ CAN_F12R2_FB24

#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk

Filter bit 24

◆ CAN_F12R2_FB24_Msk

#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)

0x01000000

◆ CAN_F12R2_FB25

#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk

Filter bit 25

◆ CAN_F12R2_FB25_Msk

#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)

0x02000000

◆ CAN_F12R2_FB26

#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk

Filter bit 26

◆ CAN_F12R2_FB26_Msk

#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)

0x04000000

◆ CAN_F12R2_FB27

#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk

Filter bit 27

◆ CAN_F12R2_FB27_Msk

#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)

0x08000000

◆ CAN_F12R2_FB28

#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk

Filter bit 28

◆ CAN_F12R2_FB28_Msk

#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)

0x10000000

◆ CAN_F12R2_FB29

#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk

Filter bit 29

◆ CAN_F12R2_FB29_Msk

#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)

0x20000000

◆ CAN_F12R2_FB2_Msk

#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)

0x00000004

◆ CAN_F12R2_FB3

#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk

Filter bit 3

◆ CAN_F12R2_FB30

#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk

Filter bit 30

◆ CAN_F12R2_FB30_Msk

#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)

0x40000000

◆ CAN_F12R2_FB31

#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk

Filter bit 31

◆ CAN_F12R2_FB31_Msk

#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)

0x80000000

◆ CAN_F12R2_FB3_Msk

#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)

0x00000008

◆ CAN_F12R2_FB4

#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk

Filter bit 4

◆ CAN_F12R2_FB4_Msk

#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)

0x00000010

◆ CAN_F12R2_FB5

#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk

Filter bit 5

◆ CAN_F12R2_FB5_Msk

#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)

0x00000020

◆ CAN_F12R2_FB6

#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk

Filter bit 6

◆ CAN_F12R2_FB6_Msk

#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)

0x00000040

◆ CAN_F12R2_FB7

#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk

Filter bit 7

◆ CAN_F12R2_FB7_Msk

#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)

0x00000080

◆ CAN_F12R2_FB8

#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk

Filter bit 8

◆ CAN_F12R2_FB8_Msk

#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)

0x00000100

◆ CAN_F12R2_FB9

#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk

Filter bit 9

◆ CAN_F12R2_FB9_Msk

#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)

0x00000200

◆ CAN_F13R1_FB0

#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk

Filter bit 0

◆ CAN_F13R1_FB0_Msk

#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)

0x00000001

◆ CAN_F13R1_FB1

#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk

Filter bit 1

◆ CAN_F13R1_FB10

#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk

Filter bit 10

◆ CAN_F13R1_FB10_Msk

#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)

0x00000400

◆ CAN_F13R1_FB11

#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk

Filter bit 11

◆ CAN_F13R1_FB11_Msk

#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)

0x00000800

◆ CAN_F13R1_FB12

#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk

Filter bit 12

◆ CAN_F13R1_FB12_Msk

#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)

0x00001000

◆ CAN_F13R1_FB13

#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk

Filter bit 13

◆ CAN_F13R1_FB13_Msk

#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)

0x00002000

◆ CAN_F13R1_FB14

#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk

Filter bit 14

◆ CAN_F13R1_FB14_Msk

#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)

0x00004000

◆ CAN_F13R1_FB15

#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk

Filter bit 15

◆ CAN_F13R1_FB15_Msk

#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)

0x00008000

◆ CAN_F13R1_FB16

#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk

Filter bit 16

◆ CAN_F13R1_FB16_Msk

#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)

0x00010000

◆ CAN_F13R1_FB17

#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk

Filter bit 17

◆ CAN_F13R1_FB17_Msk

#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)

0x00020000

◆ CAN_F13R1_FB18

#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk

Filter bit 18

◆ CAN_F13R1_FB18_Msk

#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)

0x00040000

◆ CAN_F13R1_FB19

#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk

Filter bit 19

◆ CAN_F13R1_FB19_Msk

#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)

0x00080000

◆ CAN_F13R1_FB1_Msk

#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)

0x00000002

◆ CAN_F13R1_FB2

#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk

Filter bit 2

◆ CAN_F13R1_FB20

#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk

Filter bit 20

◆ CAN_F13R1_FB20_Msk

#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)

0x00100000

◆ CAN_F13R1_FB21

#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk

Filter bit 21

◆ CAN_F13R1_FB21_Msk

#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)

0x00200000

◆ CAN_F13R1_FB22

#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk

Filter bit 22

◆ CAN_F13R1_FB22_Msk

#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)

0x00400000

◆ CAN_F13R1_FB23

#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk

Filter bit 23

◆ CAN_F13R1_FB23_Msk

#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)

0x00800000

◆ CAN_F13R1_FB24

#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk

Filter bit 24

◆ CAN_F13R1_FB24_Msk

#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)

0x01000000

◆ CAN_F13R1_FB25

#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk

Filter bit 25

◆ CAN_F13R1_FB25_Msk

#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)

0x02000000

◆ CAN_F13R1_FB26

#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk

Filter bit 26

◆ CAN_F13R1_FB26_Msk

#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)

0x04000000

◆ CAN_F13R1_FB27

#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk

Filter bit 27

◆ CAN_F13R1_FB27_Msk

#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)

0x08000000

◆ CAN_F13R1_FB28

#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk

Filter bit 28

◆ CAN_F13R1_FB28_Msk

#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)

0x10000000

◆ CAN_F13R1_FB29

#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk

Filter bit 29

◆ CAN_F13R1_FB29_Msk

#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)

0x20000000

◆ CAN_F13R1_FB2_Msk

#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)

0x00000004

◆ CAN_F13R1_FB3

#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk

Filter bit 3

◆ CAN_F13R1_FB30

#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk

Filter bit 30

◆ CAN_F13R1_FB30_Msk

#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)

0x40000000

◆ CAN_F13R1_FB31

#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk

Filter bit 31

◆ CAN_F13R1_FB31_Msk

#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)

0x80000000

◆ CAN_F13R1_FB3_Msk

#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)

0x00000008

◆ CAN_F13R1_FB4

#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk

Filter bit 4

◆ CAN_F13R1_FB4_Msk

#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)

0x00000010

◆ CAN_F13R1_FB5

#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk

Filter bit 5

◆ CAN_F13R1_FB5_Msk

#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)

0x00000020

◆ CAN_F13R1_FB6

#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk

Filter bit 6

◆ CAN_F13R1_FB6_Msk

#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)

0x00000040

◆ CAN_F13R1_FB7

#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk

Filter bit 7

◆ CAN_F13R1_FB7_Msk

#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)

0x00000080

◆ CAN_F13R1_FB8

#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk

Filter bit 8

◆ CAN_F13R1_FB8_Msk

#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)

0x00000100

◆ CAN_F13R1_FB9

#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk

Filter bit 9

◆ CAN_F13R1_FB9_Msk

#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)

0x00000200

◆ CAN_F13R2_FB0

#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk

Filter bit 0

◆ CAN_F13R2_FB0_Msk

#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)

0x00000001

◆ CAN_F13R2_FB1

#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk

Filter bit 1

◆ CAN_F13R2_FB10

#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk

Filter bit 10

◆ CAN_F13R2_FB10_Msk

#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)

0x00000400

◆ CAN_F13R2_FB11

#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk

Filter bit 11

◆ CAN_F13R2_FB11_Msk

#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)

0x00000800

◆ CAN_F13R2_FB12

#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk

Filter bit 12

◆ CAN_F13R2_FB12_Msk

#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)

0x00001000

◆ CAN_F13R2_FB13

#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk

Filter bit 13

◆ CAN_F13R2_FB13_Msk

#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)

0x00002000

◆ CAN_F13R2_FB14

#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk

Filter bit 14

◆ CAN_F13R2_FB14_Msk

#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)

0x00004000

◆ CAN_F13R2_FB15

#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk

Filter bit 15

◆ CAN_F13R2_FB15_Msk

#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)

0x00008000

◆ CAN_F13R2_FB16

#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk

Filter bit 16

◆ CAN_F13R2_FB16_Msk

#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)

0x00010000

◆ CAN_F13R2_FB17

#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk

Filter bit 17

◆ CAN_F13R2_FB17_Msk

#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)

0x00020000

◆ CAN_F13R2_FB18

#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk

Filter bit 18

◆ CAN_F13R2_FB18_Msk

#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)

0x00040000

◆ CAN_F13R2_FB19

#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk

Filter bit 19

◆ CAN_F13R2_FB19_Msk

#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)

0x00080000

◆ CAN_F13R2_FB1_Msk

#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)

0x00000002

◆ CAN_F13R2_FB2

#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk

Filter bit 2

◆ CAN_F13R2_FB20

#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk

Filter bit 20

◆ CAN_F13R2_FB20_Msk

#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)

0x00100000

◆ CAN_F13R2_FB21

#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk

Filter bit 21

◆ CAN_F13R2_FB21_Msk

#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)

0x00200000

◆ CAN_F13R2_FB22

#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk

Filter bit 22

◆ CAN_F13R2_FB22_Msk

#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)

0x00400000

◆ CAN_F13R2_FB23

#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk

Filter bit 23

◆ CAN_F13R2_FB23_Msk

#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)

0x00800000

◆ CAN_F13R2_FB24

#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk

Filter bit 24

◆ CAN_F13R2_FB24_Msk

#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)

0x01000000

◆ CAN_F13R2_FB25

#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk

Filter bit 25

◆ CAN_F13R2_FB25_Msk

#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)

0x02000000

◆ CAN_F13R2_FB26

#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk

Filter bit 26

◆ CAN_F13R2_FB26_Msk

#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)

0x04000000

◆ CAN_F13R2_FB27

#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk

Filter bit 27

◆ CAN_F13R2_FB27_Msk

#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)

0x08000000

◆ CAN_F13R2_FB28

#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk

Filter bit 28

◆ CAN_F13R2_FB28_Msk

#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)

0x10000000

◆ CAN_F13R2_FB29

#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk

Filter bit 29

◆ CAN_F13R2_FB29_Msk

#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)

0x20000000

◆ CAN_F13R2_FB2_Msk

#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)

0x00000004

◆ CAN_F13R2_FB3

#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk

Filter bit 3

◆ CAN_F13R2_FB30

#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk

Filter bit 30

◆ CAN_F13R2_FB30_Msk

#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)

0x40000000

◆ CAN_F13R2_FB31

#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk

Filter bit 31

◆ CAN_F13R2_FB31_Msk

#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)

0x80000000

◆ CAN_F13R2_FB3_Msk

#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)

0x00000008

◆ CAN_F13R2_FB4

#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk

Filter bit 4

◆ CAN_F13R2_FB4_Msk

#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)

0x00000010

◆ CAN_F13R2_FB5

#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk

Filter bit 5

◆ CAN_F13R2_FB5_Msk

#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)

0x00000020

◆ CAN_F13R2_FB6

#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk

Filter bit 6

◆ CAN_F13R2_FB6_Msk

#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)

0x00000040

◆ CAN_F13R2_FB7

#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk

Filter bit 7

◆ CAN_F13R2_FB7_Msk

#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)

0x00000080

◆ CAN_F13R2_FB8

#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk

Filter bit 8

◆ CAN_F13R2_FB8_Msk

#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)

0x00000100

◆ CAN_F13R2_FB9

#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk

Filter bit 9

◆ CAN_F13R2_FB9_Msk

#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)

0x00000200

◆ CAN_F1R1_FB0

#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk

Filter bit 0

◆ CAN_F1R1_FB0_Msk

#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)

0x00000001

◆ CAN_F1R1_FB1

#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk

Filter bit 1

◆ CAN_F1R1_FB10

#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk

Filter bit 10

◆ CAN_F1R1_FB10_Msk

#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)

0x00000400

◆ CAN_F1R1_FB11

#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk

Filter bit 11

◆ CAN_F1R1_FB11_Msk

#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)

0x00000800

◆ CAN_F1R1_FB12

#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk

Filter bit 12

◆ CAN_F1R1_FB12_Msk

#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)

0x00001000

◆ CAN_F1R1_FB13

#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk

Filter bit 13

◆ CAN_F1R1_FB13_Msk

#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)

0x00002000

◆ CAN_F1R1_FB14

#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk

Filter bit 14

◆ CAN_F1R1_FB14_Msk

#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)

0x00004000

◆ CAN_F1R1_FB15

#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk

Filter bit 15

◆ CAN_F1R1_FB15_Msk

#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)

0x00008000

◆ CAN_F1R1_FB16

#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk

Filter bit 16

◆ CAN_F1R1_FB16_Msk

#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)

0x00010000

◆ CAN_F1R1_FB17

#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk

Filter bit 17

◆ CAN_F1R1_FB17_Msk

#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)

0x00020000

◆ CAN_F1R1_FB18

#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk

Filter bit 18

◆ CAN_F1R1_FB18_Msk

#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)

0x00040000

◆ CAN_F1R1_FB19

#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk

Filter bit 19

◆ CAN_F1R1_FB19_Msk

#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)

0x00080000

◆ CAN_F1R1_FB1_Msk

#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)

0x00000002

◆ CAN_F1R1_FB2

#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk

Filter bit 2

◆ CAN_F1R1_FB20

#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk

Filter bit 20

◆ CAN_F1R1_FB20_Msk

#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)

0x00100000

◆ CAN_F1R1_FB21

#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk

Filter bit 21

◆ CAN_F1R1_FB21_Msk

#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)

0x00200000

◆ CAN_F1R1_FB22

#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk

Filter bit 22

◆ CAN_F1R1_FB22_Msk

#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)

0x00400000

◆ CAN_F1R1_FB23

#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk

Filter bit 23

◆ CAN_F1R1_FB23_Msk

#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)

0x00800000

◆ CAN_F1R1_FB24

#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk

Filter bit 24

◆ CAN_F1R1_FB24_Msk

#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)

0x01000000

◆ CAN_F1R1_FB25

#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk

Filter bit 25

◆ CAN_F1R1_FB25_Msk

#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)

0x02000000

◆ CAN_F1R1_FB26

#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk

Filter bit 26

◆ CAN_F1R1_FB26_Msk

#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)

0x04000000

◆ CAN_F1R1_FB27

#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk

Filter bit 27

◆ CAN_F1R1_FB27_Msk

#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)

0x08000000

◆ CAN_F1R1_FB28

#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk

Filter bit 28

◆ CAN_F1R1_FB28_Msk

#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)

0x10000000

◆ CAN_F1R1_FB29

#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk

Filter bit 29

◆ CAN_F1R1_FB29_Msk

#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)

0x20000000

◆ CAN_F1R1_FB2_Msk

#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)

0x00000004

◆ CAN_F1R1_FB3

#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk

Filter bit 3

◆ CAN_F1R1_FB30

#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk

Filter bit 30

◆ CAN_F1R1_FB30_Msk

#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)

0x40000000

◆ CAN_F1R1_FB31

#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk

Filter bit 31

◆ CAN_F1R1_FB31_Msk

#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)

0x80000000

◆ CAN_F1R1_FB3_Msk

#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)

0x00000008

◆ CAN_F1R1_FB4

#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk

Filter bit 4

◆ CAN_F1R1_FB4_Msk

#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)

0x00000010

◆ CAN_F1R1_FB5

#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk

Filter bit 5

◆ CAN_F1R1_FB5_Msk

#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)

0x00000020

◆ CAN_F1R1_FB6

#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk

Filter bit 6

◆ CAN_F1R1_FB6_Msk

#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)

0x00000040

◆ CAN_F1R1_FB7

#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk

Filter bit 7

◆ CAN_F1R1_FB7_Msk

#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)

0x00000080

◆ CAN_F1R1_FB8

#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk

Filter bit 8

◆ CAN_F1R1_FB8_Msk

#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)

0x00000100

◆ CAN_F1R1_FB9

#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk

Filter bit 9

◆ CAN_F1R1_FB9_Msk

#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)

0x00000200

◆ CAN_F1R2_FB0

#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk

Filter bit 0

◆ CAN_F1R2_FB0_Msk

#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)

0x00000001

◆ CAN_F1R2_FB1

#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk

Filter bit 1

◆ CAN_F1R2_FB10

#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk

Filter bit 10

◆ CAN_F1R2_FB10_Msk

#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)

0x00000400

◆ CAN_F1R2_FB11

#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk

Filter bit 11

◆ CAN_F1R2_FB11_Msk

#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)

0x00000800

◆ CAN_F1R2_FB12

#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk

Filter bit 12

◆ CAN_F1R2_FB12_Msk

#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)

0x00001000

◆ CAN_F1R2_FB13

#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk

Filter bit 13

◆ CAN_F1R2_FB13_Msk

#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)

0x00002000

◆ CAN_F1R2_FB14

#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk

Filter bit 14

◆ CAN_F1R2_FB14_Msk

#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)

0x00004000

◆ CAN_F1R2_FB15

#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk

Filter bit 15

◆ CAN_F1R2_FB15_Msk

#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)

0x00008000

◆ CAN_F1R2_FB16

#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk

Filter bit 16

◆ CAN_F1R2_FB16_Msk

#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)

0x00010000

◆ CAN_F1R2_FB17

#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk

Filter bit 17

◆ CAN_F1R2_FB17_Msk

#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)

0x00020000

◆ CAN_F1R2_FB18

#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk

Filter bit 18

◆ CAN_F1R2_FB18_Msk

#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)

0x00040000

◆ CAN_F1R2_FB19

#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk

Filter bit 19

◆ CAN_F1R2_FB19_Msk

#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)

0x00080000

◆ CAN_F1R2_FB1_Msk

#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)

0x00000002

◆ CAN_F1R2_FB2

#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk

Filter bit 2

◆ CAN_F1R2_FB20

#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk

Filter bit 20

◆ CAN_F1R2_FB20_Msk

#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)

0x00100000

◆ CAN_F1R2_FB21

#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk

Filter bit 21

◆ CAN_F1R2_FB21_Msk

#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)

0x00200000

◆ CAN_F1R2_FB22

#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk

Filter bit 22

◆ CAN_F1R2_FB22_Msk

#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)

0x00400000

◆ CAN_F1R2_FB23

#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk

Filter bit 23

◆ CAN_F1R2_FB23_Msk

#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)

0x00800000

◆ CAN_F1R2_FB24

#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk

Filter bit 24

◆ CAN_F1R2_FB24_Msk

#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)

0x01000000

◆ CAN_F1R2_FB25

#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk

Filter bit 25

◆ CAN_F1R2_FB25_Msk

#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)

0x02000000

◆ CAN_F1R2_FB26

#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk

Filter bit 26

◆ CAN_F1R2_FB26_Msk

#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)

0x04000000

◆ CAN_F1R2_FB27

#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk

Filter bit 27

◆ CAN_F1R2_FB27_Msk

#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)

0x08000000

◆ CAN_F1R2_FB28

#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk

Filter bit 28

◆ CAN_F1R2_FB28_Msk

#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)

0x10000000

◆ CAN_F1R2_FB29

#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk

Filter bit 29

◆ CAN_F1R2_FB29_Msk

#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)

0x20000000

◆ CAN_F1R2_FB2_Msk

#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)

0x00000004

◆ CAN_F1R2_FB3

#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk

Filter bit 3

◆ CAN_F1R2_FB30

#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk

Filter bit 30

◆ CAN_F1R2_FB30_Msk

#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)

0x40000000

◆ CAN_F1R2_FB31

#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk

Filter bit 31

◆ CAN_F1R2_FB31_Msk

#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)

0x80000000

◆ CAN_F1R2_FB3_Msk

#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)

0x00000008

◆ CAN_F1R2_FB4

#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk

Filter bit 4

◆ CAN_F1R2_FB4_Msk

#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)

0x00000010

◆ CAN_F1R2_FB5

#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk

Filter bit 5

◆ CAN_F1R2_FB5_Msk

#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)

0x00000020

◆ CAN_F1R2_FB6

#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk

Filter bit 6

◆ CAN_F1R2_FB6_Msk

#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)

0x00000040

◆ CAN_F1R2_FB7

#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk

Filter bit 7

◆ CAN_F1R2_FB7_Msk

#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)

0x00000080

◆ CAN_F1R2_FB8

#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk

Filter bit 8

◆ CAN_F1R2_FB8_Msk

#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)

0x00000100

◆ CAN_F1R2_FB9

#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk

Filter bit 9

◆ CAN_F1R2_FB9_Msk

#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)

0x00000200

◆ CAN_F2R1_FB0

#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk

Filter bit 0

◆ CAN_F2R1_FB0_Msk

#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)

0x00000001

◆ CAN_F2R1_FB1

#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk

Filter bit 1

◆ CAN_F2R1_FB10

#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk

Filter bit 10

◆ CAN_F2R1_FB10_Msk

#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)

0x00000400

◆ CAN_F2R1_FB11

#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk

Filter bit 11

◆ CAN_F2R1_FB11_Msk

#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)

0x00000800

◆ CAN_F2R1_FB12

#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk

Filter bit 12

◆ CAN_F2R1_FB12_Msk

#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)

0x00001000

◆ CAN_F2R1_FB13

#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk

Filter bit 13

◆ CAN_F2R1_FB13_Msk

#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)

0x00002000

◆ CAN_F2R1_FB14

#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk

Filter bit 14

◆ CAN_F2R1_FB14_Msk

#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)

0x00004000

◆ CAN_F2R1_FB15

#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk

Filter bit 15

◆ CAN_F2R1_FB15_Msk

#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)

0x00008000

◆ CAN_F2R1_FB16

#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk

Filter bit 16

◆ CAN_F2R1_FB16_Msk

#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)

0x00010000

◆ CAN_F2R1_FB17

#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk

Filter bit 17

◆ CAN_F2R1_FB17_Msk

#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)

0x00020000

◆ CAN_F2R1_FB18

#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk

Filter bit 18

◆ CAN_F2R1_FB18_Msk

#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)

0x00040000

◆ CAN_F2R1_FB19

#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk

Filter bit 19

◆ CAN_F2R1_FB19_Msk

#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)

0x00080000

◆ CAN_F2R1_FB1_Msk

#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)

0x00000002

◆ CAN_F2R1_FB2

#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk

Filter bit 2

◆ CAN_F2R1_FB20

#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk

Filter bit 20

◆ CAN_F2R1_FB20_Msk

#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)

0x00100000

◆ CAN_F2R1_FB21

#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk

Filter bit 21

◆ CAN_F2R1_FB21_Msk

#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)

0x00200000

◆ CAN_F2R1_FB22

#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk

Filter bit 22

◆ CAN_F2R1_FB22_Msk

#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)

0x00400000

◆ CAN_F2R1_FB23

#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk

Filter bit 23

◆ CAN_F2R1_FB23_Msk

#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)

0x00800000

◆ CAN_F2R1_FB24

#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk

Filter bit 24

◆ CAN_F2R1_FB24_Msk

#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)

0x01000000

◆ CAN_F2R1_FB25

#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk

Filter bit 25

◆ CAN_F2R1_FB25_Msk

#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)

0x02000000

◆ CAN_F2R1_FB26

#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk

Filter bit 26

◆ CAN_F2R1_FB26_Msk

#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)

0x04000000

◆ CAN_F2R1_FB27

#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk

Filter bit 27

◆ CAN_F2R1_FB27_Msk

#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)

0x08000000

◆ CAN_F2R1_FB28

#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk

Filter bit 28

◆ CAN_F2R1_FB28_Msk

#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)

0x10000000

◆ CAN_F2R1_FB29

#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk

Filter bit 29

◆ CAN_F2R1_FB29_Msk

#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)

0x20000000

◆ CAN_F2R1_FB2_Msk

#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)

0x00000004

◆ CAN_F2R1_FB3

#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk

Filter bit 3

◆ CAN_F2R1_FB30

#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk

Filter bit 30

◆ CAN_F2R1_FB30_Msk

#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)

0x40000000

◆ CAN_F2R1_FB31

#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk

Filter bit 31

◆ CAN_F2R1_FB31_Msk

#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)

0x80000000

◆ CAN_F2R1_FB3_Msk

#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)

0x00000008

◆ CAN_F2R1_FB4

#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk

Filter bit 4

◆ CAN_F2R1_FB4_Msk

#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)

0x00000010

◆ CAN_F2R1_FB5

#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk

Filter bit 5

◆ CAN_F2R1_FB5_Msk

#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)

0x00000020

◆ CAN_F2R1_FB6

#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk

Filter bit 6

◆ CAN_F2R1_FB6_Msk

#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)

0x00000040

◆ CAN_F2R1_FB7

#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk

Filter bit 7

◆ CAN_F2R1_FB7_Msk

#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)

0x00000080

◆ CAN_F2R1_FB8

#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk

Filter bit 8

◆ CAN_F2R1_FB8_Msk

#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)

0x00000100

◆ CAN_F2R1_FB9

#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk

Filter bit 9

◆ CAN_F2R1_FB9_Msk

#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)

0x00000200

◆ CAN_F2R2_FB0

#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk

Filter bit 0

◆ CAN_F2R2_FB0_Msk

#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)

0x00000001

◆ CAN_F2R2_FB1

#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk

Filter bit 1

◆ CAN_F2R2_FB10

#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk

Filter bit 10

◆ CAN_F2R2_FB10_Msk

#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)

0x00000400

◆ CAN_F2R2_FB11

#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk

Filter bit 11

◆ CAN_F2R2_FB11_Msk

#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)

0x00000800

◆ CAN_F2R2_FB12

#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk

Filter bit 12

◆ CAN_F2R2_FB12_Msk

#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)

0x00001000

◆ CAN_F2R2_FB13

#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk

Filter bit 13

◆ CAN_F2R2_FB13_Msk

#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)

0x00002000

◆ CAN_F2R2_FB14

#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk

Filter bit 14

◆ CAN_F2R2_FB14_Msk

#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)

0x00004000

◆ CAN_F2R2_FB15

#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk

Filter bit 15

◆ CAN_F2R2_FB15_Msk

#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)

0x00008000

◆ CAN_F2R2_FB16

#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk

Filter bit 16

◆ CAN_F2R2_FB16_Msk

#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)

0x00010000

◆ CAN_F2R2_FB17

#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk

Filter bit 17

◆ CAN_F2R2_FB17_Msk

#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)

0x00020000

◆ CAN_F2R2_FB18

#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk

Filter bit 18

◆ CAN_F2R2_FB18_Msk

#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)

0x00040000

◆ CAN_F2R2_FB19

#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk

Filter bit 19

◆ CAN_F2R2_FB19_Msk

#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)

0x00080000

◆ CAN_F2R2_FB1_Msk

#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)

0x00000002

◆ CAN_F2R2_FB2

#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk

Filter bit 2

◆ CAN_F2R2_FB20

#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk

Filter bit 20

◆ CAN_F2R2_FB20_Msk

#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)

0x00100000

◆ CAN_F2R2_FB21

#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk

Filter bit 21

◆ CAN_F2R2_FB21_Msk

#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)

0x00200000

◆ CAN_F2R2_FB22

#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk

Filter bit 22

◆ CAN_F2R2_FB22_Msk

#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)

0x00400000

◆ CAN_F2R2_FB23

#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk

Filter bit 23

◆ CAN_F2R2_FB23_Msk

#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)

0x00800000

◆ CAN_F2R2_FB24

#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk

Filter bit 24

◆ CAN_F2R2_FB24_Msk

#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)

0x01000000

◆ CAN_F2R2_FB25

#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk

Filter bit 25

◆ CAN_F2R2_FB25_Msk

#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)

0x02000000

◆ CAN_F2R2_FB26

#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk

Filter bit 26

◆ CAN_F2R2_FB26_Msk

#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)

0x04000000

◆ CAN_F2R2_FB27

#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk

Filter bit 27

◆ CAN_F2R2_FB27_Msk

#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)

0x08000000

◆ CAN_F2R2_FB28

#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk

Filter bit 28

◆ CAN_F2R2_FB28_Msk

#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)

0x10000000

◆ CAN_F2R2_FB29

#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk

Filter bit 29

◆ CAN_F2R2_FB29_Msk

#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)

0x20000000

◆ CAN_F2R2_FB2_Msk

#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)

0x00000004

◆ CAN_F2R2_FB3

#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk

Filter bit 3

◆ CAN_F2R2_FB30

#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk

Filter bit 30

◆ CAN_F2R2_FB30_Msk

#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)

0x40000000

◆ CAN_F2R2_FB31

#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk

Filter bit 31

◆ CAN_F2R2_FB31_Msk

#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)

0x80000000

◆ CAN_F2R2_FB3_Msk

#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)

0x00000008

◆ CAN_F2R2_FB4

#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk

Filter bit 4

◆ CAN_F2R2_FB4_Msk

#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)

0x00000010

◆ CAN_F2R2_FB5

#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk

Filter bit 5

◆ CAN_F2R2_FB5_Msk

#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)

0x00000020

◆ CAN_F2R2_FB6

#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk

Filter bit 6

◆ CAN_F2R2_FB6_Msk

#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)

0x00000040

◆ CAN_F2R2_FB7

#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk

Filter bit 7

◆ CAN_F2R2_FB7_Msk

#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)

0x00000080

◆ CAN_F2R2_FB8

#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk

Filter bit 8

◆ CAN_F2R2_FB8_Msk

#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)

0x00000100

◆ CAN_F2R2_FB9

#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk

Filter bit 9

◆ CAN_F2R2_FB9_Msk

#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)

0x00000200

◆ CAN_F3R1_FB0

#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk

Filter bit 0

◆ CAN_F3R1_FB0_Msk

#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)

0x00000001

◆ CAN_F3R1_FB1

#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk

Filter bit 1

◆ CAN_F3R1_FB10

#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk

Filter bit 10

◆ CAN_F3R1_FB10_Msk

#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)

0x00000400

◆ CAN_F3R1_FB11

#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk

Filter bit 11

◆ CAN_F3R1_FB11_Msk

#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)

0x00000800

◆ CAN_F3R1_FB12

#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk

Filter bit 12

◆ CAN_F3R1_FB12_Msk

#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)

0x00001000

◆ CAN_F3R1_FB13

#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk

Filter bit 13

◆ CAN_F3R1_FB13_Msk

#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)

0x00002000

◆ CAN_F3R1_FB14

#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk

Filter bit 14

◆ CAN_F3R1_FB14_Msk

#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)

0x00004000

◆ CAN_F3R1_FB15

#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk

Filter bit 15

◆ CAN_F3R1_FB15_Msk

#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)

0x00008000

◆ CAN_F3R1_FB16

#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk

Filter bit 16

◆ CAN_F3R1_FB16_Msk

#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)

0x00010000

◆ CAN_F3R1_FB17

#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk

Filter bit 17

◆ CAN_F3R1_FB17_Msk

#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)

0x00020000

◆ CAN_F3R1_FB18

#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk

Filter bit 18

◆ CAN_F3R1_FB18_Msk

#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)

0x00040000

◆ CAN_F3R1_FB19

#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk

Filter bit 19

◆ CAN_F3R1_FB19_Msk

#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)

0x00080000

◆ CAN_F3R1_FB1_Msk

#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)

0x00000002

◆ CAN_F3R1_FB2

#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk

Filter bit 2

◆ CAN_F3R1_FB20

#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk

Filter bit 20

◆ CAN_F3R1_FB20_Msk

#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)

0x00100000

◆ CAN_F3R1_FB21

#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk

Filter bit 21

◆ CAN_F3R1_FB21_Msk

#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)

0x00200000

◆ CAN_F3R1_FB22

#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk

Filter bit 22

◆ CAN_F3R1_FB22_Msk

#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)

0x00400000

◆ CAN_F3R1_FB23

#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk

Filter bit 23

◆ CAN_F3R1_FB23_Msk

#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)

0x00800000

◆ CAN_F3R1_FB24

#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk

Filter bit 24

◆ CAN_F3R1_FB24_Msk

#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)

0x01000000

◆ CAN_F3R1_FB25

#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk

Filter bit 25

◆ CAN_F3R1_FB25_Msk

#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)

0x02000000

◆ CAN_F3R1_FB26

#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk

Filter bit 26

◆ CAN_F3R1_FB26_Msk

#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)

0x04000000

◆ CAN_F3R1_FB27

#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk

Filter bit 27

◆ CAN_F3R1_FB27_Msk

#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)

0x08000000

◆ CAN_F3R1_FB28

#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk

Filter bit 28

◆ CAN_F3R1_FB28_Msk

#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)

0x10000000

◆ CAN_F3R1_FB29

#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk

Filter bit 29

◆ CAN_F3R1_FB29_Msk

#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)

0x20000000

◆ CAN_F3R1_FB2_Msk

#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)

0x00000004

◆ CAN_F3R1_FB3

#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk

Filter bit 3

◆ CAN_F3R1_FB30

#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk

Filter bit 30

◆ CAN_F3R1_FB30_Msk

#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)

0x40000000

◆ CAN_F3R1_FB31

#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk

Filter bit 31

◆ CAN_F3R1_FB31_Msk

#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)

0x80000000

◆ CAN_F3R1_FB3_Msk

#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)

0x00000008

◆ CAN_F3R1_FB4

#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk

Filter bit 4

◆ CAN_F3R1_FB4_Msk

#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)

0x00000010

◆ CAN_F3R1_FB5

#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk

Filter bit 5

◆ CAN_F3R1_FB5_Msk

#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)

0x00000020

◆ CAN_F3R1_FB6

#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk

Filter bit 6

◆ CAN_F3R1_FB6_Msk

#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)

0x00000040

◆ CAN_F3R1_FB7

#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk

Filter bit 7

◆ CAN_F3R1_FB7_Msk

#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)

0x00000080

◆ CAN_F3R1_FB8

#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk

Filter bit 8

◆ CAN_F3R1_FB8_Msk

#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)

0x00000100

◆ CAN_F3R1_FB9

#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk

Filter bit 9

◆ CAN_F3R1_FB9_Msk

#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)

0x00000200

◆ CAN_F3R2_FB0

#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk

Filter bit 0

◆ CAN_F3R2_FB0_Msk

#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)

0x00000001

◆ CAN_F3R2_FB1

#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk

Filter bit 1

◆ CAN_F3R2_FB10

#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk

Filter bit 10

◆ CAN_F3R2_FB10_Msk

#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)

0x00000400

◆ CAN_F3R2_FB11

#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk

Filter bit 11

◆ CAN_F3R2_FB11_Msk

#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)

0x00000800

◆ CAN_F3R2_FB12

#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk

Filter bit 12

◆ CAN_F3R2_FB12_Msk

#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)

0x00001000

◆ CAN_F3R2_FB13

#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk

Filter bit 13

◆ CAN_F3R2_FB13_Msk

#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)

0x00002000

◆ CAN_F3R2_FB14

#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk

Filter bit 14

◆ CAN_F3R2_FB14_Msk

#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)

0x00004000

◆ CAN_F3R2_FB15

#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk

Filter bit 15

◆ CAN_F3R2_FB15_Msk

#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)

0x00008000

◆ CAN_F3R2_FB16

#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk

Filter bit 16

◆ CAN_F3R2_FB16_Msk

#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)

0x00010000

◆ CAN_F3R2_FB17

#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk

Filter bit 17

◆ CAN_F3R2_FB17_Msk

#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)

0x00020000

◆ CAN_F3R2_FB18

#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk

Filter bit 18

◆ CAN_F3R2_FB18_Msk

#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)

0x00040000

◆ CAN_F3R2_FB19

#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk

Filter bit 19

◆ CAN_F3R2_FB19_Msk

#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)

0x00080000

◆ CAN_F3R2_FB1_Msk

#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)

0x00000002

◆ CAN_F3R2_FB2

#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk

Filter bit 2

◆ CAN_F3R2_FB20

#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk

Filter bit 20

◆ CAN_F3R2_FB20_Msk

#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)

0x00100000

◆ CAN_F3R2_FB21

#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk

Filter bit 21

◆ CAN_F3R2_FB21_Msk

#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)

0x00200000

◆ CAN_F3R2_FB22

#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk

Filter bit 22

◆ CAN_F3R2_FB22_Msk

#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)

0x00400000

◆ CAN_F3R2_FB23

#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk

Filter bit 23

◆ CAN_F3R2_FB23_Msk

#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)

0x00800000

◆ CAN_F3R2_FB24

#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk

Filter bit 24

◆ CAN_F3R2_FB24_Msk

#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)

0x01000000

◆ CAN_F3R2_FB25

#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk

Filter bit 25

◆ CAN_F3R2_FB25_Msk

#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)

0x02000000

◆ CAN_F3R2_FB26

#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk

Filter bit 26

◆ CAN_F3R2_FB26_Msk

#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)

0x04000000

◆ CAN_F3R2_FB27

#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk

Filter bit 27

◆ CAN_F3R2_FB27_Msk

#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)

0x08000000

◆ CAN_F3R2_FB28

#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk

Filter bit 28

◆ CAN_F3R2_FB28_Msk

#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)

0x10000000

◆ CAN_F3R2_FB29

#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk

Filter bit 29

◆ CAN_F3R2_FB29_Msk

#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)

0x20000000

◆ CAN_F3R2_FB2_Msk

#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)

0x00000004

◆ CAN_F3R2_FB3

#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk

Filter bit 3

◆ CAN_F3R2_FB30

#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk

Filter bit 30

◆ CAN_F3R2_FB30_Msk

#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)

0x40000000

◆ CAN_F3R2_FB31

#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk

Filter bit 31

◆ CAN_F3R2_FB31_Msk

#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)

0x80000000

◆ CAN_F3R2_FB3_Msk

#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)

0x00000008

◆ CAN_F3R2_FB4

#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk

Filter bit 4

◆ CAN_F3R2_FB4_Msk

#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)

0x00000010

◆ CAN_F3R2_FB5

#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk

Filter bit 5

◆ CAN_F3R2_FB5_Msk

#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)

0x00000020

◆ CAN_F3R2_FB6

#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk

Filter bit 6

◆ CAN_F3R2_FB6_Msk

#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)

0x00000040

◆ CAN_F3R2_FB7

#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk

Filter bit 7

◆ CAN_F3R2_FB7_Msk

#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)

0x00000080

◆ CAN_F3R2_FB8

#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk

Filter bit 8

◆ CAN_F3R2_FB8_Msk

#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)

0x00000100

◆ CAN_F3R2_FB9

#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk

Filter bit 9

◆ CAN_F3R2_FB9_Msk

#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)

0x00000200

◆ CAN_F4R1_FB0

#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk

Filter bit 0

◆ CAN_F4R1_FB0_Msk

#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)

0x00000001

◆ CAN_F4R1_FB1

#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk

Filter bit 1

◆ CAN_F4R1_FB10

#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk

Filter bit 10

◆ CAN_F4R1_FB10_Msk

#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)

0x00000400

◆ CAN_F4R1_FB11

#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk

Filter bit 11

◆ CAN_F4R1_FB11_Msk

#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)

0x00000800

◆ CAN_F4R1_FB12

#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk

Filter bit 12

◆ CAN_F4R1_FB12_Msk

#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)

0x00001000

◆ CAN_F4R1_FB13

#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk

Filter bit 13

◆ CAN_F4R1_FB13_Msk

#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)

0x00002000

◆ CAN_F4R1_FB14

#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk

Filter bit 14

◆ CAN_F4R1_FB14_Msk

#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)

0x00004000

◆ CAN_F4R1_FB15

#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk

Filter bit 15

◆ CAN_F4R1_FB15_Msk

#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)

0x00008000

◆ CAN_F4R1_FB16

#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk

Filter bit 16

◆ CAN_F4R1_FB16_Msk

#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)

0x00010000

◆ CAN_F4R1_FB17

#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk

Filter bit 17

◆ CAN_F4R1_FB17_Msk

#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)

0x00020000

◆ CAN_F4R1_FB18

#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk

Filter bit 18

◆ CAN_F4R1_FB18_Msk

#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)

0x00040000

◆ CAN_F4R1_FB19

#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk

Filter bit 19

◆ CAN_F4R1_FB19_Msk

#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)

0x00080000

◆ CAN_F4R1_FB1_Msk

#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)

0x00000002

◆ CAN_F4R1_FB2

#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk

Filter bit 2

◆ CAN_F4R1_FB20

#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk

Filter bit 20

◆ CAN_F4R1_FB20_Msk

#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)

0x00100000

◆ CAN_F4R1_FB21

#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk

Filter bit 21

◆ CAN_F4R1_FB21_Msk

#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)

0x00200000

◆ CAN_F4R1_FB22

#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk

Filter bit 22

◆ CAN_F4R1_FB22_Msk

#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)

0x00400000

◆ CAN_F4R1_FB23

#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk

Filter bit 23

◆ CAN_F4R1_FB23_Msk

#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)

0x00800000

◆ CAN_F4R1_FB24

#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk

Filter bit 24

◆ CAN_F4R1_FB24_Msk

#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)

0x01000000

◆ CAN_F4R1_FB25

#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk

Filter bit 25

◆ CAN_F4R1_FB25_Msk

#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)

0x02000000

◆ CAN_F4R1_FB26

#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk

Filter bit 26

◆ CAN_F4R1_FB26_Msk

#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)

0x04000000

◆ CAN_F4R1_FB27

#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk

Filter bit 27

◆ CAN_F4R1_FB27_Msk

#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)

0x08000000

◆ CAN_F4R1_FB28

#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk

Filter bit 28

◆ CAN_F4R1_FB28_Msk

#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)

0x10000000

◆ CAN_F4R1_FB29

#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk

Filter bit 29

◆ CAN_F4R1_FB29_Msk

#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)

0x20000000

◆ CAN_F4R1_FB2_Msk

#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)

0x00000004

◆ CAN_F4R1_FB3

#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk

Filter bit 3

◆ CAN_F4R1_FB30

#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk

Filter bit 30

◆ CAN_F4R1_FB30_Msk

#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)

0x40000000

◆ CAN_F4R1_FB31

#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk

Filter bit 31

◆ CAN_F4R1_FB31_Msk

#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)

0x80000000

◆ CAN_F4R1_FB3_Msk

#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)

0x00000008

◆ CAN_F4R1_FB4

#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk

Filter bit 4

◆ CAN_F4R1_FB4_Msk

#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)

0x00000010

◆ CAN_F4R1_FB5

#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk

Filter bit 5

◆ CAN_F4R1_FB5_Msk

#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)

0x00000020

◆ CAN_F4R1_FB6

#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk

Filter bit 6

◆ CAN_F4R1_FB6_Msk

#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)

0x00000040

◆ CAN_F4R1_FB7

#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk

Filter bit 7

◆ CAN_F4R1_FB7_Msk

#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)

0x00000080

◆ CAN_F4R1_FB8

#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk

Filter bit 8

◆ CAN_F4R1_FB8_Msk

#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)

0x00000100

◆ CAN_F4R1_FB9

#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk

Filter bit 9

◆ CAN_F4R1_FB9_Msk

#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)

0x00000200

◆ CAN_F4R2_FB0

#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk

Filter bit 0

◆ CAN_F4R2_FB0_Msk

#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)

0x00000001

◆ CAN_F4R2_FB1

#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk

Filter bit 1

◆ CAN_F4R2_FB10

#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk

Filter bit 10

◆ CAN_F4R2_FB10_Msk

#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)

0x00000400

◆ CAN_F4R2_FB11

#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk

Filter bit 11

◆ CAN_F4R2_FB11_Msk

#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)

0x00000800

◆ CAN_F4R2_FB12

#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk

Filter bit 12

◆ CAN_F4R2_FB12_Msk

#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)

0x00001000

◆ CAN_F4R2_FB13

#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk

Filter bit 13

◆ CAN_F4R2_FB13_Msk

#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)

0x00002000

◆ CAN_F4R2_FB14

#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk

Filter bit 14

◆ CAN_F4R2_FB14_Msk

#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)

0x00004000

◆ CAN_F4R2_FB15

#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk

Filter bit 15

◆ CAN_F4R2_FB15_Msk

#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)

0x00008000

◆ CAN_F4R2_FB16

#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk

Filter bit 16

◆ CAN_F4R2_FB16_Msk

#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)

0x00010000

◆ CAN_F4R2_FB17

#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk

Filter bit 17

◆ CAN_F4R2_FB17_Msk

#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)

0x00020000

◆ CAN_F4R2_FB18

#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk

Filter bit 18

◆ CAN_F4R2_FB18_Msk

#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)

0x00040000

◆ CAN_F4R2_FB19

#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk

Filter bit 19

◆ CAN_F4R2_FB19_Msk

#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)

0x00080000

◆ CAN_F4R2_FB1_Msk

#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)

0x00000002

◆ CAN_F4R2_FB2

#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk

Filter bit 2

◆ CAN_F4R2_FB20

#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk

Filter bit 20

◆ CAN_F4R2_FB20_Msk

#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)

0x00100000

◆ CAN_F4R2_FB21

#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk

Filter bit 21

◆ CAN_F4R2_FB21_Msk

#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)

0x00200000

◆ CAN_F4R2_FB22

#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk

Filter bit 22

◆ CAN_F4R2_FB22_Msk

#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)

0x00400000

◆ CAN_F4R2_FB23

#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk

Filter bit 23

◆ CAN_F4R2_FB23_Msk

#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)

0x00800000

◆ CAN_F4R2_FB24

#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk

Filter bit 24

◆ CAN_F4R2_FB24_Msk

#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)

0x01000000

◆ CAN_F4R2_FB25

#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk

Filter bit 25

◆ CAN_F4R2_FB25_Msk

#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)

0x02000000

◆ CAN_F4R2_FB26

#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk

Filter bit 26

◆ CAN_F4R2_FB26_Msk

#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)

0x04000000

◆ CAN_F4R2_FB27

#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk

Filter bit 27

◆ CAN_F4R2_FB27_Msk

#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)

0x08000000

◆ CAN_F4R2_FB28

#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk

Filter bit 28

◆ CAN_F4R2_FB28_Msk

#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)

0x10000000

◆ CAN_F4R2_FB29

#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk

Filter bit 29

◆ CAN_F4R2_FB29_Msk

#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)

0x20000000

◆ CAN_F4R2_FB2_Msk

#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)

0x00000004

◆ CAN_F4R2_FB3

#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk

Filter bit 3

◆ CAN_F4R2_FB30

#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk

Filter bit 30

◆ CAN_F4R2_FB30_Msk

#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)

0x40000000

◆ CAN_F4R2_FB31

#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk

Filter bit 31

◆ CAN_F4R2_FB31_Msk

#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)

0x80000000

◆ CAN_F4R2_FB3_Msk

#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)

0x00000008

◆ CAN_F4R2_FB4

#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk

Filter bit 4

◆ CAN_F4R2_FB4_Msk

#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)

0x00000010

◆ CAN_F4R2_FB5

#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk

Filter bit 5

◆ CAN_F4R2_FB5_Msk

#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)

0x00000020

◆ CAN_F4R2_FB6

#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk

Filter bit 6

◆ CAN_F4R2_FB6_Msk

#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)

0x00000040

◆ CAN_F4R2_FB7

#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk

Filter bit 7

◆ CAN_F4R2_FB7_Msk

#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)

0x00000080

◆ CAN_F4R2_FB8

#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk

Filter bit 8

◆ CAN_F4R2_FB8_Msk

#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)

0x00000100

◆ CAN_F4R2_FB9

#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk

Filter bit 9

◆ CAN_F4R2_FB9_Msk

#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)

0x00000200

◆ CAN_F5R1_FB0

#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk

Filter bit 0

◆ CAN_F5R1_FB0_Msk

#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)

0x00000001

◆ CAN_F5R1_FB1

#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk

Filter bit 1

◆ CAN_F5R1_FB10

#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk

Filter bit 10

◆ CAN_F5R1_FB10_Msk

#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)

0x00000400

◆ CAN_F5R1_FB11

#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk

Filter bit 11

◆ CAN_F5R1_FB11_Msk

#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)

0x00000800

◆ CAN_F5R1_FB12

#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk

Filter bit 12

◆ CAN_F5R1_FB12_Msk

#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)

0x00001000

◆ CAN_F5R1_FB13

#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk

Filter bit 13

◆ CAN_F5R1_FB13_Msk

#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)

0x00002000

◆ CAN_F5R1_FB14

#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk

Filter bit 14

◆ CAN_F5R1_FB14_Msk

#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)

0x00004000

◆ CAN_F5R1_FB15

#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk

Filter bit 15

◆ CAN_F5R1_FB15_Msk

#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)

0x00008000

◆ CAN_F5R1_FB16

#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk

Filter bit 16

◆ CAN_F5R1_FB16_Msk

#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)

0x00010000

◆ CAN_F5R1_FB17

#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk

Filter bit 17

◆ CAN_F5R1_FB17_Msk

#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)

0x00020000

◆ CAN_F5R1_FB18

#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk

Filter bit 18

◆ CAN_F5R1_FB18_Msk

#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)

0x00040000

◆ CAN_F5R1_FB19

#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk

Filter bit 19

◆ CAN_F5R1_FB19_Msk

#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)

0x00080000

◆ CAN_F5R1_FB1_Msk

#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)

0x00000002

◆ CAN_F5R1_FB2

#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk

Filter bit 2

◆ CAN_F5R1_FB20

#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk

Filter bit 20

◆ CAN_F5R1_FB20_Msk

#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)

0x00100000

◆ CAN_F5R1_FB21

#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk

Filter bit 21

◆ CAN_F5R1_FB21_Msk

#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)

0x00200000

◆ CAN_F5R1_FB22

#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk

Filter bit 22

◆ CAN_F5R1_FB22_Msk

#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)

0x00400000

◆ CAN_F5R1_FB23

#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk

Filter bit 23

◆ CAN_F5R1_FB23_Msk

#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)

0x00800000

◆ CAN_F5R1_FB24

#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk

Filter bit 24

◆ CAN_F5R1_FB24_Msk

#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)

0x01000000

◆ CAN_F5R1_FB25

#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk

Filter bit 25

◆ CAN_F5R1_FB25_Msk

#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)

0x02000000

◆ CAN_F5R1_FB26

#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk

Filter bit 26

◆ CAN_F5R1_FB26_Msk

#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)

0x04000000

◆ CAN_F5R1_FB27

#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk

Filter bit 27

◆ CAN_F5R1_FB27_Msk

#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)

0x08000000

◆ CAN_F5R1_FB28

#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk

Filter bit 28

◆ CAN_F5R1_FB28_Msk

#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)

0x10000000

◆ CAN_F5R1_FB29

#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk

Filter bit 29

◆ CAN_F5R1_FB29_Msk

#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)

0x20000000

◆ CAN_F5R1_FB2_Msk

#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)

0x00000004

◆ CAN_F5R1_FB3

#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk

Filter bit 3

◆ CAN_F5R1_FB30

#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk

Filter bit 30

◆ CAN_F5R1_FB30_Msk

#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)

0x40000000

◆ CAN_F5R1_FB31

#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk

Filter bit 31

◆ CAN_F5R1_FB31_Msk

#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)

0x80000000

◆ CAN_F5R1_FB3_Msk

#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)

0x00000008

◆ CAN_F5R1_FB4

#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk

Filter bit 4

◆ CAN_F5R1_FB4_Msk

#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)

0x00000010

◆ CAN_F5R1_FB5

#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk

Filter bit 5

◆ CAN_F5R1_FB5_Msk

#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)

0x00000020

◆ CAN_F5R1_FB6

#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk

Filter bit 6

◆ CAN_F5R1_FB6_Msk

#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)

0x00000040

◆ CAN_F5R1_FB7

#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk

Filter bit 7

◆ CAN_F5R1_FB7_Msk

#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)

0x00000080

◆ CAN_F5R1_FB8

#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk

Filter bit 8

◆ CAN_F5R1_FB8_Msk

#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)

0x00000100

◆ CAN_F5R1_FB9

#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk

Filter bit 9

◆ CAN_F5R1_FB9_Msk

#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)

0x00000200

◆ CAN_F5R2_FB0

#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk

Filter bit 0

◆ CAN_F5R2_FB0_Msk

#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)

0x00000001

◆ CAN_F5R2_FB1

#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk

Filter bit 1

◆ CAN_F5R2_FB10

#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk

Filter bit 10

◆ CAN_F5R2_FB10_Msk

#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)

0x00000400

◆ CAN_F5R2_FB11

#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk

Filter bit 11

◆ CAN_F5R2_FB11_Msk

#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)

0x00000800

◆ CAN_F5R2_FB12

#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk

Filter bit 12

◆ CAN_F5R2_FB12_Msk

#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)

0x00001000

◆ CAN_F5R2_FB13

#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk

Filter bit 13

◆ CAN_F5R2_FB13_Msk

#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)

0x00002000

◆ CAN_F5R2_FB14

#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk

Filter bit 14

◆ CAN_F5R2_FB14_Msk

#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)

0x00004000

◆ CAN_F5R2_FB15

#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk

Filter bit 15

◆ CAN_F5R2_FB15_Msk

#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)

0x00008000

◆ CAN_F5R2_FB16

#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk

Filter bit 16

◆ CAN_F5R2_FB16_Msk

#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)

0x00010000

◆ CAN_F5R2_FB17

#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk

Filter bit 17

◆ CAN_F5R2_FB17_Msk

#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)

0x00020000

◆ CAN_F5R2_FB18

#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk

Filter bit 18

◆ CAN_F5R2_FB18_Msk

#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)

0x00040000

◆ CAN_F5R2_FB19

#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk

Filter bit 19

◆ CAN_F5R2_FB19_Msk

#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)

0x00080000

◆ CAN_F5R2_FB1_Msk

#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)

0x00000002

◆ CAN_F5R2_FB2

#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk

Filter bit 2

◆ CAN_F5R2_FB20

#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk

Filter bit 20

◆ CAN_F5R2_FB20_Msk

#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)

0x00100000

◆ CAN_F5R2_FB21

#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk

Filter bit 21

◆ CAN_F5R2_FB21_Msk

#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)

0x00200000

◆ CAN_F5R2_FB22

#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk

Filter bit 22

◆ CAN_F5R2_FB22_Msk

#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)

0x00400000

◆ CAN_F5R2_FB23

#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk

Filter bit 23

◆ CAN_F5R2_FB23_Msk

#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)

0x00800000

◆ CAN_F5R2_FB24

#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk

Filter bit 24

◆ CAN_F5R2_FB24_Msk

#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)

0x01000000

◆ CAN_F5R2_FB25

#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk

Filter bit 25

◆ CAN_F5R2_FB25_Msk

#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)

0x02000000

◆ CAN_F5R2_FB26

#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk

Filter bit 26

◆ CAN_F5R2_FB26_Msk

#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)

0x04000000

◆ CAN_F5R2_FB27

#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk

Filter bit 27

◆ CAN_F5R2_FB27_Msk

#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)

0x08000000

◆ CAN_F5R2_FB28

#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk

Filter bit 28

◆ CAN_F5R2_FB28_Msk

#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)

0x10000000

◆ CAN_F5R2_FB29

#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk

Filter bit 29

◆ CAN_F5R2_FB29_Msk

#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)

0x20000000

◆ CAN_F5R2_FB2_Msk

#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)

0x00000004

◆ CAN_F5R2_FB3

#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk

Filter bit 3

◆ CAN_F5R2_FB30

#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk

Filter bit 30

◆ CAN_F5R2_FB30_Msk

#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)

0x40000000

◆ CAN_F5R2_FB31

#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk

Filter bit 31

◆ CAN_F5R2_FB31_Msk

#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)

0x80000000

◆ CAN_F5R2_FB3_Msk

#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)

0x00000008

◆ CAN_F5R2_FB4

#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk

Filter bit 4

◆ CAN_F5R2_FB4_Msk

#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)

0x00000010

◆ CAN_F5R2_FB5

#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk

Filter bit 5

◆ CAN_F5R2_FB5_Msk

#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)

0x00000020

◆ CAN_F5R2_FB6

#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk

Filter bit 6

◆ CAN_F5R2_FB6_Msk

#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)

0x00000040

◆ CAN_F5R2_FB7

#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk

Filter bit 7

◆ CAN_F5R2_FB7_Msk

#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)

0x00000080

◆ CAN_F5R2_FB8

#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk

Filter bit 8

◆ CAN_F5R2_FB8_Msk

#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)

0x00000100

◆ CAN_F5R2_FB9

#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk

Filter bit 9

◆ CAN_F5R2_FB9_Msk

#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)

0x00000200

◆ CAN_F6R1_FB0

#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk

Filter bit 0

◆ CAN_F6R1_FB0_Msk

#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)

0x00000001

◆ CAN_F6R1_FB1

#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk

Filter bit 1

◆ CAN_F6R1_FB10

#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk

Filter bit 10

◆ CAN_F6R1_FB10_Msk

#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)

0x00000400

◆ CAN_F6R1_FB11

#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk

Filter bit 11

◆ CAN_F6R1_FB11_Msk

#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)

0x00000800

◆ CAN_F6R1_FB12

#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk

Filter bit 12

◆ CAN_F6R1_FB12_Msk

#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)

0x00001000

◆ CAN_F6R1_FB13

#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk

Filter bit 13

◆ CAN_F6R1_FB13_Msk

#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)

0x00002000

◆ CAN_F6R1_FB14

#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk

Filter bit 14

◆ CAN_F6R1_FB14_Msk

#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)

0x00004000

◆ CAN_F6R1_FB15

#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk

Filter bit 15

◆ CAN_F6R1_FB15_Msk

#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)

0x00008000

◆ CAN_F6R1_FB16

#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk

Filter bit 16

◆ CAN_F6R1_FB16_Msk

#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)

0x00010000

◆ CAN_F6R1_FB17

#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk

Filter bit 17

◆ CAN_F6R1_FB17_Msk

#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)

0x00020000

◆ CAN_F6R1_FB18

#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk

Filter bit 18

◆ CAN_F6R1_FB18_Msk

#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)

0x00040000

◆ CAN_F6R1_FB19

#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk

Filter bit 19

◆ CAN_F6R1_FB19_Msk

#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)

0x00080000

◆ CAN_F6R1_FB1_Msk

#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)

0x00000002

◆ CAN_F6R1_FB2

#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk

Filter bit 2

◆ CAN_F6R1_FB20

#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk

Filter bit 20

◆ CAN_F6R1_FB20_Msk

#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)

0x00100000

◆ CAN_F6R1_FB21

#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk

Filter bit 21

◆ CAN_F6R1_FB21_Msk

#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)

0x00200000

◆ CAN_F6R1_FB22

#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk

Filter bit 22

◆ CAN_F6R1_FB22_Msk

#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)

0x00400000

◆ CAN_F6R1_FB23

#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk

Filter bit 23

◆ CAN_F6R1_FB23_Msk

#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)

0x00800000

◆ CAN_F6R1_FB24

#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk

Filter bit 24

◆ CAN_F6R1_FB24_Msk

#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)

0x01000000

◆ CAN_F6R1_FB25

#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk

Filter bit 25

◆ CAN_F6R1_FB25_Msk

#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)

0x02000000

◆ CAN_F6R1_FB26

#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk

Filter bit 26

◆ CAN_F6R1_FB26_Msk

#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)

0x04000000

◆ CAN_F6R1_FB27

#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk

Filter bit 27

◆ CAN_F6R1_FB27_Msk

#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)

0x08000000

◆ CAN_F6R1_FB28

#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk

Filter bit 28

◆ CAN_F6R1_FB28_Msk

#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)

0x10000000

◆ CAN_F6R1_FB29

#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk

Filter bit 29

◆ CAN_F6R1_FB29_Msk

#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)

0x20000000

◆ CAN_F6R1_FB2_Msk

#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)

0x00000004

◆ CAN_F6R1_FB3

#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk

Filter bit 3

◆ CAN_F6R1_FB30

#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk

Filter bit 30

◆ CAN_F6R1_FB30_Msk

#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)

0x40000000

◆ CAN_F6R1_FB31

#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk

Filter bit 31

◆ CAN_F6R1_FB31_Msk

#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)

0x80000000

◆ CAN_F6R1_FB3_Msk

#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)

0x00000008

◆ CAN_F6R1_FB4

#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk

Filter bit 4

◆ CAN_F6R1_FB4_Msk

#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)

0x00000010

◆ CAN_F6R1_FB5

#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk

Filter bit 5

◆ CAN_F6R1_FB5_Msk

#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)

0x00000020

◆ CAN_F6R1_FB6

#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk

Filter bit 6

◆ CAN_F6R1_FB6_Msk

#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)

0x00000040

◆ CAN_F6R1_FB7

#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk

Filter bit 7

◆ CAN_F6R1_FB7_Msk

#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)

0x00000080

◆ CAN_F6R1_FB8

#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk

Filter bit 8

◆ CAN_F6R1_FB8_Msk

#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)

0x00000100

◆ CAN_F6R1_FB9

#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk

Filter bit 9

◆ CAN_F6R1_FB9_Msk

#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)

0x00000200

◆ CAN_F6R2_FB0

#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk

Filter bit 0

◆ CAN_F6R2_FB0_Msk

#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)

0x00000001

◆ CAN_F6R2_FB1

#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk

Filter bit 1

◆ CAN_F6R2_FB10

#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk

Filter bit 10

◆ CAN_F6R2_FB10_Msk

#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)

0x00000400

◆ CAN_F6R2_FB11

#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk

Filter bit 11

◆ CAN_F6R2_FB11_Msk

#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)

0x00000800

◆ CAN_F6R2_FB12

#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk

Filter bit 12

◆ CAN_F6R2_FB12_Msk

#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)

0x00001000

◆ CAN_F6R2_FB13

#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk

Filter bit 13

◆ CAN_F6R2_FB13_Msk

#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)

0x00002000

◆ CAN_F6R2_FB14

#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk

Filter bit 14

◆ CAN_F6R2_FB14_Msk

#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)

0x00004000

◆ CAN_F6R2_FB15

#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk

Filter bit 15

◆ CAN_F6R2_FB15_Msk

#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)

0x00008000

◆ CAN_F6R2_FB16

#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk

Filter bit 16

◆ CAN_F6R2_FB16_Msk

#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)

0x00010000

◆ CAN_F6R2_FB17

#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk

Filter bit 17

◆ CAN_F6R2_FB17_Msk

#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)

0x00020000

◆ CAN_F6R2_FB18

#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk

Filter bit 18

◆ CAN_F6R2_FB18_Msk

#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)

0x00040000

◆ CAN_F6R2_FB19

#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk

Filter bit 19

◆ CAN_F6R2_FB19_Msk

#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)

0x00080000

◆ CAN_F6R2_FB1_Msk

#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)

0x00000002

◆ CAN_F6R2_FB2

#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk

Filter bit 2

◆ CAN_F6R2_FB20

#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk

Filter bit 20

◆ CAN_F6R2_FB20_Msk

#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)

0x00100000

◆ CAN_F6R2_FB21

#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk

Filter bit 21

◆ CAN_F6R2_FB21_Msk

#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)

0x00200000

◆ CAN_F6R2_FB22

#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk

Filter bit 22

◆ CAN_F6R2_FB22_Msk

#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)

0x00400000

◆ CAN_F6R2_FB23

#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk

Filter bit 23

◆ CAN_F6R2_FB23_Msk

#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)

0x00800000

◆ CAN_F6R2_FB24

#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk

Filter bit 24

◆ CAN_F6R2_FB24_Msk

#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)

0x01000000

◆ CAN_F6R2_FB25

#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk

Filter bit 25

◆ CAN_F6R2_FB25_Msk

#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)

0x02000000

◆ CAN_F6R2_FB26

#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk

Filter bit 26

◆ CAN_F6R2_FB26_Msk

#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)

0x04000000

◆ CAN_F6R2_FB27

#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk

Filter bit 27

◆ CAN_F6R2_FB27_Msk

#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)

0x08000000

◆ CAN_F6R2_FB28

#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk

Filter bit 28

◆ CAN_F6R2_FB28_Msk

#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)

0x10000000

◆ CAN_F6R2_FB29

#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk

Filter bit 29

◆ CAN_F6R2_FB29_Msk

#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)

0x20000000

◆ CAN_F6R2_FB2_Msk

#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)

0x00000004

◆ CAN_F6R2_FB3

#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk

Filter bit 3

◆ CAN_F6R2_FB30

#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk

Filter bit 30

◆ CAN_F6R2_FB30_Msk

#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)

0x40000000

◆ CAN_F6R2_FB31

#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk

Filter bit 31

◆ CAN_F6R2_FB31_Msk

#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)

0x80000000

◆ CAN_F6R2_FB3_Msk

#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)

0x00000008

◆ CAN_F6R2_FB4

#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk

Filter bit 4

◆ CAN_F6R2_FB4_Msk

#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)

0x00000010

◆ CAN_F6R2_FB5

#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk

Filter bit 5

◆ CAN_F6R2_FB5_Msk

#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)

0x00000020

◆ CAN_F6R2_FB6

#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk

Filter bit 6

◆ CAN_F6R2_FB6_Msk

#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)

0x00000040

◆ CAN_F6R2_FB7

#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk

Filter bit 7

◆ CAN_F6R2_FB7_Msk

#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)

0x00000080

◆ CAN_F6R2_FB8

#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk

Filter bit 8

◆ CAN_F6R2_FB8_Msk

#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)

0x00000100

◆ CAN_F6R2_FB9

#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk

Filter bit 9

◆ CAN_F6R2_FB9_Msk

#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)

0x00000200

◆ CAN_F7R1_FB0

#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk

Filter bit 0

◆ CAN_F7R1_FB0_Msk

#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)

0x00000001

◆ CAN_F7R1_FB1

#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk

Filter bit 1

◆ CAN_F7R1_FB10

#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk

Filter bit 10

◆ CAN_F7R1_FB10_Msk

#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)

0x00000400

◆ CAN_F7R1_FB11

#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk

Filter bit 11

◆ CAN_F7R1_FB11_Msk

#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)

0x00000800

◆ CAN_F7R1_FB12

#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk

Filter bit 12

◆ CAN_F7R1_FB12_Msk

#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)

0x00001000

◆ CAN_F7R1_FB13

#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk

Filter bit 13

◆ CAN_F7R1_FB13_Msk

#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)

0x00002000

◆ CAN_F7R1_FB14

#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk

Filter bit 14

◆ CAN_F7R1_FB14_Msk

#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)

0x00004000

◆ CAN_F7R1_FB15

#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk

Filter bit 15

◆ CAN_F7R1_FB15_Msk

#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)

0x00008000

◆ CAN_F7R1_FB16

#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk

Filter bit 16

◆ CAN_F7R1_FB16_Msk

#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)

0x00010000

◆ CAN_F7R1_FB17

#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk

Filter bit 17

◆ CAN_F7R1_FB17_Msk

#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)

0x00020000

◆ CAN_F7R1_FB18

#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk

Filter bit 18

◆ CAN_F7R1_FB18_Msk

#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)

0x00040000

◆ CAN_F7R1_FB19

#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk

Filter bit 19

◆ CAN_F7R1_FB19_Msk

#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)

0x00080000

◆ CAN_F7R1_FB1_Msk

#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)

0x00000002

◆ CAN_F7R1_FB2

#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk

Filter bit 2

◆ CAN_F7R1_FB20

#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk

Filter bit 20

◆ CAN_F7R1_FB20_Msk

#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)

0x00100000

◆ CAN_F7R1_FB21

#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk

Filter bit 21

◆ CAN_F7R1_FB21_Msk

#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)

0x00200000

◆ CAN_F7R1_FB22

#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk

Filter bit 22

◆ CAN_F7R1_FB22_Msk

#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)

0x00400000

◆ CAN_F7R1_FB23

#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk

Filter bit 23

◆ CAN_F7R1_FB23_Msk

#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)

0x00800000

◆ CAN_F7R1_FB24

#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk

Filter bit 24

◆ CAN_F7R1_FB24_Msk

#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)

0x01000000

◆ CAN_F7R1_FB25

#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk

Filter bit 25

◆ CAN_F7R1_FB25_Msk

#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)

0x02000000

◆ CAN_F7R1_FB26

#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk

Filter bit 26

◆ CAN_F7R1_FB26_Msk

#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)

0x04000000

◆ CAN_F7R1_FB27

#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk

Filter bit 27

◆ CAN_F7R1_FB27_Msk

#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)

0x08000000

◆ CAN_F7R1_FB28

#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk

Filter bit 28

◆ CAN_F7R1_FB28_Msk

#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)

0x10000000

◆ CAN_F7R1_FB29

#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk

Filter bit 29

◆ CAN_F7R1_FB29_Msk

#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)

0x20000000

◆ CAN_F7R1_FB2_Msk

#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)

0x00000004

◆ CAN_F7R1_FB3

#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk

Filter bit 3

◆ CAN_F7R1_FB30

#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk

Filter bit 30

◆ CAN_F7R1_FB30_Msk

#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)

0x40000000

◆ CAN_F7R1_FB31

#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk

Filter bit 31

◆ CAN_F7R1_FB31_Msk

#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)

0x80000000

◆ CAN_F7R1_FB3_Msk

#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)

0x00000008

◆ CAN_F7R1_FB4

#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk

Filter bit 4

◆ CAN_F7R1_FB4_Msk

#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)

0x00000010

◆ CAN_F7R1_FB5

#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk

Filter bit 5

◆ CAN_F7R1_FB5_Msk

#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)

0x00000020

◆ CAN_F7R1_FB6

#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk

Filter bit 6

◆ CAN_F7R1_FB6_Msk

#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)

0x00000040

◆ CAN_F7R1_FB7

#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk

Filter bit 7

◆ CAN_F7R1_FB7_Msk

#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)

0x00000080

◆ CAN_F7R1_FB8

#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk

Filter bit 8

◆ CAN_F7R1_FB8_Msk

#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)

0x00000100

◆ CAN_F7R1_FB9

#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk

Filter bit 9

◆ CAN_F7R1_FB9_Msk

#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)

0x00000200

◆ CAN_F7R2_FB0

#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk

Filter bit 0

◆ CAN_F7R2_FB0_Msk

#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)

0x00000001

◆ CAN_F7R2_FB1

#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk

Filter bit 1

◆ CAN_F7R2_FB10

#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk

Filter bit 10

◆ CAN_F7R2_FB10_Msk

#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)

0x00000400

◆ CAN_F7R2_FB11

#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk

Filter bit 11

◆ CAN_F7R2_FB11_Msk

#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)

0x00000800

◆ CAN_F7R2_FB12

#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk

Filter bit 12

◆ CAN_F7R2_FB12_Msk

#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)

0x00001000

◆ CAN_F7R2_FB13

#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk

Filter bit 13

◆ CAN_F7R2_FB13_Msk

#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)

0x00002000

◆ CAN_F7R2_FB14

#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk

Filter bit 14

◆ CAN_F7R2_FB14_Msk

#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)

0x00004000

◆ CAN_F7R2_FB15

#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk

Filter bit 15

◆ CAN_F7R2_FB15_Msk

#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)

0x00008000

◆ CAN_F7R2_FB16

#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk

Filter bit 16

◆ CAN_F7R2_FB16_Msk

#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)

0x00010000

◆ CAN_F7R2_FB17

#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk

Filter bit 17

◆ CAN_F7R2_FB17_Msk

#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)

0x00020000

◆ CAN_F7R2_FB18

#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk

Filter bit 18

◆ CAN_F7R2_FB18_Msk

#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)

0x00040000

◆ CAN_F7R2_FB19

#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk

Filter bit 19

◆ CAN_F7R2_FB19_Msk

#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)

0x00080000

◆ CAN_F7R2_FB1_Msk

#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)

0x00000002

◆ CAN_F7R2_FB2

#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk

Filter bit 2

◆ CAN_F7R2_FB20

#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk

Filter bit 20

◆ CAN_F7R2_FB20_Msk

#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)

0x00100000

◆ CAN_F7R2_FB21

#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk

Filter bit 21

◆ CAN_F7R2_FB21_Msk

#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)

0x00200000

◆ CAN_F7R2_FB22

#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk

Filter bit 22

◆ CAN_F7R2_FB22_Msk

#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)

0x00400000

◆ CAN_F7R2_FB23

#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk

Filter bit 23

◆ CAN_F7R2_FB23_Msk

#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)

0x00800000

◆ CAN_F7R2_FB24

#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk

Filter bit 24

◆ CAN_F7R2_FB24_Msk

#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)

0x01000000

◆ CAN_F7R2_FB25

#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk

Filter bit 25

◆ CAN_F7R2_FB25_Msk

#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)

0x02000000

◆ CAN_F7R2_FB26

#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk

Filter bit 26

◆ CAN_F7R2_FB26_Msk

#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)

0x04000000

◆ CAN_F7R2_FB27

#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk

Filter bit 27

◆ CAN_F7R2_FB27_Msk

#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)

0x08000000

◆ CAN_F7R2_FB28

#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk

Filter bit 28

◆ CAN_F7R2_FB28_Msk

#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)

0x10000000

◆ CAN_F7R2_FB29

#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk

Filter bit 29

◆ CAN_F7R2_FB29_Msk

#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)

0x20000000

◆ CAN_F7R2_FB2_Msk

#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)

0x00000004

◆ CAN_F7R2_FB3

#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk

Filter bit 3

◆ CAN_F7R2_FB30

#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk

Filter bit 30

◆ CAN_F7R2_FB30_Msk

#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)

0x40000000

◆ CAN_F7R2_FB31

#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk

Filter bit 31

◆ CAN_F7R2_FB31_Msk

#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)

0x80000000

◆ CAN_F7R2_FB3_Msk

#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)

0x00000008

◆ CAN_F7R2_FB4

#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk

Filter bit 4

◆ CAN_F7R2_FB4_Msk

#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)

0x00000010

◆ CAN_F7R2_FB5

#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk

Filter bit 5

◆ CAN_F7R2_FB5_Msk

#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)

0x00000020

◆ CAN_F7R2_FB6

#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk

Filter bit 6

◆ CAN_F7R2_FB6_Msk

#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)

0x00000040

◆ CAN_F7R2_FB7

#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk

Filter bit 7

◆ CAN_F7R2_FB7_Msk

#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)

0x00000080

◆ CAN_F7R2_FB8

#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk

Filter bit 8

◆ CAN_F7R2_FB8_Msk

#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)

0x00000100

◆ CAN_F7R2_FB9

#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk

Filter bit 9

◆ CAN_F7R2_FB9_Msk

#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)

0x00000200

◆ CAN_F8R1_FB0

#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk

Filter bit 0

◆ CAN_F8R1_FB0_Msk

#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)

0x00000001

◆ CAN_F8R1_FB1

#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk

Filter bit 1

◆ CAN_F8R1_FB10

#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk

Filter bit 10

◆ CAN_F8R1_FB10_Msk

#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)

0x00000400

◆ CAN_F8R1_FB11

#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk

Filter bit 11

◆ CAN_F8R1_FB11_Msk

#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)

0x00000800

◆ CAN_F8R1_FB12

#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk

Filter bit 12

◆ CAN_F8R1_FB12_Msk

#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)

0x00001000

◆ CAN_F8R1_FB13

#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk

Filter bit 13

◆ CAN_F8R1_FB13_Msk

#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)

0x00002000

◆ CAN_F8R1_FB14

#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk

Filter bit 14

◆ CAN_F8R1_FB14_Msk

#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)

0x00004000

◆ CAN_F8R1_FB15

#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk

Filter bit 15

◆ CAN_F8R1_FB15_Msk

#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)

0x00008000

◆ CAN_F8R1_FB16

#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk

Filter bit 16

◆ CAN_F8R1_FB16_Msk

#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)

0x00010000

◆ CAN_F8R1_FB17

#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk

Filter bit 17

◆ CAN_F8R1_FB17_Msk

#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)

0x00020000

◆ CAN_F8R1_FB18

#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk

Filter bit 18

◆ CAN_F8R1_FB18_Msk

#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)

0x00040000

◆ CAN_F8R1_FB19

#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk

Filter bit 19

◆ CAN_F8R1_FB19_Msk

#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)

0x00080000

◆ CAN_F8R1_FB1_Msk

#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)

0x00000002

◆ CAN_F8R1_FB2

#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk

Filter bit 2

◆ CAN_F8R1_FB20

#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk

Filter bit 20

◆ CAN_F8R1_FB20_Msk

#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)

0x00100000

◆ CAN_F8R1_FB21

#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk

Filter bit 21

◆ CAN_F8R1_FB21_Msk

#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)

0x00200000

◆ CAN_F8R1_FB22

#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk

Filter bit 22

◆ CAN_F8R1_FB22_Msk

#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)

0x00400000

◆ CAN_F8R1_FB23

#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk

Filter bit 23

◆ CAN_F8R1_FB23_Msk

#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)

0x00800000

◆ CAN_F8R1_FB24

#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk

Filter bit 24

◆ CAN_F8R1_FB24_Msk

#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)

0x01000000

◆ CAN_F8R1_FB25

#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk

Filter bit 25

◆ CAN_F8R1_FB25_Msk

#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)

0x02000000

◆ CAN_F8R1_FB26

#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk

Filter bit 26

◆ CAN_F8R1_FB26_Msk

#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)

0x04000000

◆ CAN_F8R1_FB27

#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk

Filter bit 27

◆ CAN_F8R1_FB27_Msk

#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)

0x08000000

◆ CAN_F8R1_FB28

#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk

Filter bit 28

◆ CAN_F8R1_FB28_Msk

#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)

0x10000000

◆ CAN_F8R1_FB29

#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk

Filter bit 29

◆ CAN_F8R1_FB29_Msk

#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)

0x20000000

◆ CAN_F8R1_FB2_Msk

#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)

0x00000004

◆ CAN_F8R1_FB3

#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk

Filter bit 3

◆ CAN_F8R1_FB30

#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk

Filter bit 30

◆ CAN_F8R1_FB30_Msk

#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)

0x40000000

◆ CAN_F8R1_FB31

#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk

Filter bit 31

◆ CAN_F8R1_FB31_Msk

#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)

0x80000000

◆ CAN_F8R1_FB3_Msk

#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)

0x00000008

◆ CAN_F8R1_FB4

#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk

Filter bit 4

◆ CAN_F8R1_FB4_Msk

#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)

0x00000010

◆ CAN_F8R1_FB5

#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk

Filter bit 5

◆ CAN_F8R1_FB5_Msk

#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)

0x00000020

◆ CAN_F8R1_FB6

#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk

Filter bit 6

◆ CAN_F8R1_FB6_Msk

#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)

0x00000040

◆ CAN_F8R1_FB7

#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk

Filter bit 7

◆ CAN_F8R1_FB7_Msk

#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)

0x00000080

◆ CAN_F8R1_FB8

#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk

Filter bit 8

◆ CAN_F8R1_FB8_Msk

#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)

0x00000100

◆ CAN_F8R1_FB9

#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk

Filter bit 9

◆ CAN_F8R1_FB9_Msk

#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)

0x00000200

◆ CAN_F8R2_FB0

#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk

Filter bit 0

◆ CAN_F8R2_FB0_Msk

#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)

0x00000001

◆ CAN_F8R2_FB1

#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk

Filter bit 1

◆ CAN_F8R2_FB10

#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk

Filter bit 10

◆ CAN_F8R2_FB10_Msk

#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)

0x00000400

◆ CAN_F8R2_FB11

#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk

Filter bit 11

◆ CAN_F8R2_FB11_Msk

#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)

0x00000800

◆ CAN_F8R2_FB12

#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk

Filter bit 12

◆ CAN_F8R2_FB12_Msk

#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)

0x00001000

◆ CAN_F8R2_FB13

#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk

Filter bit 13

◆ CAN_F8R2_FB13_Msk

#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)

0x00002000

◆ CAN_F8R2_FB14

#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk

Filter bit 14

◆ CAN_F8R2_FB14_Msk

#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)

0x00004000

◆ CAN_F8R2_FB15

#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk

Filter bit 15

◆ CAN_F8R2_FB15_Msk

#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)

0x00008000

◆ CAN_F8R2_FB16

#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk

Filter bit 16

◆ CAN_F8R2_FB16_Msk

#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)

0x00010000

◆ CAN_F8R2_FB17

#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk

Filter bit 17

◆ CAN_F8R2_FB17_Msk

#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)

0x00020000

◆ CAN_F8R2_FB18

#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk

Filter bit 18

◆ CAN_F8R2_FB18_Msk

#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)

0x00040000

◆ CAN_F8R2_FB19

#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk

Filter bit 19

◆ CAN_F8R2_FB19_Msk

#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)

0x00080000

◆ CAN_F8R2_FB1_Msk

#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)

0x00000002

◆ CAN_F8R2_FB2

#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk

Filter bit 2

◆ CAN_F8R2_FB20

#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk

Filter bit 20

◆ CAN_F8R2_FB20_Msk

#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)

0x00100000

◆ CAN_F8R2_FB21

#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk

Filter bit 21

◆ CAN_F8R2_FB21_Msk

#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)

0x00200000

◆ CAN_F8R2_FB22

#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk

Filter bit 22

◆ CAN_F8R2_FB22_Msk

#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)

0x00400000

◆ CAN_F8R2_FB23

#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk

Filter bit 23

◆ CAN_F8R2_FB23_Msk

#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)

0x00800000

◆ CAN_F8R2_FB24

#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk

Filter bit 24

◆ CAN_F8R2_FB24_Msk

#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)

0x01000000

◆ CAN_F8R2_FB25

#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk

Filter bit 25

◆ CAN_F8R2_FB25_Msk

#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)

0x02000000

◆ CAN_F8R2_FB26

#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk

Filter bit 26

◆ CAN_F8R2_FB26_Msk

#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)

0x04000000

◆ CAN_F8R2_FB27

#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk

Filter bit 27

◆ CAN_F8R2_FB27_Msk

#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)

0x08000000

◆ CAN_F8R2_FB28

#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk

Filter bit 28

◆ CAN_F8R2_FB28_Msk

#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)

0x10000000

◆ CAN_F8R2_FB29

#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk

Filter bit 29

◆ CAN_F8R2_FB29_Msk

#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)

0x20000000

◆ CAN_F8R2_FB2_Msk

#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)

0x00000004

◆ CAN_F8R2_FB3

#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk

Filter bit 3

◆ CAN_F8R2_FB30

#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk

Filter bit 30

◆ CAN_F8R2_FB30_Msk

#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)

0x40000000

◆ CAN_F8R2_FB31

#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk

Filter bit 31

◆ CAN_F8R2_FB31_Msk

#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)

0x80000000

◆ CAN_F8R2_FB3_Msk

#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)

0x00000008

◆ CAN_F8R2_FB4

#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk

Filter bit 4

◆ CAN_F8R2_FB4_Msk

#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)

0x00000010

◆ CAN_F8R2_FB5

#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk

Filter bit 5

◆ CAN_F8R2_FB5_Msk

#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)

0x00000020

◆ CAN_F8R2_FB6

#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk

Filter bit 6

◆ CAN_F8R2_FB6_Msk

#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)

0x00000040

◆ CAN_F8R2_FB7

#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk

Filter bit 7

◆ CAN_F8R2_FB7_Msk

#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)

0x00000080

◆ CAN_F8R2_FB8

#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk

Filter bit 8

◆ CAN_F8R2_FB8_Msk

#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)

0x00000100

◆ CAN_F8R2_FB9

#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk

Filter bit 9

◆ CAN_F8R2_FB9_Msk

#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)

0x00000200

◆ CAN_F9R1_FB0

#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk

Filter bit 0

◆ CAN_F9R1_FB0_Msk

#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)

0x00000001

◆ CAN_F9R1_FB1

#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk

Filter bit 1

◆ CAN_F9R1_FB10

#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk

Filter bit 10

◆ CAN_F9R1_FB10_Msk

#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)

0x00000400

◆ CAN_F9R1_FB11

#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk

Filter bit 11

◆ CAN_F9R1_FB11_Msk

#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)

0x00000800

◆ CAN_F9R1_FB12

#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk

Filter bit 12

◆ CAN_F9R1_FB12_Msk

#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)

0x00001000

◆ CAN_F9R1_FB13

#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk

Filter bit 13

◆ CAN_F9R1_FB13_Msk

#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)

0x00002000

◆ CAN_F9R1_FB14

#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk

Filter bit 14

◆ CAN_F9R1_FB14_Msk

#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)

0x00004000

◆ CAN_F9R1_FB15

#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk

Filter bit 15

◆ CAN_F9R1_FB15_Msk

#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)

0x00008000

◆ CAN_F9R1_FB16

#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk

Filter bit 16

◆ CAN_F9R1_FB16_Msk

#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)

0x00010000

◆ CAN_F9R1_FB17

#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk

Filter bit 17

◆ CAN_F9R1_FB17_Msk

#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)

0x00020000

◆ CAN_F9R1_FB18

#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk

Filter bit 18

◆ CAN_F9R1_FB18_Msk

#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)

0x00040000

◆ CAN_F9R1_FB19

#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk

Filter bit 19

◆ CAN_F9R1_FB19_Msk

#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)

0x00080000

◆ CAN_F9R1_FB1_Msk

#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)

0x00000002

◆ CAN_F9R1_FB2

#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk

Filter bit 2

◆ CAN_F9R1_FB20

#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk

Filter bit 20

◆ CAN_F9R1_FB20_Msk

#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)

0x00100000

◆ CAN_F9R1_FB21

#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk

Filter bit 21

◆ CAN_F9R1_FB21_Msk

#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)

0x00200000

◆ CAN_F9R1_FB22

#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk

Filter bit 22

◆ CAN_F9R1_FB22_Msk

#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)

0x00400000

◆ CAN_F9R1_FB23

#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk

Filter bit 23

◆ CAN_F9R1_FB23_Msk

#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)

0x00800000

◆ CAN_F9R1_FB24

#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk

Filter bit 24

◆ CAN_F9R1_FB24_Msk

#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)

0x01000000

◆ CAN_F9R1_FB25

#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk

Filter bit 25

◆ CAN_F9R1_FB25_Msk

#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)

0x02000000

◆ CAN_F9R1_FB26

#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk

Filter bit 26

◆ CAN_F9R1_FB26_Msk

#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)

0x04000000

◆ CAN_F9R1_FB27

#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk

Filter bit 27

◆ CAN_F9R1_FB27_Msk

#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)

0x08000000

◆ CAN_F9R1_FB28

#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk

Filter bit 28

◆ CAN_F9R1_FB28_Msk

#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)

0x10000000

◆ CAN_F9R1_FB29

#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk

Filter bit 29

◆ CAN_F9R1_FB29_Msk

#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)

0x20000000

◆ CAN_F9R1_FB2_Msk

#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)

0x00000004

◆ CAN_F9R1_FB3

#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk

Filter bit 3

◆ CAN_F9R1_FB30

#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk

Filter bit 30

◆ CAN_F9R1_FB30_Msk

#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)

0x40000000

◆ CAN_F9R1_FB31

#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk

Filter bit 31

◆ CAN_F9R1_FB31_Msk

#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)

0x80000000

◆ CAN_F9R1_FB3_Msk

#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)

0x00000008

◆ CAN_F9R1_FB4

#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk

Filter bit 4

◆ CAN_F9R1_FB4_Msk

#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)

0x00000010

◆ CAN_F9R1_FB5

#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk

Filter bit 5

◆ CAN_F9R1_FB5_Msk

#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)

0x00000020

◆ CAN_F9R1_FB6

#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk

Filter bit 6

◆ CAN_F9R1_FB6_Msk

#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)

0x00000040

◆ CAN_F9R1_FB7

#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk

Filter bit 7

◆ CAN_F9R1_FB7_Msk

#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)

0x00000080

◆ CAN_F9R1_FB8

#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk

Filter bit 8

◆ CAN_F9R1_FB8_Msk

#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)

0x00000100

◆ CAN_F9R1_FB9

#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk

Filter bit 9

◆ CAN_F9R1_FB9_Msk

#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)

0x00000200

◆ CAN_F9R2_FB0

#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk

Filter bit 0

◆ CAN_F9R2_FB0_Msk

#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)

0x00000001

◆ CAN_F9R2_FB1

#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk

Filter bit 1

◆ CAN_F9R2_FB10

#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk

Filter bit 10

◆ CAN_F9R2_FB10_Msk

#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)

0x00000400

◆ CAN_F9R2_FB11

#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk

Filter bit 11

◆ CAN_F9R2_FB11_Msk

#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)

0x00000800

◆ CAN_F9R2_FB12

#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk

Filter bit 12

◆ CAN_F9R2_FB12_Msk

#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)

0x00001000

◆ CAN_F9R2_FB13

#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk

Filter bit 13

◆ CAN_F9R2_FB13_Msk

#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)

0x00002000

◆ CAN_F9R2_FB14

#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk

Filter bit 14

◆ CAN_F9R2_FB14_Msk

#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)

0x00004000

◆ CAN_F9R2_FB15

#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk

Filter bit 15

◆ CAN_F9R2_FB15_Msk

#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)

0x00008000

◆ CAN_F9R2_FB16

#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk

Filter bit 16

◆ CAN_F9R2_FB16_Msk

#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)

0x00010000

◆ CAN_F9R2_FB17

#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk

Filter bit 17

◆ CAN_F9R2_FB17_Msk

#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)

0x00020000

◆ CAN_F9R2_FB18

#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk

Filter bit 18

◆ CAN_F9R2_FB18_Msk

#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)

0x00040000

◆ CAN_F9R2_FB19

#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk

Filter bit 19

◆ CAN_F9R2_FB19_Msk

#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)

0x00080000

◆ CAN_F9R2_FB1_Msk

#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)

0x00000002

◆ CAN_F9R2_FB2

#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk

Filter bit 2

◆ CAN_F9R2_FB20

#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk

Filter bit 20

◆ CAN_F9R2_FB20_Msk

#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)

0x00100000

◆ CAN_F9R2_FB21

#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk

Filter bit 21

◆ CAN_F9R2_FB21_Msk

#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)

0x00200000

◆ CAN_F9R2_FB22

#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk

Filter bit 22

◆ CAN_F9R2_FB22_Msk

#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)

0x00400000

◆ CAN_F9R2_FB23

#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk

Filter bit 23

◆ CAN_F9R2_FB23_Msk

#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)

0x00800000

◆ CAN_F9R2_FB24

#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk

Filter bit 24

◆ CAN_F9R2_FB24_Msk

#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)

0x01000000

◆ CAN_F9R2_FB25

#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk

Filter bit 25

◆ CAN_F9R2_FB25_Msk

#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)

0x02000000

◆ CAN_F9R2_FB26

#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk

Filter bit 26

◆ CAN_F9R2_FB26_Msk

#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)

0x04000000

◆ CAN_F9R2_FB27

#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk

Filter bit 27

◆ CAN_F9R2_FB27_Msk

#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)

0x08000000

◆ CAN_F9R2_FB28

#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk

Filter bit 28

◆ CAN_F9R2_FB28_Msk

#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)

0x10000000

◆ CAN_F9R2_FB29

#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk

Filter bit 29

◆ CAN_F9R2_FB29_Msk

#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)

0x20000000

◆ CAN_F9R2_FB2_Msk

#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)

0x00000004

◆ CAN_F9R2_FB3

#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk

Filter bit 3

◆ CAN_F9R2_FB30

#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk

Filter bit 30

◆ CAN_F9R2_FB30_Msk

#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)

0x40000000

◆ CAN_F9R2_FB31

#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk

Filter bit 31

◆ CAN_F9R2_FB31_Msk

#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)

0x80000000

◆ CAN_F9R2_FB3_Msk

#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)

0x00000008

◆ CAN_F9R2_FB4

#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk

Filter bit 4

◆ CAN_F9R2_FB4_Msk

#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)

0x00000010

◆ CAN_F9R2_FB5

#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk

Filter bit 5

◆ CAN_F9R2_FB5_Msk

#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)

0x00000020

◆ CAN_F9R2_FB6

#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk

Filter bit 6

◆ CAN_F9R2_FB6_Msk

#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)

0x00000040

◆ CAN_F9R2_FB7

#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk

Filter bit 7

◆ CAN_F9R2_FB7_Msk

#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)

0x00000080

◆ CAN_F9R2_FB8

#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk

Filter bit 8

◆ CAN_F9R2_FB8_Msk

#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)

0x00000100

◆ CAN_F9R2_FB9

#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk

Filter bit 9

◆ CAN_F9R2_FB9_Msk

#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)

0x00000200

◆ CAN_FA1R_FACT

#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk

Filter Active

◆ CAN_FA1R_FACT0

#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk

Filter Active bit 0

◆ CAN_FA1R_FACT0_Msk

#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)

0x00000001

◆ CAN_FA1R_FACT1

#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk

Filter Active bit 1

◆ CAN_FA1R_FACT10

#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk

Filter Active bit 10

◆ CAN_FA1R_FACT10_Msk

#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)

0x00000400

◆ CAN_FA1R_FACT11

#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk

Filter Active bit 11

◆ CAN_FA1R_FACT11_Msk

#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)

0x00000800

◆ CAN_FA1R_FACT12

#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk

Filter Active bit 12

◆ CAN_FA1R_FACT12_Msk

#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)

0x00001000

◆ CAN_FA1R_FACT13

#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk

Filter Active bit 13

◆ CAN_FA1R_FACT13_Msk

#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)

0x00002000

◆ CAN_FA1R_FACT14

#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk

Filter Active bit 14

◆ CAN_FA1R_FACT14_Msk

#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)

0x00004000

◆ CAN_FA1R_FACT15

#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk

Filter Active bit 15

◆ CAN_FA1R_FACT15_Msk

#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)

0x00008000

◆ CAN_FA1R_FACT16

#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk

Filter Active bit 16

◆ CAN_FA1R_FACT16_Msk

#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)

0x00010000

◆ CAN_FA1R_FACT17

#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk

Filter Active bit 17

◆ CAN_FA1R_FACT17_Msk

#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)

0x00020000

◆ CAN_FA1R_FACT18

#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk

Filter Active bit 18

◆ CAN_FA1R_FACT18_Msk

#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)

0x00040000

◆ CAN_FA1R_FACT19

#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk

Filter Active bit 19

◆ CAN_FA1R_FACT19_Msk

#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)

0x00080000

◆ CAN_FA1R_FACT1_Msk

#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)

0x00000002

◆ CAN_FA1R_FACT2

#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk

Filter Active bit 2

◆ CAN_FA1R_FACT20

#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk

Filter Active bit 20

◆ CAN_FA1R_FACT20_Msk

#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)

0x00100000

◆ CAN_FA1R_FACT21

#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk

Filter Active bit 21

◆ CAN_FA1R_FACT21_Msk

#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)

0x00200000

◆ CAN_FA1R_FACT22

#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk

Filter Active bit 22

◆ CAN_FA1R_FACT22_Msk

#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)

0x00400000

◆ CAN_FA1R_FACT23

#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk

Filter Active bit 23

◆ CAN_FA1R_FACT23_Msk

#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)

0x00800000

◆ CAN_FA1R_FACT24

#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk

Filter Active bit 24

◆ CAN_FA1R_FACT24_Msk

#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)

0x01000000

◆ CAN_FA1R_FACT25

#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk

Filter Active bit 25

◆ CAN_FA1R_FACT25_Msk

#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)

0x02000000

◆ CAN_FA1R_FACT26

#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk

Filter Active bit 26

◆ CAN_FA1R_FACT26_Msk

#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)

0x04000000

◆ CAN_FA1R_FACT27

#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk

Filter Active bit 27

◆ CAN_FA1R_FACT27_Msk

#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)

0x08000000

◆ CAN_FA1R_FACT2_Msk

#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)

0x00000004

◆ CAN_FA1R_FACT3

#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk

Filter Active bit 3

◆ CAN_FA1R_FACT3_Msk

#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)

0x00000008

◆ CAN_FA1R_FACT4

#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk

Filter Active bit 4

◆ CAN_FA1R_FACT4_Msk

#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)

0x00000010

◆ CAN_FA1R_FACT5

#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk

Filter Active bit 5

◆ CAN_FA1R_FACT5_Msk

#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)

0x00000020

◆ CAN_FA1R_FACT6

#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk

Filter Active bit 6

◆ CAN_FA1R_FACT6_Msk

#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)

0x00000040

◆ CAN_FA1R_FACT7

#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk

Filter Active bit 7

◆ CAN_FA1R_FACT7_Msk

#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)

0x00000080

◆ CAN_FA1R_FACT8

#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk

Filter Active bit 8

◆ CAN_FA1R_FACT8_Msk

#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)

0x00000100

◆ CAN_FA1R_FACT9

#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk

Filter Active bit 9

◆ CAN_FA1R_FACT9_Msk

#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)

0x00000200

◆ CAN_FA1R_FACT_Msk

#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)

0x0FFFFFFF

◆ CAN_FFA1R_FFA

#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk

Filter FIFO Assignment

◆ CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk

Filter FIFO Assignment bit 0

◆ CAN_FFA1R_FFA0_Msk

#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)

0x00000001

◆ CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk

Filter FIFO Assignment bit 1

◆ CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk

Filter FIFO Assignment bit 10

◆ CAN_FFA1R_FFA10_Msk

#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)

0x00000400

◆ CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk

Filter FIFO Assignment bit 11

◆ CAN_FFA1R_FFA11_Msk

#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)

0x00000800

◆ CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk

Filter FIFO Assignment bit 12

◆ CAN_FFA1R_FFA12_Msk

#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)

0x00001000

◆ CAN_FFA1R_FFA13

#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk

Filter FIFO Assignment bit 13

◆ CAN_FFA1R_FFA13_Msk

#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)

0x00002000

◆ CAN_FFA1R_FFA14

#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk

Filter FIFO Assignment bit 14

◆ CAN_FFA1R_FFA14_Msk

#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)

0x00004000

◆ CAN_FFA1R_FFA15

#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk

Filter FIFO Assignment bit 15

◆ CAN_FFA1R_FFA15_Msk

#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)

0x00008000

◆ CAN_FFA1R_FFA16

#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk

Filter FIFO Assignment bit 16

◆ CAN_FFA1R_FFA16_Msk

#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)

0x00010000

◆ CAN_FFA1R_FFA17

#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk

Filter FIFO Assignment bit 17

◆ CAN_FFA1R_FFA17_Msk

#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)

0x00020000

◆ CAN_FFA1R_FFA18

#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk

Filter FIFO Assignment bit 18

◆ CAN_FFA1R_FFA18_Msk

#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)

0x00040000

◆ CAN_FFA1R_FFA19

#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk

Filter FIFO Assignment bit 19

◆ CAN_FFA1R_FFA19_Msk

#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)

0x00080000

◆ CAN_FFA1R_FFA1_Msk

#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)

0x00000002

◆ CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk

Filter FIFO Assignment bit 2

◆ CAN_FFA1R_FFA20

#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk

Filter FIFO Assignment bit 20

◆ CAN_FFA1R_FFA20_Msk

#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)

0x00100000

◆ CAN_FFA1R_FFA21

#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk

Filter FIFO Assignment bit 21

◆ CAN_FFA1R_FFA21_Msk

#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)

0x00200000

◆ CAN_FFA1R_FFA22

#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk

Filter FIFO Assignment bit 22

◆ CAN_FFA1R_FFA22_Msk

#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)

0x00400000

◆ CAN_FFA1R_FFA23

#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk

Filter FIFO Assignment bit 23

◆ CAN_FFA1R_FFA23_Msk

#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)

0x00800000

◆ CAN_FFA1R_FFA24

#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk

Filter FIFO Assignment bit 24

◆ CAN_FFA1R_FFA24_Msk

#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)

0x01000000

◆ CAN_FFA1R_FFA25

#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk

Filter FIFO Assignment bit 25

◆ CAN_FFA1R_FFA25_Msk

#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)

0x02000000

◆ CAN_FFA1R_FFA26

#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk

Filter FIFO Assignment bit 26

◆ CAN_FFA1R_FFA26_Msk

#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)

0x04000000

◆ CAN_FFA1R_FFA27

#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk

Filter FIFO Assignment bit 27

◆ CAN_FFA1R_FFA27_Msk

#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)

0x08000000

◆ CAN_FFA1R_FFA2_Msk

#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)

0x00000004

◆ CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk

Filter FIFO Assignment bit 3

◆ CAN_FFA1R_FFA3_Msk

#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)

0x00000008

◆ CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk

Filter FIFO Assignment bit 4

◆ CAN_FFA1R_FFA4_Msk

#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)

0x00000010

◆ CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk

Filter FIFO Assignment bit 5

◆ CAN_FFA1R_FFA5_Msk

#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)

0x00000020

◆ CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk

Filter FIFO Assignment bit 6

◆ CAN_FFA1R_FFA6_Msk

#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)

0x00000040

◆ CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk

Filter FIFO Assignment bit 7

◆ CAN_FFA1R_FFA7_Msk

#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)

0x00000080

◆ CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk

Filter FIFO Assignment bit 8

◆ CAN_FFA1R_FFA8_Msk

#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)

0x00000100

◆ CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk

Filter FIFO Assignment bit 9

◆ CAN_FFA1R_FFA9_Msk

#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)

0x00000200

◆ CAN_FFA1R_FFA_Msk

#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)

0x0FFFFFFF

◆ CAN_FM1R_FBM

#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk

Filter Mode

◆ CAN_FM1R_FBM0

#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk

Filter Init Mode bit 0

◆ CAN_FM1R_FBM0_Msk

#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)

0x00000001

◆ CAN_FM1R_FBM1

#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk

Filter Init Mode bit 1

◆ CAN_FM1R_FBM10

#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk

Filter Init Mode bit 10

◆ CAN_FM1R_FBM10_Msk

#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)

0x00000400

◆ CAN_FM1R_FBM11

#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk

Filter Init Mode bit 11

◆ CAN_FM1R_FBM11_Msk

#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)

0x00000800

◆ CAN_FM1R_FBM12

#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk

Filter Init Mode bit 12

◆ CAN_FM1R_FBM12_Msk

#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)

0x00001000

◆ CAN_FM1R_FBM13

#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk

Filter Init Mode bit 13

◆ CAN_FM1R_FBM13_Msk

#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)

0x00002000

◆ CAN_FM1R_FBM14

#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk

Filter Init Mode bit 14

◆ CAN_FM1R_FBM14_Msk

#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)

0x00004000

◆ CAN_FM1R_FBM15

#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk

Filter Init Mode bit 15

◆ CAN_FM1R_FBM15_Msk

#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)

0x00008000

◆ CAN_FM1R_FBM16

#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk

Filter Init Mode bit 16

◆ CAN_FM1R_FBM16_Msk

#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)

0x00010000

◆ CAN_FM1R_FBM17

#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk

Filter Init Mode bit 17

◆ CAN_FM1R_FBM17_Msk

#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)

0x00020000

◆ CAN_FM1R_FBM18

#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk

Filter Init Mode bit 18

◆ CAN_FM1R_FBM18_Msk

#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)

0x00040000

◆ CAN_FM1R_FBM19

#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk

Filter Init Mode bit 19

◆ CAN_FM1R_FBM19_Msk

#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)

0x00080000

◆ CAN_FM1R_FBM1_Msk

#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)

0x00000002

◆ CAN_FM1R_FBM2

#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk

Filter Init Mode bit 2

◆ CAN_FM1R_FBM20

#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk

Filter Init Mode bit 20

◆ CAN_FM1R_FBM20_Msk

#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)

0x00100000

◆ CAN_FM1R_FBM21

#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk

Filter Init Mode bit 21

◆ CAN_FM1R_FBM21_Msk

#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)

0x00200000

◆ CAN_FM1R_FBM22

#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk

Filter Init Mode bit 22

◆ CAN_FM1R_FBM22_Msk

#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)

0x00400000

◆ CAN_FM1R_FBM23

#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk

Filter Init Mode bit 23

◆ CAN_FM1R_FBM23_Msk

#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)

0x00800000

◆ CAN_FM1R_FBM24

#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk

Filter Init Mode bit 24

◆ CAN_FM1R_FBM24_Msk

#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)

0x01000000

◆ CAN_FM1R_FBM25

#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk

Filter Init Mode bit 25

◆ CAN_FM1R_FBM25_Msk

#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)

0x02000000

◆ CAN_FM1R_FBM26

#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk

Filter Init Mode bit 26

◆ CAN_FM1R_FBM26_Msk

#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)

0x04000000

◆ CAN_FM1R_FBM27

#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk

Filter Init Mode bit 27

◆ CAN_FM1R_FBM27_Msk

#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)

0x08000000

◆ CAN_FM1R_FBM2_Msk

#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)

0x00000004

◆ CAN_FM1R_FBM3

#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk

Filter Init Mode bit 3

◆ CAN_FM1R_FBM3_Msk

#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)

0x00000008

◆ CAN_FM1R_FBM4

#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk

Filter Init Mode bit 4

◆ CAN_FM1R_FBM4_Msk

#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)

0x00000010

◆ CAN_FM1R_FBM5

#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk

Filter Init Mode bit 5

◆ CAN_FM1R_FBM5_Msk

#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)

0x00000020

◆ CAN_FM1R_FBM6

#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk

Filter Init Mode bit 6

◆ CAN_FM1R_FBM6_Msk

#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)

0x00000040

◆ CAN_FM1R_FBM7

#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk

Filter Init Mode bit 7

◆ CAN_FM1R_FBM7_Msk

#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)

0x00000080

◆ CAN_FM1R_FBM8

#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk

Filter Init Mode bit 8

◆ CAN_FM1R_FBM8_Msk

#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)

0x00000100

◆ CAN_FM1R_FBM9

#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk

Filter Init Mode bit 9

◆ CAN_FM1R_FBM9_Msk

#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)

0x00000200

◆ CAN_FM1R_FBM_Msk

#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)

0x0FFFFFFF

◆ CAN_FMR_CAN2SB

#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk

CAN2 start bank

◆ CAN_FMR_CAN2SB_Msk

#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)

0x00003F00

◆ CAN_FMR_FINIT

#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk

Filter Init Mode

◆ CAN_FMR_FINIT_Msk

#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)

0x00000001

◆ CAN_FS1R_FSC

#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk

Filter Scale Configuration

◆ CAN_FS1R_FSC0

#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk

Filter Scale Configuration bit 0

◆ CAN_FS1R_FSC0_Msk

#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)

0x00000001

◆ CAN_FS1R_FSC1

#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk

Filter Scale Configuration bit 1

◆ CAN_FS1R_FSC10

#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk

Filter Scale Configuration bit 10

◆ CAN_FS1R_FSC10_Msk

#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)

0x00000400

◆ CAN_FS1R_FSC11

#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk

Filter Scale Configuration bit 11

◆ CAN_FS1R_FSC11_Msk

#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)

0x00000800

◆ CAN_FS1R_FSC12

#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk

Filter Scale Configuration bit 12

◆ CAN_FS1R_FSC12_Msk

#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)

0x00001000

◆ CAN_FS1R_FSC13

#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk

Filter Scale Configuration bit 13

◆ CAN_FS1R_FSC13_Msk

#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)

0x00002000

◆ CAN_FS1R_FSC14

#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk

Filter Scale Configuration bit 14

◆ CAN_FS1R_FSC14_Msk

#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)

0x00004000

◆ CAN_FS1R_FSC15

#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk

Filter Scale Configuration bit 15

◆ CAN_FS1R_FSC15_Msk

#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)

0x00008000

◆ CAN_FS1R_FSC16

#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk

Filter Scale Configuration bit 16

◆ CAN_FS1R_FSC16_Msk

#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)

0x00010000

◆ CAN_FS1R_FSC17

#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk

Filter Scale Configuration bit 17

◆ CAN_FS1R_FSC17_Msk

#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)

0x00020000

◆ CAN_FS1R_FSC18

#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk

Filter Scale Configuration bit 18

◆ CAN_FS1R_FSC18_Msk

#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)

0x00040000

◆ CAN_FS1R_FSC19

#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk

Filter Scale Configuration bit 19

◆ CAN_FS1R_FSC19_Msk

#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)

0x00080000

◆ CAN_FS1R_FSC1_Msk

#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)

0x00000002

◆ CAN_FS1R_FSC2

#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk

Filter Scale Configuration bit 2

◆ CAN_FS1R_FSC20

#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk

Filter Scale Configuration bit 20

◆ CAN_FS1R_FSC20_Msk

#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)

0x00100000

◆ CAN_FS1R_FSC21

#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk

Filter Scale Configuration bit 21

◆ CAN_FS1R_FSC21_Msk

#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)

0x00200000

◆ CAN_FS1R_FSC22

#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk

Filter Scale Configuration bit 22

◆ CAN_FS1R_FSC22_Msk

#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)

0x00400000

◆ CAN_FS1R_FSC23

#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk

Filter Scale Configuration bit 23

◆ CAN_FS1R_FSC23_Msk

#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)

0x00800000

◆ CAN_FS1R_FSC24

#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk

Filter Scale Configuration bit 24

◆ CAN_FS1R_FSC24_Msk

#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)

0x01000000

◆ CAN_FS1R_FSC25

#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk

Filter Scale Configuration bit 25

◆ CAN_FS1R_FSC25_Msk

#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)

0x02000000

◆ CAN_FS1R_FSC26

#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk

Filter Scale Configuration bit 26

◆ CAN_FS1R_FSC26_Msk

#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)

0x04000000

◆ CAN_FS1R_FSC27

#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk

Filter Scale Configuration bit 27

◆ CAN_FS1R_FSC27_Msk

#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)

0x08000000

◆ CAN_FS1R_FSC2_Msk

#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)

0x00000004

◆ CAN_FS1R_FSC3

#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk

Filter Scale Configuration bit 3

◆ CAN_FS1R_FSC3_Msk

#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)

0x00000008

◆ CAN_FS1R_FSC4

#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk

Filter Scale Configuration bit 4

◆ CAN_FS1R_FSC4_Msk

#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)

0x00000010

◆ CAN_FS1R_FSC5

#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk

Filter Scale Configuration bit 5

◆ CAN_FS1R_FSC5_Msk

#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)

0x00000020

◆ CAN_FS1R_FSC6

#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk

Filter Scale Configuration bit 6

◆ CAN_FS1R_FSC6_Msk

#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)

0x00000040

◆ CAN_FS1R_FSC7

#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk

Filter Scale Configuration bit 7

◆ CAN_FS1R_FSC7_Msk

#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)

0x00000080

◆ CAN_FS1R_FSC8

#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk

Filter Scale Configuration bit 8

◆ CAN_FS1R_FSC8_Msk

#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)

0x00000100

◆ CAN_FS1R_FSC9

#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk

Filter Scale Configuration bit 9

◆ CAN_FS1R_FSC9_Msk

#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)

0x00000200

◆ CAN_FS1R_FSC_Msk

#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)

0x0FFFFFFF

◆ CAN_IER_BOFIE

#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk

Bus-Off Interrupt Enable

◆ CAN_IER_BOFIE_Msk

#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)

0x00000400

◆ CAN_IER_EPVIE

#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk

Error Passive Interrupt Enable

◆ CAN_IER_EPVIE_Msk

#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)

0x00000200

◆ CAN_IER_ERRIE

#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk

Error Interrupt Enable

◆ CAN_IER_ERRIE_Msk

#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)

0x00008000

◆ CAN_IER_EWGIE

#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk

Error Warning Interrupt Enable

◆ CAN_IER_EWGIE_Msk

#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)

0x00000100

◆ CAN_IER_FFIE0

#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk

FIFO Full Interrupt Enable

◆ CAN_IER_FFIE0_Msk

#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)

0x00000004

◆ CAN_IER_FFIE1

#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk

FIFO Full Interrupt Enable

◆ CAN_IER_FFIE1_Msk

#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)

0x00000020

◆ CAN_IER_FMPIE0

#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FMPIE0_Msk

#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)

0x00000002

◆ CAN_IER_FMPIE1

#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FMPIE1_Msk

#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)

0x00000010

◆ CAN_IER_FOVIE0

#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk

FIFO Overrun Interrupt Enable

◆ CAN_IER_FOVIE0_Msk

#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)

0x00000008

◆ CAN_IER_FOVIE1

#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk

FIFO Overrun Interrupt Enable

◆ CAN_IER_FOVIE1_Msk

#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)

0x00000040

◆ CAN_IER_LECIE

#define CAN_IER_LECIE CAN_IER_LECIE_Msk

Last Error Code Interrupt Enable

◆ CAN_IER_LECIE_Msk

#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)

0x00000800

◆ CAN_IER_SLKIE

#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk

Sleep Interrupt Enable

◆ CAN_IER_SLKIE_Msk

#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)

0x00020000

◆ CAN_IER_TMEIE

#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk

Transmit Mailbox Empty Interrupt Enable

◆ CAN_IER_TMEIE_Msk

#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)

0x00000001

◆ CAN_IER_WKUIE

#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk

Wakeup Interrupt Enable

◆ CAN_IER_WKUIE_Msk

#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)

0x00010000

◆ CAN_MCR_ABOM

#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk

Automatic Bus-Off Management

◆ CAN_MCR_ABOM_Msk

#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)

0x00000040

◆ CAN_MCR_AWUM

#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk

Automatic Wakeup Mode

◆ CAN_MCR_AWUM_Msk

#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)

0x00000020

◆ CAN_MCR_DBF

#define CAN_MCR_DBF CAN_MCR_DBF_Msk

bxCAN Debug freeze

◆ CAN_MCR_DBF_Msk

#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)

0x00010000

◆ CAN_MCR_INRQ

#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk

Initialization Request

◆ CAN_MCR_INRQ_Msk

#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)

0x00000001

◆ CAN_MCR_INRQ_Pos

#define CAN_MCR_INRQ_Pos (0U)

<CAN control and status registers

◆ CAN_MCR_NART

#define CAN_MCR_NART CAN_MCR_NART_Msk

No Automatic Retransmission

◆ CAN_MCR_NART_Msk

#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)

0x00000010

◆ CAN_MCR_RESET

#define CAN_MCR_RESET CAN_MCR_RESET_Msk

bxCAN software master reset

◆ CAN_MCR_RESET_Msk

#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)

0x00008000

◆ CAN_MCR_RFLM

#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk

Receive FIFO Locked Mode

◆ CAN_MCR_RFLM_Msk

#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)

0x00000008

◆ CAN_MCR_SLEEP

#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk

Sleep Mode Request

◆ CAN_MCR_SLEEP_Msk

#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)

0x00000002

◆ CAN_MCR_TTCM

#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk

Time Triggered Communication Mode

◆ CAN_MCR_TTCM_Msk

#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)

0x00000080

◆ CAN_MCR_TXFP

#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk

Transmit FIFO Priority

◆ CAN_MCR_TXFP_Msk

#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)

0x00000004

◆ CAN_MSR_ERRI

#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk

Error Interrupt

◆ CAN_MSR_ERRI_Msk

#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)

0x00000004

◆ CAN_MSR_INAK

#define CAN_MSR_INAK CAN_MSR_INAK_Msk

Initialization Acknowledge

◆ CAN_MSR_INAK_Msk

#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)

0x00000001

◆ CAN_MSR_RX

#define CAN_MSR_RX CAN_MSR_RX_Msk

CAN Rx Signal

◆ CAN_MSR_RX_Msk

#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)

0x00000800

◆ CAN_MSR_RXM

#define CAN_MSR_RXM CAN_MSR_RXM_Msk

Receive Mode

◆ CAN_MSR_RXM_Msk

#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)

0x00000200

◆ CAN_MSR_SAMP

#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk

Last Sample Point

◆ CAN_MSR_SAMP_Msk

#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)

0x00000400

◆ CAN_MSR_SLAK

#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk

Sleep Acknowledge

◆ CAN_MSR_SLAK_Msk

#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)

0x00000002

◆ CAN_MSR_SLAKI

#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk

Sleep Acknowledge Interrupt

◆ CAN_MSR_SLAKI_Msk

#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)

0x00000010

◆ CAN_MSR_TXM

#define CAN_MSR_TXM CAN_MSR_TXM_Msk

Transmit Mode

◆ CAN_MSR_TXM_Msk

#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)

0x00000100

◆ CAN_MSR_WKUI

#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk

Wakeup Interrupt

◆ CAN_MSR_WKUI_Msk

#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)

0x00000008

◆ CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk

Data byte 4

◆ CAN_RDH0R_DATA4_Msk

#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)

0x000000FF

◆ CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk

Data byte 5

◆ CAN_RDH0R_DATA5_Msk

#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)

0x0000FF00

◆ CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk

Data byte 6

◆ CAN_RDH0R_DATA6_Msk

#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)

0x00FF0000

◆ CAN_RDH0R_DATA7

#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk

Data byte 7

◆ CAN_RDH0R_DATA7_Msk

#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)

0xFF000000

◆ CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk

Data byte 4

◆ CAN_RDH1R_DATA4_Msk

#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)

0x000000FF

◆ CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk

Data byte 5

◆ CAN_RDH1R_DATA5_Msk

#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)

0x0000FF00

◆ CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk

Data byte 6

◆ CAN_RDH1R_DATA6_Msk

#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)

0x00FF0000

◆ CAN_RDH1R_DATA7

#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk

Data byte 7 CAN filter registers

◆ CAN_RDH1R_DATA7_Msk

#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)

0xFF000000

◆ CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk

Data byte 0

◆ CAN_RDL0R_DATA0_Msk

#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)

0x000000FF

◆ CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk

Data byte 1

◆ CAN_RDL0R_DATA1_Msk

#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)

0x0000FF00

◆ CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk

Data byte 2

◆ CAN_RDL0R_DATA2_Msk

#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)

0x00FF0000

◆ CAN_RDL0R_DATA3

#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk

Data byte 3

◆ CAN_RDL0R_DATA3_Msk

#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)

0xFF000000

◆ CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk

Data byte 0

◆ CAN_RDL1R_DATA0_Msk

#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)

0x000000FF

◆ CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk

Data byte 1

◆ CAN_RDL1R_DATA1_Msk

#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)

0x0000FF00

◆ CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk

Data byte 2

◆ CAN_RDL1R_DATA2_Msk

#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)

0x00FF0000

◆ CAN_RDL1R_DATA3

#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk

Data byte 3

◆ CAN_RDL1R_DATA3_Msk

#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)

0xFF000000

◆ CAN_RDT0R_DLC

#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk

Data Length Code

◆ CAN_RDT0R_DLC_Msk

#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)

0x0000000F

◆ CAN_RDT0R_FMI

#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk

Filter Match Index

◆ CAN_RDT0R_FMI_Msk

#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)

0x0000FF00

◆ CAN_RDT0R_TIME

#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk

Message Time Stamp

◆ CAN_RDT0R_TIME_Msk

#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)

0xFFFF0000

◆ CAN_RDT1R_DLC

#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk

Data Length Code

◆ CAN_RDT1R_DLC_Msk

#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)

0x0000000F

◆ CAN_RDT1R_FMI

#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk

Filter Match Index

◆ CAN_RDT1R_FMI_Msk

#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)

0x0000FF00

◆ CAN_RDT1R_TIME

#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk

Message Time Stamp

◆ CAN_RDT1R_TIME_Msk

#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)

0xFFFF0000

◆ CAN_RF0R_FMP0

#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk

FIFO 0 Message Pending

◆ CAN_RF0R_FMP0_Msk

#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)

0x00000003

◆ CAN_RF0R_FOVR0

#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk

FIFO 0 Overrun

◆ CAN_RF0R_FOVR0_Msk

#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)

0x00000010

◆ CAN_RF0R_FULL0

#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk

FIFO 0 Full

◆ CAN_RF0R_FULL0_Msk

#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)

0x00000008

◆ CAN_RF0R_RFOM0

#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk

Release FIFO 0 Output Mailbox

◆ CAN_RF0R_RFOM0_Msk

#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)

0x00000020

◆ CAN_RF1R_FMP1

#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk

FIFO 1 Message Pending

◆ CAN_RF1R_FMP1_Msk

#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)

0x00000003

◆ CAN_RF1R_FOVR1

#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk

FIFO 1 Overrun

◆ CAN_RF1R_FOVR1_Msk

#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)

0x00000010

◆ CAN_RF1R_FULL1

#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk

FIFO 1 Full

◆ CAN_RF1R_FULL1_Msk

#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)

0x00000008

◆ CAN_RF1R_RFOM1

#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk

Release FIFO 1 Output Mailbox

◆ CAN_RF1R_RFOM1_Msk

#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)

0x00000020

◆ CAN_RI0R_EXID

#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk

Extended Identifier

◆ CAN_RI0R_EXID_Msk

#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)

0x001FFFF8

◆ CAN_RI0R_IDE

#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk

Identifier Extension

◆ CAN_RI0R_IDE_Msk

#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)

0x00000004

◆ CAN_RI0R_RTR

#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk

Remote Transmission Request

◆ CAN_RI0R_RTR_Msk

#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)

0x00000002

◆ CAN_RI0R_STID

#define CAN_RI0R_STID CAN_RI0R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_RI0R_STID_Msk

#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)

0xFFE00000

◆ CAN_RI1R_EXID

#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk

Extended identifier

◆ CAN_RI1R_EXID_Msk

#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)

0x001FFFF8

◆ CAN_RI1R_IDE

#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk

Identifier Extension

◆ CAN_RI1R_IDE_Msk

#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)

0x00000004

◆ CAN_RI1R_RTR

#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk

Remote Transmission Request

◆ CAN_RI1R_RTR_Msk

#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)

0x00000002

◆ CAN_RI1R_STID

#define CAN_RI1R_STID CAN_RI1R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_RI1R_STID_Msk

#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)

0xFFE00000

◆ CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk

Data byte 4

◆ CAN_TDH0R_DATA4_Msk

#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)

0x000000FF

◆ CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk

Data byte 5

◆ CAN_TDH0R_DATA5_Msk

#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk

Data byte 6

◆ CAN_TDH0R_DATA6_Msk

#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH0R_DATA7

#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk

Data byte 7

◆ CAN_TDH0R_DATA7_Msk

#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)

0xFF000000

◆ CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk

Data byte 4

◆ CAN_TDH1R_DATA4_Msk

#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)

0x000000FF

◆ CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk

Data byte 5

◆ CAN_TDH1R_DATA5_Msk

#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk

Data byte 6

◆ CAN_TDH1R_DATA6_Msk

#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH1R_DATA7

#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk

Data byte 7

◆ CAN_TDH1R_DATA7_Msk

#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)

0xFF000000

◆ CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk

Data byte 4

◆ CAN_TDH2R_DATA4_Msk

#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)

0x000000FF

◆ CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk

Data byte 5

◆ CAN_TDH2R_DATA5_Msk

#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk

Data byte 6

◆ CAN_TDH2R_DATA6_Msk

#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH2R_DATA7

#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk

Data byte 7

◆ CAN_TDH2R_DATA7_Msk

#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)

0xFF000000

◆ CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk

Data byte 0

◆ CAN_TDL0R_DATA0_Msk

#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)

0x000000FF

◆ CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk

Data byte 1

◆ CAN_TDL0R_DATA1_Msk

#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk

Data byte 2

◆ CAN_TDL0R_DATA2_Msk

#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL0R_DATA3

#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk

Data byte 3

◆ CAN_TDL0R_DATA3_Msk

#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)

0xFF000000

◆ CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk

Data byte 0

◆ CAN_TDL1R_DATA0_Msk

#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)

0x000000FF

◆ CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk

Data byte 1

◆ CAN_TDL1R_DATA1_Msk

#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk

Data byte 2

◆ CAN_TDL1R_DATA2_Msk

#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL1R_DATA3

#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk

Data byte 3

◆ CAN_TDL1R_DATA3_Msk

#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)

0xFF000000

◆ CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk

Data byte 0

◆ CAN_TDL2R_DATA0_Msk

#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)

0x000000FF

◆ CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk

Data byte 1

◆ CAN_TDL2R_DATA1_Msk

#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk

Data byte 2

◆ CAN_TDL2R_DATA2_Msk

#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL2R_DATA3

#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk

Data byte 3

◆ CAN_TDL2R_DATA3_Msk

#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)

0xFF000000

◆ CAN_TDT0R_DLC

#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk

Data Length Code

◆ CAN_TDT0R_DLC_Msk

#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)

0x0000000F

◆ CAN_TDT0R_TGT

#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk

Transmit Global Time

◆ CAN_TDT0R_TGT_Msk

#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)

0x00000100

◆ CAN_TDT0R_TIME

#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk

Message Time Stamp

◆ CAN_TDT0R_TIME_Msk

#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)

0xFFFF0000

◆ CAN_TDT1R_DLC

#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk

Data Length Code

◆ CAN_TDT1R_DLC_Msk

#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)

0x0000000F

◆ CAN_TDT1R_TGT

#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk

Transmit Global Time

◆ CAN_TDT1R_TGT_Msk

#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)

0x00000100

◆ CAN_TDT1R_TIME

#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk

Message Time Stamp

◆ CAN_TDT1R_TIME_Msk

#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)

0xFFFF0000

◆ CAN_TDT2R_DLC

#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk

Data Length Code

◆ CAN_TDT2R_DLC_Msk

#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)

0x0000000F

◆ CAN_TDT2R_TGT

#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk

Transmit Global Time

◆ CAN_TDT2R_TGT_Msk

#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)

0x00000100

◆ CAN_TDT2R_TIME

#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk

Message Time Stamp

◆ CAN_TDT2R_TIME_Msk

#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)

0xFFFF0000

◆ CAN_TI0R_EXID

#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk

Extended Identifier

◆ CAN_TI0R_EXID_Msk

#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)

0x001FFFF8

◆ CAN_TI0R_IDE

#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk

Identifier Extension

◆ CAN_TI0R_IDE_Msk

#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)

0x00000004

◆ CAN_TI0R_RTR

#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk

Remote Transmission Request

◆ CAN_TI0R_RTR_Msk

#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)

0x00000002

◆ CAN_TI0R_STID

#define CAN_TI0R_STID CAN_TI0R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI0R_STID_Msk

#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)

0xFFE00000

◆ CAN_TI0R_TXRQ

#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI0R_TXRQ_Msk

#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)

0x00000001

◆ CAN_TI1R_EXID

#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk

Extended Identifier

◆ CAN_TI1R_EXID_Msk

#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)

0x001FFFF8

◆ CAN_TI1R_IDE

#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk

Identifier Extension

◆ CAN_TI1R_IDE_Msk

#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)

0x00000004

◆ CAN_TI1R_RTR

#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk

Remote Transmission Request

◆ CAN_TI1R_RTR_Msk

#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)

0x00000002

◆ CAN_TI1R_STID

#define CAN_TI1R_STID CAN_TI1R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI1R_STID_Msk

#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)

0xFFE00000

◆ CAN_TI1R_TXRQ

#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI1R_TXRQ_Msk

#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)

0x00000001

◆ CAN_TI2R_EXID

#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk

Extended identifier

◆ CAN_TI2R_EXID_Msk

#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)

0x001FFFF8

◆ CAN_TI2R_IDE

#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk

Identifier Extension

◆ CAN_TI2R_IDE_Msk

#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)

0x00000004

◆ CAN_TI2R_RTR

#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk

Remote Transmission Request

◆ CAN_TI2R_RTR_Msk

#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)

0x00000002

◆ CAN_TI2R_STID

#define CAN_TI2R_STID CAN_TI2R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI2R_STID_Msk

#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)

0xFFE00000

◆ CAN_TI2R_TXRQ

#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI2R_TXRQ_Msk

#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)

0x00000001

◆ CAN_TSR_ABRQ0

#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk

Abort Request for Mailbox0

◆ CAN_TSR_ABRQ0_Msk

#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)

0x00000080

◆ CAN_TSR_ABRQ1

#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk

Abort Request for Mailbox 1

◆ CAN_TSR_ABRQ1_Msk

#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)

0x00008000

◆ CAN_TSR_ABRQ2

#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk

Abort Request for Mailbox 2

◆ CAN_TSR_ABRQ2_Msk

#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)

0x00800000

◆ CAN_TSR_ALST0

#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk

Arbitration Lost for Mailbox0

◆ CAN_TSR_ALST0_Msk

#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)

0x00000004

◆ CAN_TSR_ALST1

#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk

Arbitration Lost for Mailbox1

◆ CAN_TSR_ALST1_Msk

#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)

0x00000400

◆ CAN_TSR_ALST2

#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk

Arbitration Lost for mailbox 2

◆ CAN_TSR_ALST2_Msk

#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)

0x00040000

◆ CAN_TSR_CODE

#define CAN_TSR_CODE CAN_TSR_CODE_Msk

Mailbox Code

◆ CAN_TSR_CODE_Msk

#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)

0x03000000

◆ CAN_TSR_LOW

#define CAN_TSR_LOW CAN_TSR_LOW_Msk

LOW[2:0] bits

◆ CAN_TSR_LOW0

#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk

Lowest Priority Flag for Mailbox 0

◆ CAN_TSR_LOW0_Msk

#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)

0x20000000

◆ CAN_TSR_LOW1

#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk

Lowest Priority Flag for Mailbox 1

◆ CAN_TSR_LOW1_Msk

#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)

0x40000000

◆ CAN_TSR_LOW2

#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk

Lowest Priority Flag for Mailbox 2

◆ CAN_TSR_LOW2_Msk

#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)

0x80000000

◆ CAN_TSR_LOW_Msk

#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)

0xE0000000

◆ CAN_TSR_RQCP0

#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk

Request Completed Mailbox0

◆ CAN_TSR_RQCP0_Msk

#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)

0x00000001

◆ CAN_TSR_RQCP1

#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk

Request Completed Mailbox1

◆ CAN_TSR_RQCP1_Msk

#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)

0x00000100

◆ CAN_TSR_RQCP2

#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk

Request Completed Mailbox2

◆ CAN_TSR_RQCP2_Msk

#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)

0x00010000

◆ CAN_TSR_TERR0

#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk

Transmission Error of Mailbox0

◆ CAN_TSR_TERR0_Msk

#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)

0x00000008

◆ CAN_TSR_TERR1

#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk

Transmission Error of Mailbox1

◆ CAN_TSR_TERR1_Msk

#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)

0x00000800

◆ CAN_TSR_TERR2

#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk

Transmission Error of Mailbox 2

◆ CAN_TSR_TERR2_Msk

#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)

0x00080000

◆ CAN_TSR_TME

#define CAN_TSR_TME CAN_TSR_TME_Msk

TME[2:0] bits

◆ CAN_TSR_TME0

#define CAN_TSR_TME0 CAN_TSR_TME0_Msk

Transmit Mailbox 0 Empty

◆ CAN_TSR_TME0_Msk

#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)

0x04000000

◆ CAN_TSR_TME1

#define CAN_TSR_TME1 CAN_TSR_TME1_Msk

Transmit Mailbox 1 Empty

◆ CAN_TSR_TME1_Msk

#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)

0x08000000

◆ CAN_TSR_TME2

#define CAN_TSR_TME2 CAN_TSR_TME2_Msk

Transmit Mailbox 2 Empty

◆ CAN_TSR_TME2_Msk

#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)

0x10000000

◆ CAN_TSR_TME_Msk

#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)

0x1C000000

◆ CAN_TSR_TXOK0

#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk

Transmission OK of Mailbox0

◆ CAN_TSR_TXOK0_Msk

#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)

0x00000002

◆ CAN_TSR_TXOK1

#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk

Transmission OK of Mailbox1

◆ CAN_TSR_TXOK1_Msk

#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)

0x00000200

◆ CAN_TSR_TXOK2

#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk

Transmission OK of Mailbox 2

◆ CAN_TSR_TXOK2_Msk

#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)

0x00020000

◆ CRC_CR_RESET

#define CRC_CR_RESET CRC_CR_RESET_Msk

RESET bit

◆ CRC_CR_RESET_Msk

#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

0x00000001

◆ CRC_DR_DR

#define CRC_DR_DR CRC_DR_DR_Msk

Data register bits

◆ CRC_DR_DR_Msk

#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

0xFFFFFFFF

◆ CRC_IDR_IDR

#define CRC_IDR_IDR CRC_IDR_IDR_Msk

General-purpose 8-bit data register bits

◆ CRC_IDR_IDR_Msk

#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)

0x000000FF

◆ DAC_CHANNEL2_SUPPORT

#define DAC_CHANNEL2_SUPPORT

DAC feature available only on specific devices: availability of DAC channel 2

◆ DAC_CR_BOFF1

#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk

DAC channel1 output buffer disable

◆ DAC_CR_BOFF1_Msk

#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)

0x00000002

◆ DAC_CR_BOFF2

#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk

DAC channel2 output buffer disable

◆ DAC_CR_BOFF2_Msk

#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)

0x00020000

◆ DAC_CR_DMAEN1

#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

DAC channel1 DMA enable

◆ DAC_CR_DMAEN1_Msk

#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

0x00001000

◆ DAC_CR_DMAEN2

#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

DAC channel2 DMA enabled

◆ DAC_CR_DMAEN2_Msk

#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

0x10000000

◆ DAC_CR_DMAUDRIE1

#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

DAC channel1 DMA underrun interrupt enable

◆ DAC_CR_DMAUDRIE1_Msk

#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

0x00002000

◆ DAC_CR_DMAUDRIE2

#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

DAC channel2 DMA underrun interrupt enable

◆ DAC_CR_DMAUDRIE2_Msk

#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

0x20000000

◆ DAC_CR_EN1

#define DAC_CR_EN1 DAC_CR_EN1_Msk

DAC channel1 enable

◆ DAC_CR_EN1_Msk

#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

0x00000001

◆ DAC_CR_EN2

#define DAC_CR_EN2 DAC_CR_EN2_Msk

DAC channel2 enable

◆ DAC_CR_EN2_Msk

#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

0x00010000

◆ DAC_CR_MAMP1

#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

◆ DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

0x00000100

◆ DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

0x00000200

◆ DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

0x00000400

◆ DAC_CR_MAMP1_3

#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

0x00000800

◆ DAC_CR_MAMP1_Msk

#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

0x00000F00

◆ DAC_CR_MAMP2

#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

◆ DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

0x01000000

◆ DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

0x02000000

◆ DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

0x04000000

◆ DAC_CR_MAMP2_3

#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

0x08000000

◆ DAC_CR_MAMP2_Msk

#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

0x0F000000

◆ DAC_CR_TEN1

#define DAC_CR_TEN1 DAC_CR_TEN1_Msk

DAC channel1 Trigger enable

◆ DAC_CR_TEN1_Msk

#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

0x00000004

◆ DAC_CR_TEN2

#define DAC_CR_TEN2 DAC_CR_TEN2_Msk

DAC channel2 Trigger enable

◆ DAC_CR_TEN2_Msk

#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

0x00040000

◆ DAC_CR_TSEL1

#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

TSEL1[2:0] (DAC channel1 Trigger selection)

◆ DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

0x00000008

◆ DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

0x00000010

◆ DAC_CR_TSEL1_2

#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

0x00000020

◆ DAC_CR_TSEL1_Msk

#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)

0x00000038

◆ DAC_CR_TSEL2

#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

TSEL2[2:0] (DAC channel2 Trigger selection)

◆ DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

0x00080000

◆ DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

0x00100000

◆ DAC_CR_TSEL2_2

#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

0x00200000

◆ DAC_CR_TSEL2_Msk

#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)

0x00380000

◆ DAC_CR_WAVE1

#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

◆ DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

0x00000040

◆ DAC_CR_WAVE1_1

#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

0x00000080

◆ DAC_CR_WAVE1_Msk

#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

0x000000C0

◆ DAC_CR_WAVE2

#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

◆ DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

0x00400000

◆ DAC_CR_WAVE2_1

#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

0x00800000

◆ DAC_CR_WAVE2_Msk

#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

0x00C00000

◆ DAC_DHR12L1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12L1_DACC1DHR_Msk

#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12L2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12L2_DACC2DHR_Msk

#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

0x0000FFF0

◆ DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12LD_DACC1DHR_Msk

#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12LD_DACC2DHR

#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12LD_DACC2DHR_Msk

#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

0xFFF00000

◆ DAC_DHR12R1_DACC1DHR

#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12R1_DACC1DHR_Msk

#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12R2_DACC2DHR

#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12R2_DACC2DHR_Msk

#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

0x00000FFF

◆ DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12RD_DACC1DHR_Msk

#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12RD_DACC2DHR

#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12RD_DACC2DHR_Msk

#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

0x0FFF0000

◆ DAC_DHR8R1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8R1_DACC1DHR_Msk

#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8R2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8R2_DACC2DHR_Msk

#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

0x000000FF

◆ DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8RD_DACC1DHR_Msk

#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8RD_DACC2DHR

#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8RD_DACC2DHR_Msk

#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

0x0000FF00

◆ DAC_DOR1_DACC1DOR

#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

DAC channel1 data output

◆ DAC_DOR1_DACC1DOR_Msk

#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

0x00000FFF

◆ DAC_DOR2_DACC2DOR

#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

DAC channel2 data output

◆ DAC_DOR2_DACC2DOR_Msk

#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

0x00000FFF

◆ DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

DAC channel1 DMA underrun flag

◆ DAC_SR_DMAUDR1_Msk

#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

0x00002000

◆ DAC_SR_DMAUDR2

#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

DAC channel2 DMA underrun flag

◆ DAC_SR_DMAUDR2_Msk

#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

0x20000000

◆ DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

DAC channel1 software trigger

◆ DAC_SWTRIGR_SWTRIG1_Msk

#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

0x00000001

◆ DAC_SWTRIGR_SWTRIG2

#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

DAC channel2 software trigger

◆ DAC_SWTRIGR_SWTRIG2_Msk

#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

0x00000002

◆ DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)

0x02000000

◆ DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)

0x04000000

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)

0x00200000

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)

0x00400000

◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)

0x00800000

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)

0x00001000

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)

0x00000400

◆ DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)

0x00000040

◆ DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)

0x00000080

◆ DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)

0x00000100

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)

0x00000001

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)

0x00000002

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)

0x00000004

◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)

0x00000008

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)

0x00000010

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)

0x00000020

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)

0x00000800

◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)

0x00020000

◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)

0x00040000

◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)

0x00000001

◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)

0x00000002

◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)

0x00010000

◆ DBGMCU_CR_DBG_SLEEP_Msk

#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

0x00000001

◆ DBGMCU_CR_DBG_STANDBY_Msk

#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

0x00000004

◆ DBGMCU_CR_DBG_STOP_Msk

#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

0x00000002

◆ DBGMCU_CR_TRACE_IOEN_Msk

#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

0x00000020

◆ DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000040

◆ DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000080

◆ DBGMCU_CR_TRACE_MODE_Msk

#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

0x000000C0

◆ DBGMCU_IDCODE_DEV_ID_Msk

#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

0x00000FFF

◆ DBGMCU_IDCODE_REV_ID_Msk

#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

0xFFFF0000

◆ DCMI_CR_CAPTURE_Msk

#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)

0x00000001

◆ DCMI_CR_CM_Msk

#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)

0x00000002

◆ DCMI_CR_CRE_Msk

#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)

0x00001000

◆ DCMI_CR_CROP_Msk

#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)

0x00000004

◆ DCMI_CR_ENABLE_Msk

#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)

0x00004000

◆ DCMI_CR_ESS_Msk

#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)

0x00000010

◆ DCMI_CR_HSPOL_Msk

#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)

0x00000040

◆ DCMI_CR_JPEG_Msk

#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)

0x00000008

◆ DCMI_CR_PCKPOL_Msk

#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)

0x00000020

◆ DCMI_CR_VSPOL_Msk

#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)

0x00000080

◆ DCMI_CWSIZE_CAPCNT_Msk

#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)

0x00003FFF

◆ DCMI_CWSIZE_VLINE_Msk

#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)

0x3FFF0000

◆ DCMI_CWSTRT_HOFFCNT_Msk

#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)

0x00003FFF

◆ DCMI_CWSTRT_VST_Msk

#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)

0x1FFF0000

◆ DCMI_DR_BYTE0_Msk

#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)

0x000000FF

◆ DCMI_DR_BYTE1_Msk

#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)

0x0000FF00

◆ DCMI_DR_BYTE2_Msk

#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)

0x00FF0000

◆ DCMI_DR_BYTE3_Msk

#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)

0xFF000000

◆ DCMI_ESCR_FEC_Msk

#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)

0xFF000000

◆ DCMI_ESCR_FSC_Msk

#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)

0x000000FF

◆ DCMI_ESCR_LEC_Msk

#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)

0x00FF0000

◆ DCMI_ESCR_LSC_Msk

#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)

0x0000FF00

◆ DCMI_ESUR_FEU_Msk

#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)

0xFF000000

◆ DCMI_ESUR_FSU_Msk

#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)

0x000000FF

◆ DCMI_ESUR_LEU_Msk

#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)

0x00FF0000

◆ DCMI_ESUR_LSU_Msk

#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)

0x0000FF00

◆ DCMI_ICR_ERR_ISC_Msk

#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)

0x00000004

◆ DCMI_ICR_FRAME_ISC_Msk

#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)

0x00000001

◆ DCMI_ICR_LINE_ISC_Msk

#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)

0x00000010

◆ DCMI_ICR_OVR_ISC_Msk

#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)

0x00000002

◆ DCMI_ICR_VSYNC_ISC_Msk

#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)

0x00000008

◆ DCMI_IER_ERR_IE_Msk

#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)

0x00000004

◆ DCMI_IER_FRAME_IE_Msk

#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)

0x00000001

◆ DCMI_IER_LINE_IE_Msk

#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)

0x00000010

◆ DCMI_IER_OVR_IE_Msk

#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)

0x00000002

◆ DCMI_IER_VSYNC_IE_Msk

#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)

0x00000008

◆ DCMI_MIS_ERR_MIS_Msk

#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)

0x00000004

◆ DCMI_MIS_FRAME_MIS_Msk

#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)

0x00000001

◆ DCMI_MIS_LINE_MIS_Msk

#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)

0x00000010

◆ DCMI_MIS_OVR_MIS_Msk

#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)

0x00000002

◆ DCMI_MIS_VSYNC_MIS_Msk

#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)

0x00000008

◆ DCMI_RIS_ERR_RIS_Msk

#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)

0x00000004

◆ DCMI_RIS_FRAME_RIS_Msk

#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)

0x00000001

◆ DCMI_RIS_LINE_RIS_Msk

#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)

0x00000010

◆ DCMI_RIS_OVR_RIS_Msk

#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)

0x00000002

◆ DCMI_RIS_VSYNC_RIS_Msk

#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)

0x00000008

◆ DCMI_SR_FNE_Msk

#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)

0x00000004

◆ DCMI_SR_HSYNC_Msk

#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)

0x00000001

◆ DCMI_SR_VSYNC_Msk

#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)

0x00000002

◆ DMA_HIFCR_CDMEIF4_Msk

#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)

0x00000004

◆ DMA_HIFCR_CDMEIF5_Msk

#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)

0x00000100

◆ DMA_HIFCR_CDMEIF6_Msk

#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)

0x00040000

◆ DMA_HIFCR_CDMEIF7_Msk

#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)

0x01000000

◆ DMA_HIFCR_CFEIF4_Msk

#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)

0x00000001

◆ DMA_HIFCR_CFEIF5_Msk

#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)

0x00000040

◆ DMA_HIFCR_CFEIF6_Msk

#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)

0x00010000

◆ DMA_HIFCR_CFEIF7_Msk

#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)

0x00400000

◆ DMA_HIFCR_CHTIF4_Msk

#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)

0x00000010

◆ DMA_HIFCR_CHTIF5_Msk

#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)

0x00000400

◆ DMA_HIFCR_CHTIF6_Msk

#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)

0x00100000

◆ DMA_HIFCR_CHTIF7_Msk

#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)

0x04000000

◆ DMA_HIFCR_CTCIF4_Msk

#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)

0x00000020

◆ DMA_HIFCR_CTCIF5_Msk

#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)

0x00000800

◆ DMA_HIFCR_CTCIF6_Msk

#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)

0x00200000

◆ DMA_HIFCR_CTCIF7_Msk

#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)

0x08000000

◆ DMA_HIFCR_CTEIF4_Msk

#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)

0x00000008

◆ DMA_HIFCR_CTEIF5_Msk

#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)

0x00000200

◆ DMA_HIFCR_CTEIF6_Msk

#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)

0x00080000

◆ DMA_HIFCR_CTEIF7_Msk

#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)

0x02000000

◆ DMA_HISR_DMEIF4_Msk

#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)

0x00000004

◆ DMA_HISR_DMEIF5_Msk

#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)

0x00000100

◆ DMA_HISR_DMEIF6_Msk

#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)

0x00040000

◆ DMA_HISR_DMEIF7_Msk

#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)

0x01000000

◆ DMA_HISR_FEIF4_Msk

#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)

0x00000001

◆ DMA_HISR_FEIF5_Msk

#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)

0x00000040

◆ DMA_HISR_FEIF6_Msk

#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)

0x00010000

◆ DMA_HISR_FEIF7_Msk

#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)

0x00400000

◆ DMA_HISR_HTIF4_Msk

#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)

0x00000010

◆ DMA_HISR_HTIF5_Msk

#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)

0x00000400

◆ DMA_HISR_HTIF6_Msk

#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)

0x00100000

◆ DMA_HISR_HTIF7_Msk

#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)

0x04000000

◆ DMA_HISR_TCIF4_Msk

#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)

0x00000020

◆ DMA_HISR_TCIF5_Msk

#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)

0x00000800

◆ DMA_HISR_TCIF6_Msk

#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)

0x00200000

◆ DMA_HISR_TCIF7_Msk

#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)

0x08000000

◆ DMA_HISR_TEIF4_Msk

#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)

0x00000008

◆ DMA_HISR_TEIF5_Msk

#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)

0x00000200

◆ DMA_HISR_TEIF6_Msk

#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)

0x00080000

◆ DMA_HISR_TEIF7_Msk

#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)

0x02000000

◆ DMA_LIFCR_CDMEIF0_Msk

#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)

0x00000004

◆ DMA_LIFCR_CDMEIF1_Msk

#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)

0x00000100

◆ DMA_LIFCR_CDMEIF2_Msk

#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)

0x00040000

◆ DMA_LIFCR_CDMEIF3_Msk

#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)

0x01000000

◆ DMA_LIFCR_CFEIF0_Msk

#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)

0x00000001

◆ DMA_LIFCR_CFEIF1_Msk

#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)

0x00000040

◆ DMA_LIFCR_CFEIF2_Msk

#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)

0x00010000

◆ DMA_LIFCR_CFEIF3_Msk

#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)

0x00400000

◆ DMA_LIFCR_CHTIF0_Msk

#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)

0x00000010

◆ DMA_LIFCR_CHTIF1_Msk

#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)

0x00000400

◆ DMA_LIFCR_CHTIF2_Msk

#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)

0x00100000

◆ DMA_LIFCR_CHTIF3_Msk

#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)

0x04000000

◆ DMA_LIFCR_CTCIF0_Msk

#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)

0x00000020

◆ DMA_LIFCR_CTCIF1_Msk

#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)

0x00000800

◆ DMA_LIFCR_CTCIF2_Msk

#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)

0x00200000

◆ DMA_LIFCR_CTCIF3_Msk

#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)

0x08000000

◆ DMA_LIFCR_CTEIF0_Msk

#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)

0x00000008

◆ DMA_LIFCR_CTEIF1_Msk

#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)

0x00000200

◆ DMA_LIFCR_CTEIF2_Msk

#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)

0x00080000

◆ DMA_LIFCR_CTEIF3_Msk

#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)

0x02000000

◆ DMA_LISR_DMEIF0_Msk

#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)

0x00000004

◆ DMA_LISR_DMEIF1_Msk

#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)

0x00000100

◆ DMA_LISR_DMEIF2_Msk

#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)

0x00040000

◆ DMA_LISR_DMEIF3_Msk

#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)

0x01000000

◆ DMA_LISR_FEIF0_Msk

#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)

0x00000001

◆ DMA_LISR_FEIF1_Msk

#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)

0x00000040

◆ DMA_LISR_FEIF2_Msk

#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)

0x00010000

◆ DMA_LISR_FEIF3_Msk

#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)

0x00400000

◆ DMA_LISR_HTIF0_Msk

#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)

0x00000010

◆ DMA_LISR_HTIF1_Msk

#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)

0x00000400

◆ DMA_LISR_HTIF2_Msk

#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)

0x00100000

◆ DMA_LISR_HTIF3_Msk

#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)

0x04000000

◆ DMA_LISR_TCIF0_Msk

#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)

0x00000020

◆ DMA_LISR_TCIF1_Msk

#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)

0x00000800

◆ DMA_LISR_TCIF2_Msk

#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)

0x00200000

◆ DMA_LISR_TCIF3_Msk

#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)

0x08000000

◆ DMA_LISR_TEIF0_Msk

#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)

0x00000008

◆ DMA_LISR_TEIF1_Msk

#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)

0x00000200

◆ DMA_LISR_TEIF2_Msk

#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)

0x00080000

◆ DMA_LISR_TEIF3_Msk

#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)

0x02000000

◆ DMA_SxCR_ACK_Msk

#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)

0x00100000

◆ DMA_SxCR_CHSEL_0

#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)

0x02000000

◆ DMA_SxCR_CHSEL_1

#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)

0x04000000

◆ DMA_SxCR_CHSEL_2

#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)

0x08000000

◆ DMA_SxCR_CHSEL_Msk

#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)

0x0E000000

◆ DMA_SxCR_CIRC_Msk

#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)

0x00000100

◆ DMA_SxCR_CT_Msk

#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)

0x00080000

◆ DMA_SxCR_DBM_Msk

#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)

0x00040000

◆ DMA_SxCR_DIR_0

#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)

0x00000040

◆ DMA_SxCR_DIR_1

#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)

0x00000080

◆ DMA_SxCR_DIR_Msk

#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)

0x000000C0

◆ DMA_SxCR_DMEIE_Msk

#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)

0x00000002

◆ DMA_SxCR_EN_Msk

#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)

0x00000001

◆ DMA_SxCR_HTIE_Msk

#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)

0x00000008

◆ DMA_SxCR_MBURST_0

#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)

0x00800000

◆ DMA_SxCR_MBURST_1

#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)

0x01000000

◆ DMA_SxCR_MBURST_Msk

#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)

0x01800000

◆ DMA_SxCR_MINC_Msk

#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)

0x00000400

◆ DMA_SxCR_MSIZE_0

#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)

0x00002000

◆ DMA_SxCR_MSIZE_1

#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)

0x00004000

◆ DMA_SxCR_MSIZE_Msk

#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)

0x00006000

◆ DMA_SxCR_PBURST_0

#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)

0x00200000

◆ DMA_SxCR_PBURST_1

#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)

0x00400000

◆ DMA_SxCR_PBURST_Msk

#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)

0x00600000

◆ DMA_SxCR_PFCTRL_Msk

#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)

0x00000020

◆ DMA_SxCR_PINC_Msk

#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)

0x00000200

◆ DMA_SxCR_PINCOS_Msk

#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)

0x00008000

◆ DMA_SxCR_PL_0

#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)

0x00010000

◆ DMA_SxCR_PL_1

#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)

0x00020000

◆ DMA_SxCR_PL_Msk

#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)

0x00030000

◆ DMA_SxCR_PSIZE_0

#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)

0x00000800

◆ DMA_SxCR_PSIZE_1

#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)

0x00001000

◆ DMA_SxCR_PSIZE_Msk

#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)

0x00001800

◆ DMA_SxCR_TCIE_Msk

#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)

0x00000010

◆ DMA_SxCR_TEIE_Msk

#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)

0x00000004

◆ DMA_SxFCR_DMDIS_Msk

#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)

0x00000004

◆ DMA_SxFCR_FEIE_Msk

#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)

0x00000080

◆ DMA_SxFCR_FS_0

#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)

0x00000008

◆ DMA_SxFCR_FS_1

#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)

0x00000010

◆ DMA_SxFCR_FS_2

#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)

0x00000020

◆ DMA_SxFCR_FS_Msk

#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)

0x00000038

◆ DMA_SxFCR_FTH_0

#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)

0x00000001

◆ DMA_SxFCR_FTH_1

#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)

0x00000002

◆ DMA_SxFCR_FTH_Msk

#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)

0x00000003

◆ DMA_SxM0AR_M0A

#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk

Memory Address

◆ DMA_SxM0AR_M0A_Msk

#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)

0xFFFFFFFF

◆ DMA_SxM1AR_M1A

#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk

Memory Address

◆ DMA_SxM1AR_M1A_Msk

#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)

0xFFFFFFFF

◆ DMA_SxNDT_0

#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)

0x00000001

◆ DMA_SxNDT_1

#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)

0x00000002

◆ DMA_SxNDT_10

#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)

0x00000400

◆ DMA_SxNDT_11

#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)

0x00000800

◆ DMA_SxNDT_12

#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)

0x00001000

◆ DMA_SxNDT_13

#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)

0x00002000

◆ DMA_SxNDT_14

#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)

0x00004000

◆ DMA_SxNDT_15

#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)

0x00008000

◆ DMA_SxNDT_2

#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)

0x00000004

◆ DMA_SxNDT_3

#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)

0x00000008

◆ DMA_SxNDT_4

#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)

0x00000010

◆ DMA_SxNDT_5

#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)

0x00000020

◆ DMA_SxNDT_6

#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)

0x00000040

◆ DMA_SxNDT_7

#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)

0x00000080

◆ DMA_SxNDT_8

#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)

0x00000100

◆ DMA_SxNDT_9

#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)

0x00000200

◆ DMA_SxNDT_Msk

#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)

0x0000FFFF

◆ DMA_SxPAR_PA

#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk

Peripheral Address

◆ DMA_SxPAR_PA_Msk

#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)

0xFFFFFFFF

◆ ETH_DMABMR_AAB_Msk

#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)

0x02000000

◆ ETH_DMABMR_DA_Msk

#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)

0x00000002

◆ ETH_DMABMR_DSL_Msk

#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)

0x0000007C

◆ ETH_DMABMR_EDE_Msk

#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)

0x00000080

◆ ETH_DMABMR_FB_Msk

#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)

0x00010000

◆ ETH_DMABMR_FPM_Msk

#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)

0x01000000

◆ ETH_DMABMR_MB_Msk

#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)

0x04000000

◆ ETH_DMABMR_PBL_Msk

#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)

0x00003F00

◆ ETH_DMABMR_RDP_Msk

#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)

0x007E0000

◆ ETH_DMABMR_RTPR_Msk

#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)

0x0000C000

◆ ETH_DMABMR_SR_Msk

#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)

0x00000001

◆ ETH_DMABMR_USP_Msk

#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)

0x00800000

◆ ETH_DMACHRBAR_HRBAP_Msk

#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)

0xFFFFFFFF

◆ ETH_DMACHRDR_HRDAP_Msk

#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)

0xFFFFFFFF

◆ ETH_DMACHTBAR_HTBAP_Msk

#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)

0xFFFFFFFF

◆ ETH_DMACHTDR_HTDAP_Msk

#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)

0xFFFFFFFF

◆ ETH_DMAIER_AISE_Msk

#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)

0x00008000

◆ ETH_DMAIER_ERIE_Msk

#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)

0x00004000

◆ ETH_DMAIER_ETIE_Msk

#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)

0x00000400

◆ ETH_DMAIER_FBEIE_Msk

#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)

0x00002000

◆ ETH_DMAIER_NISE_Msk

#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)

0x00010000

◆ ETH_DMAIER_RBUIE_Msk

#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)

0x00000080

◆ ETH_DMAIER_RIE_Msk

#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)

0x00000040

◆ ETH_DMAIER_ROIE_Msk

#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)

0x00000010

◆ ETH_DMAIER_RPSIE_Msk

#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)

0x00000100

◆ ETH_DMAIER_RWTIE_Msk

#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)

0x00000200

◆ ETH_DMAIER_TBUIE_Msk

#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)

0x00000004

◆ ETH_DMAIER_TIE_Msk

#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)

0x00000001

◆ ETH_DMAIER_TJTIE_Msk

#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)

0x00000008

◆ ETH_DMAIER_TPSIE_Msk

#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)

0x00000002

◆ ETH_DMAIER_TUIE_Msk

#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)

0x00000020

◆ ETH_DMAMFBOCR_MFA_Msk

#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)

0x0FFE0000

◆ ETH_DMAMFBOCR_MFC_Msk

#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)

0x0000FFFF

◆ ETH_DMAMFBOCR_OFOC_Msk

#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)

0x10000000

◆ ETH_DMAMFBOCR_OMFC_Msk

#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)

0x00010000

◆ ETH_DMAOMR_DFRF_Msk

#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)

0x01000000

◆ ETH_DMAOMR_DTCEFD_Msk

#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)

0x04000000

◆ ETH_DMAOMR_FEF_Msk

#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)

0x00000080

◆ ETH_DMAOMR_FTF_Msk

#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)

0x00100000

◆ ETH_DMAOMR_FUGF_Msk

#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)

0x00000040

◆ ETH_DMAOMR_OSF_Msk

#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)

0x00000004

◆ ETH_DMAOMR_RSF_Msk

#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)

0x02000000

◆ ETH_DMAOMR_RTC_Msk

#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)

0x00000018

◆ ETH_DMAOMR_SR_Msk

#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)

0x00000002

◆ ETH_DMAOMR_ST_Msk

#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)

0x00002000

◆ ETH_DMAOMR_TSF_Msk

#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)

0x00200000

◆ ETH_DMAOMR_TTC_Msk

#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)

0x0001C000

◆ ETH_DMARDLAR_SRL_Msk

#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)

0xFFFFFFFF

◆ ETH_DMARPDR_RPD_Msk

#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)

0xFFFFFFFF

◆ ETH_DMASR_AIS_Msk

#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)

0x00008000

◆ ETH_DMASR_EBS_DataTransfTx_Msk

#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)

0x00800000

◆ ETH_DMASR_EBS_DescAccess_Msk

#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)

0x02000000

◆ ETH_DMASR_EBS_Msk

#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)

0x03800000

◆ ETH_DMASR_EBS_ReadTransf_Msk

#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)

0x01000000

◆ ETH_DMASR_ERS_Msk

#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)

0x00004000

◆ ETH_DMASR_ETS_Msk

#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)

0x00000400

◆ ETH_DMASR_FBES_Msk

#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)

0x00002000

◆ ETH_DMASR_MMCS_Msk

#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)

0x08000000

◆ ETH_DMASR_NIS_Msk

#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)

0x00010000

◆ ETH_DMASR_PMTS_Msk

#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)

0x10000000

◆ ETH_DMASR_RBUS_Msk

#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)

0x00000080

◆ ETH_DMASR_ROS_Msk

#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)

0x00000010

◆ ETH_DMASR_RPS_Closing_Msk

#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)

0x000A0000

◆ ETH_DMASR_RPS_Fetching_Msk

#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)

0x00020000

◆ ETH_DMASR_RPS_Msk

#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)

0x000E0000

◆ ETH_DMASR_RPS_Queuing_Msk

#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)

0x000E0000

◆ ETH_DMASR_RPS_Suspended_Msk

#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)

0x00080000

◆ ETH_DMASR_RPS_Waiting_Msk

#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)

0x00060000

◆ ETH_DMASR_RPSS_Msk

#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)

0x00000100

◆ ETH_DMASR_RS_Msk

#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)

0x00000040

◆ ETH_DMASR_RWTS_Msk

#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)

0x00000200

◆ ETH_DMASR_TBUS_Msk

#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)

0x00000004

◆ ETH_DMASR_TJTS_Msk

#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)

0x00000008

◆ ETH_DMASR_TPS_Closing_Msk

#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)

0x00700000

◆ ETH_DMASR_TPS_Fetching_Msk

#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)

0x00100000

◆ ETH_DMASR_TPS_Msk

#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)

0x00700000

◆ ETH_DMASR_TPS_Reading_Msk

#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)

0x00300000

◆ ETH_DMASR_TPS_Suspended_Msk

#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)

0x00600000

◆ ETH_DMASR_TPS_Waiting_Msk

#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)

0x00200000

◆ ETH_DMASR_TPSS_Msk

#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)

0x00000002

◆ ETH_DMASR_TS_Msk

#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)

0x00000001

◆ ETH_DMASR_TSTS_Msk

#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)

0x20000000

◆ ETH_DMASR_TUS_Msk

#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)

0x00000020

◆ ETH_DMATDLAR_STL_Msk

#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)

0xFFFFFFFF

◆ ETH_DMATPDR_TPD_Msk

#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)

0xFFFFFFFF

◆ ETH_MACA0HR_MACA0H_Msk

#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)

0x0000FFFF

◆ ETH_MACA0LR_MACA0L_Msk

#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)

0xFFFFFFFF

◆ ETH_MACA1HR_AE_Msk

#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)

0x80000000

◆ ETH_MACA1HR_MACA1H_Msk

#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)

0x0000FFFF

◆ ETH_MACA1HR_MBC_Msk

#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)

0x3F000000

◆ ETH_MACA1HR_SA_Msk

#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)

0x40000000

◆ ETH_MACA1LR_MACA1L_Msk

#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)

0xFFFFFFFF

◆ ETH_MACA2HR_AE_Msk

#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)

0x80000000

◆ ETH_MACA2HR_MACA2H_Msk

#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)

0x0000FFFF

◆ ETH_MACA2HR_MBC_Msk

#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)

0x3F000000

◆ ETH_MACA2HR_SA_Msk

#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)

0x40000000

◆ ETH_MACA2LR_MACA2L_Msk

#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)

0xFFFFFFFF

◆ ETH_MACA3HR_AE_Msk

#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)

0x80000000

◆ ETH_MACA3HR_MACA3H_Msk

#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)

0x0000FFFF

◆ ETH_MACA3HR_MBC_Msk

#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)

0x3F000000

◆ ETH_MACA3HR_SA_Msk

#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)

0x40000000

◆ ETH_MACA3LR_MACA3L_Msk

#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)

0xFFFFFFFF

◆ ETH_MACCR_APCS_Msk

#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)

0x00000080

◆ ETH_MACCR_BL

#define ETH_MACCR_BL

Value:

ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling

a transmission attempt during retries after a collision: 0 =< r <2^k */

ETH_MACCR_BL_Msk

#define ETH_MACCR_BL_Msk

Definition stm32f407xx.h:12875

◆ ETH_MACCR_BL_Msk

#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)

0x00000060

◆ ETH_MACCR_CSD_Msk

#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)

0x00010000

◆ ETH_MACCR_CSTF_Msk

#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos)

0x02000000

◆ ETH_MACCR_DC_Msk

#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)

0x00000010

◆ ETH_MACCR_DM_Msk

#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)

0x00000800

◆ ETH_MACCR_FES_Msk

#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)

0x00004000

◆ ETH_MACCR_IFG_Msk

#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)

0x000E0000

◆ ETH_MACCR_IPCO_Msk

#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)

0x00000400

◆ ETH_MACCR_JD_Msk

#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)

0x00400000

◆ ETH_MACCR_LM_Msk

#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)

0x00001000

◆ ETH_MACCR_RD_Msk

#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)

0x00000200

◆ ETH_MACCR_RE_Msk

#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)

0x00000004

◆ ETH_MACCR_ROD_Msk

#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)

0x00002000

◆ ETH_MACCR_TE_Msk

#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)

0x00000008

◆ ETH_MACCR_WD_Msk

#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)

0x00800000

◆ ETH_MACDBGR_MMRPEA_Msk

#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)

0x00000001

◆ ETH_MACDBGR_MMTEA_Msk

#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)

0x00010000

◆ ETH_MACDBGR_MSFRWCS_0

#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)

0x00000002

◆ ETH_MACDBGR_MSFRWCS_1

#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)

0x00000004

◆ ETH_MACDBGR_MSFRWCS_Msk

#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)

0x00000006

◆ ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk

#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)

0x00040000

◆ ETH_MACDBGR_MTFCS_Msk

#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)

0x00060000

◆ ETH_MACDBGR_MTFCS_TRANSFERRING_Msk

#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)

0x00060000

◆ ETH_MACDBGR_MTFCS_WAITING_Msk

#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)

0x00020000

◆ ETH_MACDBGR_MTP_Msk

#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)

0x00080000

◆ ETH_MACDBGR_RFFL_ABOVEFCT_Msk

#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)

0x00000200

◆ ETH_MACDBGR_RFFL_BELOWFCT_Msk

#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)

0x00000100

◆ ETH_MACDBGR_RFFL_FULL_Msk

#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)

0x00000300

◆ ETH_MACDBGR_RFFL_Msk

#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)

0x00000300

◆ ETH_MACDBGR_RFRCS_DATAREADING_Msk

#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)

0x00000020

◆ ETH_MACDBGR_RFRCS_FLUSHING_Msk

#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)

0x00000060

◆ ETH_MACDBGR_RFRCS_Msk

#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)

0x00000060

◆ ETH_MACDBGR_RFRCS_STATUSREADING_Msk

#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)

0x00000040

◆ ETH_MACDBGR_RFWRA_Msk

#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)

0x00000010

◆ ETH_MACDBGR_TFF_Msk

#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)

0x02000000

◆ ETH_MACDBGR_TFNE_Msk

#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)

0x01000000

◆ ETH_MACDBGR_TFRS_Msk

#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)

0x00300000

◆ ETH_MACDBGR_TFRS_READ_Msk

#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)

0x00100000

◆ ETH_MACDBGR_TFRS_WAITING_Msk

#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)

0x00200000

◆ ETH_MACDBGR_TFRS_WRITING_Msk

#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)

0x00300000

◆ ETH_MACDBGR_TFWA_Msk

#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)

0x00400000

◆ ETH_MACFCR_FCBBPA_Msk

#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)

0x00000001

◆ ETH_MACFCR_PLT_Minus144_Msk

#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)

0x00000020

◆ ETH_MACFCR_PLT_Minus256_Msk

#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)

0x00000030

◆ ETH_MACFCR_PLT_Minus28_Msk

#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)

0x00000010

◆ ETH_MACFCR_PLT_Msk

#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)

0x00000030

◆ ETH_MACFCR_PT_Msk

#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)

0xFFFF0000

◆ ETH_MACFCR_RFCE_Msk

#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)

0x00000004

◆ ETH_MACFCR_TFCE_Msk

#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)

0x00000002

◆ ETH_MACFCR_UPFD_Msk

#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)

0x00000008

◆ ETH_MACFCR_ZQPD_Msk

#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)

0x00000080

◆ ETH_MACFFR_BFD_Msk

#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)

0x00000020

◆ ETH_MACFFR_DAIF_Msk

#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)

0x00000008

◆ ETH_MACFFR_HM_Msk

#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)

0x00000004

◆ ETH_MACFFR_HPF_Msk

#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)

0x00000400

◆ ETH_MACFFR_HU_Msk

#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)

0x00000002

◆ ETH_MACFFR_PAM_Msk

#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)

0x00000010

◆ ETH_MACFFR_PCF_BlockAll_Msk

#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)

0x00000040

◆ ETH_MACFFR_PCF_ForwardAll_Msk

#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)

0x00000080

◆ ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)

0x000000C0

◆ ETH_MACFFR_PCF_Msk

#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)

0x000000C0

◆ ETH_MACFFR_PM_Msk

#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)

0x00000001

◆ ETH_MACFFR_RA_Msk

#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)

0x80000000

◆ ETH_MACFFR_SAF_Msk

#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)

0x00000200

◆ ETH_MACFFR_SAIF_Msk

#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)

0x00000100

◆ ETH_MACHTHR_HTH_Msk

#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)

0xFFFFFFFF

◆ ETH_MACHTLR_HTL_Msk

#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)

0xFFFFFFFF

◆ ETH_MACIMR_PMTIM_Msk

#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)

0x00000008

◆ ETH_MACIMR_TSTIM_Msk

#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)

0x00000200

◆ ETH_MACMIIAR_CR_Div102_Msk

#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)

0x00000010

◆ ETH_MACMIIAR_CR_Div16_Msk

#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)

0x00000008

◆ ETH_MACMIIAR_CR_Div26_Msk

#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)

0x0000000C

◆ ETH_MACMIIAR_CR_Div62_Msk

#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)

0x00000004

◆ ETH_MACMIIAR_CR_Msk

#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)

0x0000001C

◆ ETH_MACMIIAR_MB_Msk

#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)

0x00000001

◆ ETH_MACMIIAR_MR_Msk

#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)

0x000007C0

◆ ETH_MACMIIAR_MW_Msk

#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)

0x00000002

◆ ETH_MACMIIAR_PA_Msk

#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)

0x0000F800

◆ ETH_MACMIIDR_MD_Msk

#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)

0x0000FFFF

◆ ETH_MACPMTCSR_GU_Msk

#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)

0x00000200

◆ ETH_MACPMTCSR_MPE_Msk

#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)

0x00000002

◆ ETH_MACPMTCSR_MPR_Msk

#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)

0x00000020

◆ ETH_MACPMTCSR_PD_Msk

#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)

0x00000001

◆ ETH_MACPMTCSR_WFE_Msk

#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)

0x00000004

◆ ETH_MACPMTCSR_WFFRPR_Msk

#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)

0x80000000

◆ ETH_MACPMTCSR_WFR_Msk

#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)

0x00000040

◆ ETH_MACRWUFFR_D_Msk

#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)

0xFFFFFFFF

◆ ETH_MACSR_MMCS_Msk

#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)

0x00000010

◆ ETH_MACSR_MMCTS_Msk

#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)

0x00000040

◆ ETH_MACSR_MMMCRS_Msk

#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)

0x00000020

◆ ETH_MACSR_PMTS_Msk

#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)

0x00000008

◆ ETH_MACSR_TSTS_Msk

#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)

0x00000200

◆ ETH_MACVLANTR_VLANTC_Msk

#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)

0x00010000

◆ ETH_MACVLANTR_VLANTI_Msk

#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)

0x0000FFFF

◆ ETH_MMCCR_CR_Msk

#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)

0x00000001

◆ ETH_MMCCR_CSR_Msk

#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)

0x00000002

◆ ETH_MMCCR_MCF_Msk

#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)

0x00000008

◆ ETH_MMCCR_MCFHP_Msk

#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)

0x00000020

◆ ETH_MMCCR_MCP_Msk

#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)

0x00000010

◆ ETH_MMCCR_ROR_Msk

#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)

0x00000004

◆ ETH_MMCRFAECR_RFAEC_Msk

#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)

0xFFFFFFFF

◆ ETH_MMCRFCECR_RFCEC_Msk

#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)

0xFFFFFFFF

◆ ETH_MMCRGUFCR_RGUFC_Msk

#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)

0xFFFFFFFF

◆ ETH_MMCRIMR_RFAEM_Msk

#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)

0x00000040

◆ ETH_MMCRIMR_RFCEM_Msk

#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)

0x00000020

◆ ETH_MMCRIMR_RGUFM_Msk

#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)

0x00020000

◆ ETH_MMCRIR_RFAES_Msk

#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)

0x00000040

◆ ETH_MMCRIR_RFCES_Msk

#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)

0x00000020

◆ ETH_MMCRIR_RGUFS_Msk

#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)

0x00020000

◆ ETH_MMCTGFCR_TGFC_Msk

#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)

0xFFFFFFFF

◆ ETH_MMCTGFMSCCR_TGFMSCC_Msk

#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)

0xFFFFFFFF

◆ ETH_MMCTGFSCCR_TGFSCC_Msk

#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)

0xFFFFFFFF

◆ ETH_MMCTIMR_TGFM_Msk

#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)

0x00200000

◆ ETH_MMCTIMR_TGFMSCM_Msk

#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)

0x00008000

◆ ETH_MMCTIMR_TGFSCM_Msk

#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)

0x00004000

◆ ETH_MMCTIR_TGFMSCS_Msk

#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)

0x00008000

◆ ETH_MMCTIR_TGFS_Msk

#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)

0x00200000

◆ ETH_MMCTIR_TGFSCS_Msk

#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)

0x00004000

◆ ETH_PTPSSIR_STSSI_Msk

#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)

0x000000FF

◆ ETH_PTPTSAR_TSA_Msk

#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)

0xFFFFFFFF

◆ ETH_PTPTSCR_TSARU_Msk

#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)

0x00000020

◆ ETH_PTPTSCR_TSCNT_Msk

#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)

0x00030000

◆ ETH_PTPTSCR_TSE_Msk

#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)

0x00000001

◆ ETH_PTPTSCR_TSFCU_Msk

#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)

0x00000002

◆ ETH_PTPTSCR_TSITE_Msk

#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)

0x00000010

◆ ETH_PTPTSCR_TSPFFMAE_Msk

#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)

0x00008000

◆ ETH_PTPTSCR_TSPTPPSV2E_Msk

#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)

0x00000400

◆ ETH_PTPTSCR_TSSARFE_Msk

#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)

0x00000100

◆ ETH_PTPTSCR_TSSEME_Msk

#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)

0x00004000

◆ ETH_PTPTSCR_TSSIPV4FE_Msk

#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)

0x00002000

◆ ETH_PTPTSCR_TSSIPV6FE_Msk

#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)

0x00001000

◆ ETH_PTPTSCR_TSSMRME_Msk

#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)

0x00008000

◆ ETH_PTPTSCR_TSSPTPOEFE_Msk

#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)

0x00000800

◆ ETH_PTPTSCR_TSSSR_Msk

#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)

0x00000200

◆ ETH_PTPTSCR_TSSTI_Msk

#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)

0x00000004

◆ ETH_PTPTSCR_TSSTU_Msk

#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)

0x00000008

◆ ETH_PTPTSHR_STS_Msk

#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)

0xFFFFFFFF

◆ ETH_PTPTSHUR_TSUS_Msk

#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)

0xFFFFFFFF

◆ ETH_PTPTSLR_STPNS_Msk

#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)

0x80000000

◆ ETH_PTPTSLR_STSS_Msk

#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)

0x7FFFFFFF

◆ ETH_PTPTSLUR_TSUPNS_Msk

#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)

0x80000000

◆ ETH_PTPTSLUR_TSUSS_Msk

#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)

0x7FFFFFFF

◆ ETH_PTPTSSR_TSSO_Msk

#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)

0x00000010

◆ ETH_PTPTSSR_TSTTR_Msk

#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)

0x00000020

◆ ETH_PTPTTHR_TTSH_Msk

#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)

0xFFFFFFFF

◆ ETH_PTPTTLR_TTSL_Msk

#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)

0xFFFFFFFF

◆ EXTI_EMR_MR0

#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk

Event Mask on line 0

◆ EXTI_EMR_MR0_Msk

#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)

0x00000001

◆ EXTI_EMR_MR1

#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk

Event Mask on line 1

◆ EXTI_EMR_MR10

#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk

Event Mask on line 10

◆ EXTI_EMR_MR10_Msk

#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)

0x00000400

◆ EXTI_EMR_MR11

#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk

Event Mask on line 11

◆ EXTI_EMR_MR11_Msk

#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)

0x00000800

◆ EXTI_EMR_MR12

#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk

Event Mask on line 12

◆ EXTI_EMR_MR12_Msk

#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)

0x00001000

◆ EXTI_EMR_MR13

#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk

Event Mask on line 13

◆ EXTI_EMR_MR13_Msk

#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)

0x00002000

◆ EXTI_EMR_MR14

#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk

Event Mask on line 14

◆ EXTI_EMR_MR14_Msk

#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)

0x00004000

◆ EXTI_EMR_MR15

#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk

Event Mask on line 15

◆ EXTI_EMR_MR15_Msk

#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)

0x00008000

◆ EXTI_EMR_MR16

#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk

Event Mask on line 16

◆ EXTI_EMR_MR16_Msk

#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)

0x00010000

◆ EXTI_EMR_MR17

#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk

Event Mask on line 17

◆ EXTI_EMR_MR17_Msk

#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)

0x00020000

◆ EXTI_EMR_MR18

#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk

Event Mask on line 18

◆ EXTI_EMR_MR18_Msk

#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)

0x00040000

◆ EXTI_EMR_MR19

#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk

Event Mask on line 19

◆ EXTI_EMR_MR19_Msk

#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)

0x00080000

◆ EXTI_EMR_MR1_Msk

#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)

0x00000002

◆ EXTI_EMR_MR2

#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk

Event Mask on line 2

◆ EXTI_EMR_MR20

#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk

Event Mask on line 20

◆ EXTI_EMR_MR20_Msk

#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)

0x00100000

◆ EXTI_EMR_MR21

#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk

Event Mask on line 21

◆ EXTI_EMR_MR21_Msk

#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)

0x00200000

◆ EXTI_EMR_MR22

#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk

Event Mask on line 22

◆ EXTI_EMR_MR22_Msk

#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)

0x00400000

◆ EXTI_EMR_MR2_Msk

#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)

0x00000004

◆ EXTI_EMR_MR3

#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk

Event Mask on line 3

◆ EXTI_EMR_MR3_Msk

#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)

0x00000008

◆ EXTI_EMR_MR4

#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk

Event Mask on line 4

◆ EXTI_EMR_MR4_Msk

#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)

0x00000010

◆ EXTI_EMR_MR5

#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk

Event Mask on line 5

◆ EXTI_EMR_MR5_Msk

#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)

0x00000020

◆ EXTI_EMR_MR6

#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk

Event Mask on line 6

◆ EXTI_EMR_MR6_Msk

#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)

0x00000040

◆ EXTI_EMR_MR7

#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk

Event Mask on line 7

◆ EXTI_EMR_MR7_Msk

#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)

0x00000080

◆ EXTI_EMR_MR8

#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk

Event Mask on line 8

◆ EXTI_EMR_MR8_Msk

#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)

0x00000100

◆ EXTI_EMR_MR9

#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk

Event Mask on line 9

◆ EXTI_EMR_MR9_Msk

#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)

0x00000200

◆ EXTI_FTSR_TR0

#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk

Falling trigger event configuration bit of line 0

◆ EXTI_FTSR_TR0_Msk

#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)

0x00000001

◆ EXTI_FTSR_TR1

#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk

Falling trigger event configuration bit of line 1

◆ EXTI_FTSR_TR10

#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk

Falling trigger event configuration bit of line 10

◆ EXTI_FTSR_TR10_Msk

#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)

0x00000400

◆ EXTI_FTSR_TR11

#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk

Falling trigger event configuration bit of line 11

◆ EXTI_FTSR_TR11_Msk

#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)

0x00000800

◆ EXTI_FTSR_TR12

#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk

Falling trigger event configuration bit of line 12

◆ EXTI_FTSR_TR12_Msk

#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)

0x00001000

◆ EXTI_FTSR_TR13

#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk

Falling trigger event configuration bit of line 13

◆ EXTI_FTSR_TR13_Msk

#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)

0x00002000

◆ EXTI_FTSR_TR14

#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk

Falling trigger event configuration bit of line 14

◆ EXTI_FTSR_TR14_Msk

#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)

0x00004000

◆ EXTI_FTSR_TR15

#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk

Falling trigger event configuration bit of line 15

◆ EXTI_FTSR_TR15_Msk

#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)

0x00008000

◆ EXTI_FTSR_TR16

#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk

Falling trigger event configuration bit of line 16

◆ EXTI_FTSR_TR16_Msk

#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)

0x00010000

◆ EXTI_FTSR_TR17

#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk

Falling trigger event configuration bit of line 17

◆ EXTI_FTSR_TR17_Msk

#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)

0x00020000

◆ EXTI_FTSR_TR18

#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk

Falling trigger event configuration bit of line 18

◆ EXTI_FTSR_TR18_Msk

#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)

0x00040000

◆ EXTI_FTSR_TR19

#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk

Falling trigger event configuration bit of line 19

◆ EXTI_FTSR_TR19_Msk

#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)

0x00080000

◆ EXTI_FTSR_TR1_Msk

#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)

0x00000002

◆ EXTI_FTSR_TR2

#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk

Falling trigger event configuration bit of line 2

◆ EXTI_FTSR_TR20

#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk

Falling trigger event configuration bit of line 20

◆ EXTI_FTSR_TR20_Msk

#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)

0x00100000

◆ EXTI_FTSR_TR21

#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk

Falling trigger event configuration bit of line 21

◆ EXTI_FTSR_TR21_Msk

#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)

0x00200000

◆ EXTI_FTSR_TR22

#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk

Falling trigger event configuration bit of line 22

◆ EXTI_FTSR_TR22_Msk

#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)

0x00400000

◆ EXTI_FTSR_TR2_Msk

#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)

0x00000004

◆ EXTI_FTSR_TR3

#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk

Falling trigger event configuration bit of line 3

◆ EXTI_FTSR_TR3_Msk

#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)

0x00000008

◆ EXTI_FTSR_TR4

#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk

Falling trigger event configuration bit of line 4

◆ EXTI_FTSR_TR4_Msk

#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)

0x00000010

◆ EXTI_FTSR_TR5

#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk

Falling trigger event configuration bit of line 5

◆ EXTI_FTSR_TR5_Msk

#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)

0x00000020

◆ EXTI_FTSR_TR6

#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk

Falling trigger event configuration bit of line 6

◆ EXTI_FTSR_TR6_Msk

#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)

0x00000040

◆ EXTI_FTSR_TR7

#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk

Falling trigger event configuration bit of line 7

◆ EXTI_FTSR_TR7_Msk

#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)

0x00000080

◆ EXTI_FTSR_TR8

#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk

Falling trigger event configuration bit of line 8

◆ EXTI_FTSR_TR8_Msk

#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)

0x00000100

◆ EXTI_FTSR_TR9

#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk

Falling trigger event configuration bit of line 9

◆ EXTI_FTSR_TR9_Msk

#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)

0x00000200

◆ EXTI_IMR_IM

#define EXTI_IMR_IM EXTI_IMR_IM_Msk

Interrupt Mask All

◆ EXTI_IMR_IM_Msk

#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)

0x007FFFFF

◆ EXTI_IMR_MR0

#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk

Interrupt Mask on line 0

◆ EXTI_IMR_MR0_Msk

#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)

0x00000001

◆ EXTI_IMR_MR1

#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk

Interrupt Mask on line 1

◆ EXTI_IMR_MR10

#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk

Interrupt Mask on line 10

◆ EXTI_IMR_MR10_Msk

#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)

0x00000400

◆ EXTI_IMR_MR11

#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk

Interrupt Mask on line 11

◆ EXTI_IMR_MR11_Msk

#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)

0x00000800

◆ EXTI_IMR_MR12

#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk

Interrupt Mask on line 12

◆ EXTI_IMR_MR12_Msk

#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)

0x00001000

◆ EXTI_IMR_MR13

#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk

Interrupt Mask on line 13

◆ EXTI_IMR_MR13_Msk

#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)

0x00002000

◆ EXTI_IMR_MR14

#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk

Interrupt Mask on line 14

◆ EXTI_IMR_MR14_Msk

#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)

0x00004000

◆ EXTI_IMR_MR15

#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk

Interrupt Mask on line 15

◆ EXTI_IMR_MR15_Msk

#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)

0x00008000

◆ EXTI_IMR_MR16

#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk

Interrupt Mask on line 16

◆ EXTI_IMR_MR16_Msk

#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)

0x00010000

◆ EXTI_IMR_MR17

#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk

Interrupt Mask on line 17

◆ EXTI_IMR_MR17_Msk

#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)

0x00020000

◆ EXTI_IMR_MR18

#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk

Interrupt Mask on line 18

◆ EXTI_IMR_MR18_Msk

#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)

0x00040000

◆ EXTI_IMR_MR19

#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk

Interrupt Mask on line 19

◆ EXTI_IMR_MR19_Msk

#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)

0x00080000

◆ EXTI_IMR_MR1_Msk

#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)

0x00000002

◆ EXTI_IMR_MR2

#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk

Interrupt Mask on line 2

◆ EXTI_IMR_MR20

#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk

Interrupt Mask on line 20

◆ EXTI_IMR_MR20_Msk

#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)

0x00100000

◆ EXTI_IMR_MR21

#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk

Interrupt Mask on line 21

◆ EXTI_IMR_MR21_Msk

#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)

0x00200000

◆ EXTI_IMR_MR22

#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk

Interrupt Mask on line 22

◆ EXTI_IMR_MR22_Msk

#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)

0x00400000

◆ EXTI_IMR_MR2_Msk

#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)

0x00000004

◆ EXTI_IMR_MR3

#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk

Interrupt Mask on line 3

◆ EXTI_IMR_MR3_Msk

#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)

0x00000008

◆ EXTI_IMR_MR4

#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk

Interrupt Mask on line 4

◆ EXTI_IMR_MR4_Msk

#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)

0x00000010

◆ EXTI_IMR_MR5

#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk

Interrupt Mask on line 5

◆ EXTI_IMR_MR5_Msk

#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)

0x00000020

◆ EXTI_IMR_MR6

#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk

Interrupt Mask on line 6

◆ EXTI_IMR_MR6_Msk

#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)

0x00000040

◆ EXTI_IMR_MR7

#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk

Interrupt Mask on line 7

◆ EXTI_IMR_MR7_Msk

#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)

0x00000080

◆ EXTI_IMR_MR8

#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk

Interrupt Mask on line 8

◆ EXTI_IMR_MR8_Msk

#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)

0x00000100

◆ EXTI_IMR_MR9

#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk

Interrupt Mask on line 9

◆ EXTI_IMR_MR9_Msk

#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)

0x00000200

◆ EXTI_PR_PR0

#define EXTI_PR_PR0 EXTI_PR_PR0_Msk

Pending bit for line 0

◆ EXTI_PR_PR0_Msk

#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)

0x00000001

◆ EXTI_PR_PR1

#define EXTI_PR_PR1 EXTI_PR_PR1_Msk

Pending bit for line 1

◆ EXTI_PR_PR10

#define EXTI_PR_PR10 EXTI_PR_PR10_Msk

Pending bit for line 10

◆ EXTI_PR_PR10_Msk

#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)

0x00000400

◆ EXTI_PR_PR11

#define EXTI_PR_PR11 EXTI_PR_PR11_Msk

Pending bit for line 11

◆ EXTI_PR_PR11_Msk

#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)

0x00000800

◆ EXTI_PR_PR12

#define EXTI_PR_PR12 EXTI_PR_PR12_Msk

Pending bit for line 12

◆ EXTI_PR_PR12_Msk

#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)

0x00001000

◆ EXTI_PR_PR13

#define EXTI_PR_PR13 EXTI_PR_PR13_Msk

Pending bit for line 13

◆ EXTI_PR_PR13_Msk

#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)

0x00002000

◆ EXTI_PR_PR14

#define EXTI_PR_PR14 EXTI_PR_PR14_Msk

Pending bit for line 14

◆ EXTI_PR_PR14_Msk

#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)

0x00004000

◆ EXTI_PR_PR15

#define EXTI_PR_PR15 EXTI_PR_PR15_Msk

Pending bit for line 15

◆ EXTI_PR_PR15_Msk

#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)

0x00008000

◆ EXTI_PR_PR16

#define EXTI_PR_PR16 EXTI_PR_PR16_Msk

Pending bit for line 16

◆ EXTI_PR_PR16_Msk

#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)

0x00010000

◆ EXTI_PR_PR17

#define EXTI_PR_PR17 EXTI_PR_PR17_Msk

Pending bit for line 17

◆ EXTI_PR_PR17_Msk

#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)

0x00020000

◆ EXTI_PR_PR18

#define EXTI_PR_PR18 EXTI_PR_PR18_Msk

Pending bit for line 18

◆ EXTI_PR_PR18_Msk

#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)

0x00040000

◆ EXTI_PR_PR19

#define EXTI_PR_PR19 EXTI_PR_PR19_Msk

Pending bit for line 19

◆ EXTI_PR_PR19_Msk

#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)

0x00080000

◆ EXTI_PR_PR1_Msk

#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)

0x00000002

◆ EXTI_PR_PR2

#define EXTI_PR_PR2 EXTI_PR_PR2_Msk

Pending bit for line 2

◆ EXTI_PR_PR20

#define EXTI_PR_PR20 EXTI_PR_PR20_Msk

Pending bit for line 20

◆ EXTI_PR_PR20_Msk

#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)

0x00100000

◆ EXTI_PR_PR21

#define EXTI_PR_PR21 EXTI_PR_PR21_Msk

Pending bit for line 21

◆ EXTI_PR_PR21_Msk

#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)

0x00200000

◆ EXTI_PR_PR22

#define EXTI_PR_PR22 EXTI_PR_PR22_Msk

Pending bit for line 22

◆ EXTI_PR_PR22_Msk

#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)

0x00400000

◆ EXTI_PR_PR2_Msk

#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)

0x00000004

◆ EXTI_PR_PR3

#define EXTI_PR_PR3 EXTI_PR_PR3_Msk

Pending bit for line 3

◆ EXTI_PR_PR3_Msk

#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)

0x00000008

◆ EXTI_PR_PR4

#define EXTI_PR_PR4 EXTI_PR_PR4_Msk

Pending bit for line 4

◆ EXTI_PR_PR4_Msk

#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)

0x00000010

◆ EXTI_PR_PR5

#define EXTI_PR_PR5 EXTI_PR_PR5_Msk

Pending bit for line 5

◆ EXTI_PR_PR5_Msk

#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)

0x00000020

◆ EXTI_PR_PR6

#define EXTI_PR_PR6 EXTI_PR_PR6_Msk

Pending bit for line 6

◆ EXTI_PR_PR6_Msk

#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)

0x00000040

◆ EXTI_PR_PR7

#define EXTI_PR_PR7 EXTI_PR_PR7_Msk

Pending bit for line 7

◆ EXTI_PR_PR7_Msk

#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)

0x00000080

◆ EXTI_PR_PR8

#define EXTI_PR_PR8 EXTI_PR_PR8_Msk

Pending bit for line 8

◆ EXTI_PR_PR8_Msk

#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)

0x00000100

◆ EXTI_PR_PR9

#define EXTI_PR_PR9 EXTI_PR_PR9_Msk

Pending bit for line 9

◆ EXTI_PR_PR9_Msk

#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)

0x00000200

◆ EXTI_RTSR_TR0

#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk

Rising trigger event configuration bit of line 0

◆ EXTI_RTSR_TR0_Msk

#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)

0x00000001

◆ EXTI_RTSR_TR1

#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk

Rising trigger event configuration bit of line 1

◆ EXTI_RTSR_TR10

#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk

Rising trigger event configuration bit of line 10

◆ EXTI_RTSR_TR10_Msk

#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)

0x00000400

◆ EXTI_RTSR_TR11

#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk

Rising trigger event configuration bit of line 11

◆ EXTI_RTSR_TR11_Msk

#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)

0x00000800

◆ EXTI_RTSR_TR12

#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk

Rising trigger event configuration bit of line 12

◆ EXTI_RTSR_TR12_Msk

#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)

0x00001000

◆ EXTI_RTSR_TR13

#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk

Rising trigger event configuration bit of line 13

◆ EXTI_RTSR_TR13_Msk

#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)

0x00002000

◆ EXTI_RTSR_TR14

#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk

Rising trigger event configuration bit of line 14

◆ EXTI_RTSR_TR14_Msk

#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)

0x00004000

◆ EXTI_RTSR_TR15

#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk

Rising trigger event configuration bit of line 15

◆ EXTI_RTSR_TR15_Msk

#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)

0x00008000

◆ EXTI_RTSR_TR16

#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk

Rising trigger event configuration bit of line 16

◆ EXTI_RTSR_TR16_Msk

#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)

0x00010000

◆ EXTI_RTSR_TR17

#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk

Rising trigger event configuration bit of line 17

◆ EXTI_RTSR_TR17_Msk

#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)

0x00020000

◆ EXTI_RTSR_TR18

#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk

Rising trigger event configuration bit of line 18

◆ EXTI_RTSR_TR18_Msk

#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)

0x00040000

◆ EXTI_RTSR_TR19

#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk

Rising trigger event configuration bit of line 19

◆ EXTI_RTSR_TR19_Msk

#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)

0x00080000

◆ EXTI_RTSR_TR1_Msk

#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)

0x00000002

◆ EXTI_RTSR_TR2

#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk

Rising trigger event configuration bit of line 2

◆ EXTI_RTSR_TR20

#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk

Rising trigger event configuration bit of line 20

◆ EXTI_RTSR_TR20_Msk

#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)

0x00100000

◆ EXTI_RTSR_TR21

#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk

Rising trigger event configuration bit of line 21

◆ EXTI_RTSR_TR21_Msk

#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)

0x00200000

◆ EXTI_RTSR_TR22

#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk

Rising trigger event configuration bit of line 22

◆ EXTI_RTSR_TR22_Msk

#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)

0x00400000

◆ EXTI_RTSR_TR2_Msk

#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)

0x00000004

◆ EXTI_RTSR_TR3

#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk

Rising trigger event configuration bit of line 3

◆ EXTI_RTSR_TR3_Msk

#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)

0x00000008

◆ EXTI_RTSR_TR4

#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk

Rising trigger event configuration bit of line 4

◆ EXTI_RTSR_TR4_Msk

#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)

0x00000010

◆ EXTI_RTSR_TR5

#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk

Rising trigger event configuration bit of line 5

◆ EXTI_RTSR_TR5_Msk

#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)

0x00000020

◆ EXTI_RTSR_TR6

#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk

Rising trigger event configuration bit of line 6

◆ EXTI_RTSR_TR6_Msk

#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)

0x00000040

◆ EXTI_RTSR_TR7

#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk

Rising trigger event configuration bit of line 7

◆ EXTI_RTSR_TR7_Msk

#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)

0x00000080

◆ EXTI_RTSR_TR8

#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk

Rising trigger event configuration bit of line 8

◆ EXTI_RTSR_TR8_Msk

#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)

0x00000100

◆ EXTI_RTSR_TR9

#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk

Rising trigger event configuration bit of line 9

◆ EXTI_RTSR_TR9_Msk

#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)

0x00000200

◆ EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk

Software Interrupt on line 0

◆ EXTI_SWIER_SWIER0_Msk

#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)

0x00000001

◆ EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk

Software Interrupt on line 1

◆ EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk

Software Interrupt on line 10

◆ EXTI_SWIER_SWIER10_Msk

#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)

0x00000400

◆ EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk

Software Interrupt on line 11

◆ EXTI_SWIER_SWIER11_Msk

#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)

0x00000800

◆ EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk

Software Interrupt on line 12

◆ EXTI_SWIER_SWIER12_Msk

#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)

0x00001000

◆ EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk

Software Interrupt on line 13

◆ EXTI_SWIER_SWIER13_Msk

#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)

0x00002000

◆ EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk

Software Interrupt on line 14

◆ EXTI_SWIER_SWIER14_Msk

#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)

0x00004000

◆ EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk

Software Interrupt on line 15

◆ EXTI_SWIER_SWIER15_Msk

#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)

0x00008000

◆ EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk

Software Interrupt on line 16

◆ EXTI_SWIER_SWIER16_Msk

#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)

0x00010000

◆ EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk

Software Interrupt on line 17

◆ EXTI_SWIER_SWIER17_Msk

#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)

0x00020000

◆ EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk

Software Interrupt on line 18

◆ EXTI_SWIER_SWIER18_Msk

#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)

0x00040000

◆ EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk

Software Interrupt on line 19

◆ EXTI_SWIER_SWIER19_Msk

#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)

0x00080000

◆ EXTI_SWIER_SWIER1_Msk

#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)

0x00000002

◆ EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk

Software Interrupt on line 2

◆ EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk

Software Interrupt on line 20

◆ EXTI_SWIER_SWIER20_Msk

#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)

0x00100000

◆ EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk

Software Interrupt on line 21

◆ EXTI_SWIER_SWIER21_Msk

#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)

0x00200000

◆ EXTI_SWIER_SWIER22

#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk

Software Interrupt on line 22

◆ EXTI_SWIER_SWIER22_Msk

#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)

0x00400000

◆ EXTI_SWIER_SWIER2_Msk

#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)

0x00000004

◆ EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk

Software Interrupt on line 3

◆ EXTI_SWIER_SWIER3_Msk

#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)

0x00000008

◆ EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk

Software Interrupt on line 4

◆ EXTI_SWIER_SWIER4_Msk

#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)

0x00000010

◆ EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk

Software Interrupt on line 5

◆ EXTI_SWIER_SWIER5_Msk

#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)

0x00000020

◆ EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk

Software Interrupt on line 6

◆ EXTI_SWIER_SWIER6_Msk

#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)

0x00000040

◆ EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk

Software Interrupt on line 7

◆ EXTI_SWIER_SWIER7_Msk

#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)

0x00000080

◆ EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk

Software Interrupt on line 8

◆ EXTI_SWIER_SWIER8_Msk

#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)

0x00000100

◆ EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk

Software Interrupt on line 9

◆ EXTI_SWIER_SWIER9_Msk

#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)

0x00000200

◆ FLASH_ACR_BYTE0_ADDRESS_Msk

#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)

0x40023C00

◆ FLASH_ACR_BYTE2_ADDRESS_Msk

#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)

0x40023C03

◆ FLASH_ACR_DCEN_Msk

#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)

0x00000400

◆ FLASH_ACR_DCRST_Msk

#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)

0x00001000

◆ FLASH_ACR_ICEN_Msk

#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

0x00000200

◆ FLASH_ACR_ICRST_Msk

#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

0x00000800

◆ FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

0x00000007

◆ FLASH_ACR_PRFTEN_Msk

#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

0x00000100

◆ FLASH_CR_EOPIE_Msk

#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

0x01000000

◆ FLASH_CR_LOCK_Msk

#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

0x80000000

◆ FLASH_CR_MER_Msk

#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

0x00000004

◆ FLASH_CR_PG_Msk

#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

0x00000001

◆ FLASH_CR_PSIZE_0

#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)

0x00000100

◆ FLASH_CR_PSIZE_1

#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)

0x00000200

◆ FLASH_CR_PSIZE_Msk

#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)

0x00000300

◆ FLASH_CR_SER_Msk

#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)

0x00000002

◆ FLASH_CR_SNB_0

#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)

0x00000008

◆ FLASH_CR_SNB_1

#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)

0x00000010

◆ FLASH_CR_SNB_2

#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)

0x00000020

◆ FLASH_CR_SNB_3

#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)

0x00000040

◆ FLASH_CR_SNB_Msk

#define FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos)

0x00000078

◆ FLASH_CR_STRT_Msk

#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

0x00010000

◆ FLASH_OPTCR1_nWRP_0

#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)

0x00010000

◆ FLASH_OPTCR1_nWRP_1

#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)

0x00020000

◆ FLASH_OPTCR1_nWRP_10

#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)

0x04000000

◆ FLASH_OPTCR1_nWRP_11

#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)

0x08000000

◆ FLASH_OPTCR1_nWRP_2

#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)

0x00040000

◆ FLASH_OPTCR1_nWRP_3

#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)

0x00080000

◆ FLASH_OPTCR1_nWRP_4

#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)

0x00100000

◆ FLASH_OPTCR1_nWRP_5

#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)

0x00200000

◆ FLASH_OPTCR1_nWRP_6

#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)

0x00400000

◆ FLASH_OPTCR1_nWRP_7

#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)

0x00800000

◆ FLASH_OPTCR1_nWRP_8

#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)

0x01000000

◆ FLASH_OPTCR1_nWRP_9

#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)

0x02000000

◆ FLASH_OPTCR1_nWRP_Msk

#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)

0x0FFF0000

◆ FLASH_OPTCR_BOR_LEV_Msk

#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)

0x0000000C

◆ FLASH_OPTCR_nRST_STDBY_Msk

#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)

0x00000080

◆ FLASH_OPTCR_nRST_STOP_Msk

#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)

0x00000040

◆ FLASH_OPTCR_nWRP_Msk

#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)

0x0FFF0000

◆ FLASH_OPTCR_OPTLOCK_Msk

#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)

0x00000001

◆ FLASH_OPTCR_OPTSTRT_Msk

#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)

0x00000002

◆ FLASH_OPTCR_RDP_0

#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)

0x00000100

◆ FLASH_OPTCR_RDP_1

#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)

0x00000200

◆ FLASH_OPTCR_RDP_2

#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)

0x00000400

◆ FLASH_OPTCR_RDP_3

#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)

0x00000800

◆ FLASH_OPTCR_RDP_4

#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)

0x00001000

◆ FLASH_OPTCR_RDP_5

#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)

0x00002000

◆ FLASH_OPTCR_RDP_6

#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)

0x00004000

◆ FLASH_OPTCR_RDP_7

#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)

0x00008000

◆ FLASH_OPTCR_RDP_Msk

#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)

0x0000FF00

◆ FLASH_OPTCR_WDG_SW_Msk

#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)

0x00000020

◆ FLASH_SR_BSY_Msk

#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

0x00010000

◆ FLASH_SR_EOP_Msk

#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

0x00000001

◆ FLASH_SR_OPERR_Msk

#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

0x00000002

◆ FLASH_SR_PGAERR_Msk

#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

0x00000020

◆ FLASH_SR_PGPERR_Msk

#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)

0x00000040

◆ FLASH_SR_PGSERR_Msk

#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

0x00000080

◆ FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

0x00000010

◆ FSMC_BCR1_ASYNCWAIT

#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk

Asynchronous wait

◆ FSMC_BCR1_ASYNCWAIT_Msk

#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)

0x00008000

◆ FSMC_BCR1_BURSTEN

#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk

Burst enable bit

◆ FSMC_BCR1_BURSTEN_Msk

#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)

0x00000100

◆ FSMC_BCR1_CBURSTRW

#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk

Write burst enable

◆ FSMC_BCR1_CBURSTRW_Msk

#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)

0x00080000

◆ FSMC_BCR1_CPSIZE

#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk

CRAM page size

◆ FSMC_BCR1_CPSIZE_0

#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)

0x00010000

◆ FSMC_BCR1_CPSIZE_1

#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)

0x00020000

◆ FSMC_BCR1_CPSIZE_2

#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)

0x00040000

◆ FSMC_BCR1_CPSIZE_Msk

#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)

0x00070000

◆ FSMC_BCR1_EXTMOD

#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk

Extended mode enable

◆ FSMC_BCR1_EXTMOD_Msk

#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)

0x00004000

◆ FSMC_BCR1_FACCEN

#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk

Flash access enable

◆ FSMC_BCR1_FACCEN_Msk

#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)

0x00000040

◆ FSMC_BCR1_MBKEN

#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk

Memory bank enable bit

◆ FSMC_BCR1_MBKEN_Msk

#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)

0x00000001

◆ FSMC_BCR1_MTYP

#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR1_MTYP_0

#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)

0x00000004

◆ FSMC_BCR1_MTYP_1

#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)

0x00000008

◆ FSMC_BCR1_MTYP_Msk

#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)

0x0000000C

◆ FSMC_BCR1_MUXEN

#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk

Address/data multiplexing enable bit

◆ FSMC_BCR1_MUXEN_Msk

#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)

0x00000002

◆ FSMC_BCR1_MWID

#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR1_MWID_0

#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)

0x00000010

◆ FSMC_BCR1_MWID_1

#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)

0x00000020

◆ FSMC_BCR1_MWID_Msk

#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)

0x00000030

◆ FSMC_BCR1_WAITCFG

#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk

Wait timing configuration

◆ FSMC_BCR1_WAITCFG_Msk

#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)

0x00000800

◆ FSMC_BCR1_WAITEN

#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk

Wait enable bit

◆ FSMC_BCR1_WAITEN_Msk

#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)

0x00002000

◆ FSMC_BCR1_WAITPOL

#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk

Wait signal polarity bit

◆ FSMC_BCR1_WAITPOL_Msk

#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)

0x00000200

◆ FSMC_BCR1_WRAPMOD

#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk

Wrapped burst mode support

◆ FSMC_BCR1_WRAPMOD_Msk

#define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)

0x00000400

◆ FSMC_BCR1_WREN

#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk

Write enable bit

◆ FSMC_BCR1_WREN_Msk

#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)

0x00001000

◆ FSMC_BCR2_ASYNCWAIT

#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk

Asynchronous wait

◆ FSMC_BCR2_ASYNCWAIT_Msk

#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)

0x00008000

◆ FSMC_BCR2_BURSTEN

#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk

Burst enable bit

◆ FSMC_BCR2_BURSTEN_Msk

#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)

0x00000100

◆ FSMC_BCR2_CBURSTRW

#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk

Write burst enable

◆ FSMC_BCR2_CBURSTRW_Msk

#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)

0x00080000

◆ FSMC_BCR2_CPSIZE

#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk

CRAM page size

◆ FSMC_BCR2_CPSIZE_0

#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)

0x00010000

◆ FSMC_BCR2_CPSIZE_1

#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)

0x00020000

◆ FSMC_BCR2_CPSIZE_2

#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)

0x00040000

◆ FSMC_BCR2_CPSIZE_Msk

#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)

0x00070000

◆ FSMC_BCR2_EXTMOD

#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk

Extended mode enable

◆ FSMC_BCR2_EXTMOD_Msk

#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)

0x00004000

◆ FSMC_BCR2_FACCEN

#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk

Flash access enable

◆ FSMC_BCR2_FACCEN_Msk

#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)

0x00000040

◆ FSMC_BCR2_MBKEN

#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk

Memory bank enable bit

◆ FSMC_BCR2_MBKEN_Msk

#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)

0x00000001

◆ FSMC_BCR2_MTYP

#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR2_MTYP_0

#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)

0x00000004

◆ FSMC_BCR2_MTYP_1

#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)

0x00000008

◆ FSMC_BCR2_MTYP_Msk

#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)

0x0000000C

◆ FSMC_BCR2_MUXEN

#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk

Address/data multiplexing enable bit

◆ FSMC_BCR2_MUXEN_Msk

#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)

0x00000002

◆ FSMC_BCR2_MWID

#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR2_MWID_0

#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)

0x00000010

◆ FSMC_BCR2_MWID_1

#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)

0x00000020

◆ FSMC_BCR2_MWID_Msk

#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)

0x00000030

◆ FSMC_BCR2_WAITCFG

#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk

Wait timing configuration

◆ FSMC_BCR2_WAITCFG_Msk

#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)

0x00000800

◆ FSMC_BCR2_WAITEN

#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk

Wait enable bit

◆ FSMC_BCR2_WAITEN_Msk

#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)

0x00002000

◆ FSMC_BCR2_WAITPOL

#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk

Wait signal polarity bit

◆ FSMC_BCR2_WAITPOL_Msk

#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)

0x00000200

◆ FSMC_BCR2_WRAPMOD

#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk

Wrapped burst mode support

◆ FSMC_BCR2_WRAPMOD_Msk

#define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)

0x00000400

◆ FSMC_BCR2_WREN

#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk

Write enable bit

◆ FSMC_BCR2_WREN_Msk

#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)

0x00001000

◆ FSMC_BCR3_ASYNCWAIT

#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk

Asynchronous wait

◆ FSMC_BCR3_ASYNCWAIT_Msk

#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)

0x00008000

◆ FSMC_BCR3_BURSTEN

#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk

Burst enable bit

◆ FSMC_BCR3_BURSTEN_Msk

#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)

0x00000100

◆ FSMC_BCR3_CBURSTRW

#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk

Write burst enable

◆ FSMC_BCR3_CBURSTRW_Msk

#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)

0x00080000

◆ FSMC_BCR3_CPSIZE

#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk

CRAM page size

◆ FSMC_BCR3_CPSIZE_0

#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)

0x00010000

◆ FSMC_BCR3_CPSIZE_1

#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)

0x00020000

◆ FSMC_BCR3_CPSIZE_2

#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)

0x00040000

◆ FSMC_BCR3_CPSIZE_Msk

#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)

0x00070000

◆ FSMC_BCR3_EXTMOD

#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk

Extended mode enable

◆ FSMC_BCR3_EXTMOD_Msk

#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)

0x00004000

◆ FSMC_BCR3_FACCEN

#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk

Flash access enable

◆ FSMC_BCR3_FACCEN_Msk

#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)

0x00000040

◆ FSMC_BCR3_MBKEN

#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk

Memory bank enable bit

◆ FSMC_BCR3_MBKEN_Msk

#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)

0x00000001

◆ FSMC_BCR3_MTYP

#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR3_MTYP_0

#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)

0x00000004

◆ FSMC_BCR3_MTYP_1

#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)

0x00000008

◆ FSMC_BCR3_MTYP_Msk

#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)

0x0000000C

◆ FSMC_BCR3_MUXEN

#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk

Address/data multiplexing enable bit

◆ FSMC_BCR3_MUXEN_Msk

#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)

0x00000002

◆ FSMC_BCR3_MWID

#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR3_MWID_0

#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)

0x00000010

◆ FSMC_BCR3_MWID_1

#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)

0x00000020

◆ FSMC_BCR3_MWID_Msk

#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)

0x00000030

◆ FSMC_BCR3_WAITCFG

#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk

Wait timing configuration

◆ FSMC_BCR3_WAITCFG_Msk

#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)

0x00000800

◆ FSMC_BCR3_WAITEN

#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk

Wait enable bit

◆ FSMC_BCR3_WAITEN_Msk

#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)

0x00002000

◆ FSMC_BCR3_WAITPOL

#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk

Wait signal polarity bit

◆ FSMC_BCR3_WAITPOL_Msk

#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)

0x00000200

◆ FSMC_BCR3_WRAPMOD

#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk

Wrapped burst mode support

◆ FSMC_BCR3_WRAPMOD_Msk

#define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)

0x00000400

◆ FSMC_BCR3_WREN

#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk

Write enable bit

◆ FSMC_BCR3_WREN_Msk

#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)

0x00001000

◆ FSMC_BCR4_ASYNCWAIT

#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk

Asynchronous wait

◆ FSMC_BCR4_ASYNCWAIT_Msk

#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)

0x00008000

◆ FSMC_BCR4_BURSTEN

#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk

Burst enable bit

◆ FSMC_BCR4_BURSTEN_Msk

#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)

0x00000100

◆ FSMC_BCR4_CBURSTRW

#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk

Write burst enable

◆ FSMC_BCR4_CBURSTRW_Msk

#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)

0x00080000

◆ FSMC_BCR4_CPSIZE

#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk

CRAM page size

◆ FSMC_BCR4_CPSIZE_0

#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)

0x00010000

◆ FSMC_BCR4_CPSIZE_1

#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)

0x00020000

◆ FSMC_BCR4_CPSIZE_2

#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)

0x00040000

◆ FSMC_BCR4_CPSIZE_Msk

#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)

0x00070000

◆ FSMC_BCR4_EXTMOD

#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk

Extended mode enable

◆ FSMC_BCR4_EXTMOD_Msk

#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)

0x00004000

◆ FSMC_BCR4_FACCEN

#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk

Flash access enable

◆ FSMC_BCR4_FACCEN_Msk

#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)

0x00000040

◆ FSMC_BCR4_MBKEN

#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk

Memory bank enable bit

◆ FSMC_BCR4_MBKEN_Msk

#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)

0x00000001

◆ FSMC_BCR4_MTYP

#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR4_MTYP_0

#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)

0x00000004

◆ FSMC_BCR4_MTYP_1

#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)

0x00000008

◆ FSMC_BCR4_MTYP_Msk

#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)

0x0000000C

◆ FSMC_BCR4_MUXEN

#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk

Address/data multiplexing enable bit

◆ FSMC_BCR4_MUXEN_Msk

#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)

0x00000002

◆ FSMC_BCR4_MWID

#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR4_MWID_0

#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)

0x00000010

◆ FSMC_BCR4_MWID_1

#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)

0x00000020

◆ FSMC_BCR4_MWID_Msk

#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)

0x00000030

◆ FSMC_BCR4_WAITCFG

#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk

Wait timing configuration

◆ FSMC_BCR4_WAITCFG_Msk

#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)

0x00000800

◆ FSMC_BCR4_WAITEN

#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk

Wait enable bit

◆ FSMC_BCR4_WAITEN_Msk

#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)

0x00002000

◆ FSMC_BCR4_WAITPOL

#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk

Wait signal polarity bit

◆ FSMC_BCR4_WAITPOL_Msk

#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)

0x00000200

◆ FSMC_BCR4_WRAPMOD

#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk

Wrapped burst mode support

◆ FSMC_BCR4_WRAPMOD_Msk

#define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)

0x00000400

◆ FSMC_BCR4_WREN

#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk

Write enable bit

◆ FSMC_BCR4_WREN_Msk

#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)

0x00001000

◆ FSMC_BTR1_ACCMOD

#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR1_ACCMOD_0

#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)

0x10000000

◆ FSMC_BTR1_ACCMOD_1

#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)

0x20000000

◆ FSMC_BTR1_ACCMOD_Msk

#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)

0x30000000

◆ FSMC_BTR1_ADDHLD

#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR1_ADDHLD_0

#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)

0x00000010

◆ FSMC_BTR1_ADDHLD_1

#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)

0x00000020

◆ FSMC_BTR1_ADDHLD_2

#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)

0x00000040

◆ FSMC_BTR1_ADDHLD_3

#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)

0x00000080

◆ FSMC_BTR1_ADDHLD_Msk

#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)

0x000000F0

◆ FSMC_BTR1_ADDSET

#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR1_ADDSET_0

#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)

0x00000001

◆ FSMC_BTR1_ADDSET_1

#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)

0x00000002

◆ FSMC_BTR1_ADDSET_2

#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)

0x00000004

◆ FSMC_BTR1_ADDSET_3

#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)

0x00000008

◆ FSMC_BTR1_ADDSET_Msk

#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)

0x0000000F

◆ FSMC_BTR1_BUSTURN

#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR1_BUSTURN_0

#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)

0x00010000

◆ FSMC_BTR1_BUSTURN_1

#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)

0x00020000

◆ FSMC_BTR1_BUSTURN_2

#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)

0x00040000

◆ FSMC_BTR1_BUSTURN_3

#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)

0x00080000

◆ FSMC_BTR1_BUSTURN_Msk

#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)

0x000F0000

◆ FSMC_BTR1_CLKDIV

#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR1_CLKDIV_0

#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)

0x00100000

◆ FSMC_BTR1_CLKDIV_1

#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)

0x00200000

◆ FSMC_BTR1_CLKDIV_2

#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)

0x00400000

◆ FSMC_BTR1_CLKDIV_3

#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)

0x00800000

◆ FSMC_BTR1_CLKDIV_Msk

#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)

0x00F00000

◆ FSMC_BTR1_DATAST

#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BTR1_DATAST_0

#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)

0x00000100

◆ FSMC_BTR1_DATAST_1

#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)

0x00000200

◆ FSMC_BTR1_DATAST_2

#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)

0x00000400

◆ FSMC_BTR1_DATAST_3

#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)

0x00000800

◆ FSMC_BTR1_DATAST_4

#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)

0x00001000

◆ FSMC_BTR1_DATAST_5

#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)

0x00002000

◆ FSMC_BTR1_DATAST_6

#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)

0x00004000

◆ FSMC_BTR1_DATAST_7

#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)

0x00008000

◆ FSMC_BTR1_DATAST_Msk

#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)

0x0000FF00

◆ FSMC_BTR1_DATLAT

#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR1_DATLAT_0

#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)

0x01000000

◆ FSMC_BTR1_DATLAT_1

#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)

0x02000000

◆ FSMC_BTR1_DATLAT_2

#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)

0x04000000

◆ FSMC_BTR1_DATLAT_3

#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)

0x08000000

◆ FSMC_BTR1_DATLAT_Msk

#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)

0x0F000000

◆ FSMC_BTR2_ACCMOD

#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR2_ACCMOD_0

#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)

0x10000000

◆ FSMC_BTR2_ACCMOD_1

#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)

0x20000000

◆ FSMC_BTR2_ACCMOD_Msk

#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)

0x30000000

◆ FSMC_BTR2_ADDHLD

#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR2_ADDHLD_0

#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)

0x00000010

◆ FSMC_BTR2_ADDHLD_1

#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)

0x00000020

◆ FSMC_BTR2_ADDHLD_2

#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)

0x00000040

◆ FSMC_BTR2_ADDHLD_3

#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)

0x00000080

◆ FSMC_BTR2_ADDHLD_Msk

#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)

0x000000F0

◆ FSMC_BTR2_ADDSET

#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR2_ADDSET_0

#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)

0x00000001

◆ FSMC_BTR2_ADDSET_1

#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)

0x00000002

◆ FSMC_BTR2_ADDSET_2

#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)

0x00000004

◆ FSMC_BTR2_ADDSET_3

#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)

0x00000008

◆ FSMC_BTR2_ADDSET_Msk

#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)

0x0000000F

◆ FSMC_BTR2_BUSTURN

#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR2_BUSTURN_0

#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)

0x00010000

◆ FSMC_BTR2_BUSTURN_1

#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)

0x00020000

◆ FSMC_BTR2_BUSTURN_2

#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)

0x00040000

◆ FSMC_BTR2_BUSTURN_3

#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)

0x00080000

◆ FSMC_BTR2_BUSTURN_Msk

#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)

0x000F0000

◆ FSMC_BTR2_CLKDIV

#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR2_CLKDIV_0

#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)

0x00100000

◆ FSMC_BTR2_CLKDIV_1

#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)

0x00200000

◆ FSMC_BTR2_CLKDIV_2

#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)

0x00400000

◆ FSMC_BTR2_CLKDIV_3

#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)

0x00800000

◆ FSMC_BTR2_CLKDIV_Msk

#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)

0x00F00000

◆ FSMC_BTR2_DATAST

#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BTR2_DATAST_0

#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)

0x00000100

◆ FSMC_BTR2_DATAST_1

#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)

0x00000200

◆ FSMC_BTR2_DATAST_2

#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)

0x00000400

◆ FSMC_BTR2_DATAST_3

#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)

0x00000800

◆ FSMC_BTR2_DATAST_4

#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)

0x00001000

◆ FSMC_BTR2_DATAST_5

#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)

0x00002000

◆ FSMC_BTR2_DATAST_6

#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)

0x00004000

◆ FSMC_BTR2_DATAST_7

#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)

0x00008000

◆ FSMC_BTR2_DATAST_Msk

#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)

0x0000FF00

◆ FSMC_BTR2_DATLAT

#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR2_DATLAT_0

#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)

0x01000000

◆ FSMC_BTR2_DATLAT_1

#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)

0x02000000

◆ FSMC_BTR2_DATLAT_2

#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)

0x04000000

◆ FSMC_BTR2_DATLAT_3

#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)

0x08000000

◆ FSMC_BTR2_DATLAT_Msk

#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)

0x0F000000

◆ FSMC_BTR3_ACCMOD

#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR3_ACCMOD_0

#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)

0x10000000

◆ FSMC_BTR3_ACCMOD_1

#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)

0x20000000

◆ FSMC_BTR3_ACCMOD_Msk

#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)

0x30000000

◆ FSMC_BTR3_ADDHLD

#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR3_ADDHLD_0

#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)

0x00000010

◆ FSMC_BTR3_ADDHLD_1

#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)

0x00000020

◆ FSMC_BTR3_ADDHLD_2

#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)

0x00000040

◆ FSMC_BTR3_ADDHLD_3

#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)

0x00000080

◆ FSMC_BTR3_ADDHLD_Msk

#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)

0x000000F0

◆ FSMC_BTR3_ADDSET

#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR3_ADDSET_0

#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)

0x00000001

◆ FSMC_BTR3_ADDSET_1

#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)

0x00000002

◆ FSMC_BTR3_ADDSET_2

#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)

0x00000004

◆ FSMC_BTR3_ADDSET_3

#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)

0x00000008

◆ FSMC_BTR3_ADDSET_Msk

#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)

0x0000000F

◆ FSMC_BTR3_BUSTURN

#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR3_BUSTURN_0

#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)

0x00010000

◆ FSMC_BTR3_BUSTURN_1

#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)

0x00020000

◆ FSMC_BTR3_BUSTURN_2

#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)

0x00040000

◆ FSMC_BTR3_BUSTURN_3

#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)

0x00080000

◆ FSMC_BTR3_BUSTURN_Msk

#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)

0x000F0000

◆ FSMC_BTR3_CLKDIV

#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR3_CLKDIV_0

#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)

0x00100000

◆ FSMC_BTR3_CLKDIV_1

#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)

0x00200000

◆ FSMC_BTR3_CLKDIV_2

#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)

0x00400000

◆ FSMC_BTR3_CLKDIV_3

#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)

0x00800000

◆ FSMC_BTR3_CLKDIV_Msk

#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)

0x00F00000

◆ FSMC_BTR3_DATAST

#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BTR3_DATAST_0

#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)

0x00000100

◆ FSMC_BTR3_DATAST_1

#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)

0x00000200

◆ FSMC_BTR3_DATAST_2

#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)

0x00000400

◆ FSMC_BTR3_DATAST_3

#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)

0x00000800

◆ FSMC_BTR3_DATAST_4

#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)

0x00001000

◆ FSMC_BTR3_DATAST_5

#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)

0x00002000

◆ FSMC_BTR3_DATAST_6

#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)

0x00004000

◆ FSMC_BTR3_DATAST_7

#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)

0x00008000

◆ FSMC_BTR3_DATAST_Msk

#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)

0x0000FF00

◆ FSMC_BTR3_DATLAT

#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR3_DATLAT_0

#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)

0x01000000

◆ FSMC_BTR3_DATLAT_1

#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)

0x02000000

◆ FSMC_BTR3_DATLAT_2

#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)

0x04000000

◆ FSMC_BTR3_DATLAT_3

#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)

0x08000000

◆ FSMC_BTR3_DATLAT_Msk

#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)

0x0F000000

◆ FSMC_BTR4_ACCMOD

#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR4_ACCMOD_0

#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)

0x10000000

◆ FSMC_BTR4_ACCMOD_1

#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)

0x20000000

◆ FSMC_BTR4_ACCMOD_Msk

#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)

0x30000000

◆ FSMC_BTR4_ADDHLD

#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR4_ADDHLD_0

#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)

0x00000010

◆ FSMC_BTR4_ADDHLD_1

#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)

0x00000020

◆ FSMC_BTR4_ADDHLD_2

#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)

0x00000040

◆ FSMC_BTR4_ADDHLD_3

#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)

0x00000080

◆ FSMC_BTR4_ADDHLD_Msk

#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)

0x000000F0

◆ FSMC_BTR4_ADDSET

#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR4_ADDSET_0

#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)

0x00000001

◆ FSMC_BTR4_ADDSET_1

#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)

0x00000002

◆ FSMC_BTR4_ADDSET_2

#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)

0x00000004

◆ FSMC_BTR4_ADDSET_3

#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)

0x00000008

◆ FSMC_BTR4_ADDSET_Msk

#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)

0x0000000F

◆ FSMC_BTR4_BUSTURN

#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR4_BUSTURN_0

#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)

0x00010000

◆ FSMC_BTR4_BUSTURN_1

#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)

0x00020000

◆ FSMC_BTR4_BUSTURN_2

#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)

0x00040000

◆ FSMC_BTR4_BUSTURN_3

#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)

0x00080000

◆ FSMC_BTR4_BUSTURN_Msk

#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)

0x000F0000

◆ FSMC_BTR4_CLKDIV

#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR4_CLKDIV_0

#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)

0x00100000

◆ FSMC_BTR4_CLKDIV_1

#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)

0x00200000

◆ FSMC_BTR4_CLKDIV_2

#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)

0x00400000

◆ FSMC_BTR4_CLKDIV_3

#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)

0x00800000

◆ FSMC_BTR4_CLKDIV_Msk

#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)

0x00F00000

◆ FSMC_BTR4_DATAST

#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BTR4_DATAST_0

#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)

0x00000100

◆ FSMC_BTR4_DATAST_1

#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)

0x00000200

◆ FSMC_BTR4_DATAST_2

#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)

0x00000400

◆ FSMC_BTR4_DATAST_3

#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)

0x00000800

◆ FSMC_BTR4_DATAST_4

#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)

0x00001000

◆ FSMC_BTR4_DATAST_5

#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)

0x00002000

◆ FSMC_BTR4_DATAST_6

#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)

0x00004000

◆ FSMC_BTR4_DATAST_7

#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)

0x00008000

◆ FSMC_BTR4_DATAST_Msk

#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)

0x0000FF00

◆ FSMC_BTR4_DATLAT

#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR4_DATLAT_0

#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)

0x01000000

◆ FSMC_BTR4_DATLAT_1

#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)

0x02000000

◆ FSMC_BTR4_DATLAT_2

#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)

0x04000000

◆ FSMC_BTR4_DATLAT_3

#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)

0x08000000

◆ FSMC_BTR4_DATLAT_Msk

#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)

0x0F000000

◆ FSMC_BWTR1_ACCMOD

#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR1_ACCMOD_0

#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)

0x10000000

◆ FSMC_BWTR1_ACCMOD_1

#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)

0x20000000

◆ FSMC_BWTR1_ACCMOD_Msk

#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)

0x30000000

◆ FSMC_BWTR1_ADDHLD

#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR1_ADDHLD_0

#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)

0x00000010

◆ FSMC_BWTR1_ADDHLD_1

#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)

0x00000020

◆ FSMC_BWTR1_ADDHLD_2

#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)

0x00000040

◆ FSMC_BWTR1_ADDHLD_3

#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)

0x00000080

◆ FSMC_BWTR1_ADDHLD_Msk

#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)

0x000000F0

◆ FSMC_BWTR1_ADDSET

#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR1_ADDSET_0

#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)

0x00000001

◆ FSMC_BWTR1_ADDSET_1

#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)

0x00000002

◆ FSMC_BWTR1_ADDSET_2

#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)

0x00000004

◆ FSMC_BWTR1_ADDSET_3

#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)

0x00000008

◆ FSMC_BWTR1_ADDSET_Msk

#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)

0x0000000F

◆ FSMC_BWTR1_BUSTURN

#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround duration)

◆ FSMC_BWTR1_BUSTURN_0

#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)

0x00010000

◆ FSMC_BWTR1_BUSTURN_1

#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)

0x00020000

◆ FSMC_BWTR1_BUSTURN_2

#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)

0x00040000

◆ FSMC_BWTR1_BUSTURN_3

#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)

0x00080000

◆ FSMC_BWTR1_BUSTURN_Msk

#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)

0x000F0000

◆ FSMC_BWTR1_DATAST

#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BWTR1_DATAST_0

#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)

0x00000100

◆ FSMC_BWTR1_DATAST_1

#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)

0x00000200

◆ FSMC_BWTR1_DATAST_2

#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)

0x00000400

◆ FSMC_BWTR1_DATAST_3

#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)

0x00000800

◆ FSMC_BWTR1_DATAST_4

#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)

0x00001000

◆ FSMC_BWTR1_DATAST_5

#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)

0x00002000

◆ FSMC_BWTR1_DATAST_6

#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)

0x00004000

◆ FSMC_BWTR1_DATAST_7

#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)

0x00008000

◆ FSMC_BWTR1_DATAST_Msk

#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)

0x0000FF00

◆ FSMC_BWTR2_ACCMOD

#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR2_ACCMOD_0

#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)

0x10000000

◆ FSMC_BWTR2_ACCMOD_1

#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)

0x20000000

◆ FSMC_BWTR2_ACCMOD_Msk

#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)

0x30000000

◆ FSMC_BWTR2_ADDHLD

#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR2_ADDHLD_0

#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)

0x00000010

◆ FSMC_BWTR2_ADDHLD_1

#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)

0x00000020

◆ FSMC_BWTR2_ADDHLD_2

#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)

0x00000040

◆ FSMC_BWTR2_ADDHLD_3

#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)

0x00000080

◆ FSMC_BWTR2_ADDHLD_Msk

#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)

0x000000F0

◆ FSMC_BWTR2_ADDSET

#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR2_ADDSET_0

#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)

0x00000001

◆ FSMC_BWTR2_ADDSET_1

#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)

0x00000002

◆ FSMC_BWTR2_ADDSET_2

#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)

0x00000004

◆ FSMC_BWTR2_ADDSET_3

#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)

0x00000008

◆ FSMC_BWTR2_ADDSET_Msk

#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)

0x0000000F

◆ FSMC_BWTR2_BUSTURN

#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround duration)

◆ FSMC_BWTR2_BUSTURN_0

#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)

0x00010000

◆ FSMC_BWTR2_BUSTURN_1

#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)

0x00020000

◆ FSMC_BWTR2_BUSTURN_2

#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)

0x00040000

◆ FSMC_BWTR2_BUSTURN_3

#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)

0x00080000

◆ FSMC_BWTR2_BUSTURN_Msk

#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)

0x000F0000

◆ FSMC_BWTR2_DATAST

#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BWTR2_DATAST_0

#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)

0x00000100

◆ FSMC_BWTR2_DATAST_1

#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)

0x00000200

◆ FSMC_BWTR2_DATAST_2

#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)

0x00000400

◆ FSMC_BWTR2_DATAST_3

#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)

0x00000800

◆ FSMC_BWTR2_DATAST_4

#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)

0x00001000

◆ FSMC_BWTR2_DATAST_5

#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)

0x00002000

◆ FSMC_BWTR2_DATAST_6

#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)

0x00004000

◆ FSMC_BWTR2_DATAST_7

#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)

0x00008000

◆ FSMC_BWTR2_DATAST_Msk

#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)

0x0000FF00

◆ FSMC_BWTR3_ACCMOD

#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR3_ACCMOD_0

#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)

0x10000000

◆ FSMC_BWTR3_ACCMOD_1

#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)

0x20000000

◆ FSMC_BWTR3_ACCMOD_Msk

#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)

0x30000000

◆ FSMC_BWTR3_ADDHLD

#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR3_ADDHLD_0

#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)

0x00000010

◆ FSMC_BWTR3_ADDHLD_1

#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)

0x00000020

◆ FSMC_BWTR3_ADDHLD_2

#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)

0x00000040

◆ FSMC_BWTR3_ADDHLD_3

#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)

0x00000080

◆ FSMC_BWTR3_ADDHLD_Msk

#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)

0x000000F0

◆ FSMC_BWTR3_ADDSET

#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR3_ADDSET_0

#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)

0x00000001

◆ FSMC_BWTR3_ADDSET_1

#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)

0x00000002

◆ FSMC_BWTR3_ADDSET_2

#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)

0x00000004

◆ FSMC_BWTR3_ADDSET_3

#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)

0x00000008

◆ FSMC_BWTR3_ADDSET_Msk

#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)

0x0000000F

◆ FSMC_BWTR3_BUSTURN

#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround duration)

◆ FSMC_BWTR3_BUSTURN_0

#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)

0x00010000

◆ FSMC_BWTR3_BUSTURN_1

#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)

0x00020000

◆ FSMC_BWTR3_BUSTURN_2

#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)

0x00040000

◆ FSMC_BWTR3_BUSTURN_3

#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)

0x00080000

◆ FSMC_BWTR3_BUSTURN_Msk

#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)

0x000F0000

◆ FSMC_BWTR3_DATAST

#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk

DATAST [7:0] bits (Data-phase duration)

◆ FSMC_BWTR3_DATAST_0

#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)

0x00000100

◆ FSMC_BWTR3_DATAST_1

#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)

0x00000200

◆ FSMC_BWTR3_DATAST_2

#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)

0x00000400

◆ FSMC_BWTR3_DATAST_3

#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)

0x00000800

◆ FSMC_BWTR3_DATAST_4

#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)

0x00001000

◆ FSMC_BWTR3_DATAST_5

#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)

0x00002000

◆ FSMC_BWTR3_DATAST_6

#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)

0x00004000

◆ FSMC_BWTR3_DATAST_7

#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)

0x00008000

◆ FSMC_BWTR3_DATAST_Msk

#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)

0x0000FF00

◆ FSMC_BWTR4_ACCMOD

#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR4_ACCMOD_0

#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)

0x10000000

◆ FSMC_BWTR4_ACCMOD_1

#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)

0x20000000

◆ FSMC_BWTR4_ACCMOD_Msk

#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)

0x30000000

◆ FSMC_BWTR4_ADDHLD

#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR4_ADDHLD_0

#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)

0x00000010

◆ FSMC_BWTR4_ADDHLD_1

#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)

0x00000020

◆ FSMC_BWTR4_ADDHLD_2

#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)

0x00000040

◆ FSMC_BWTR4_ADDHLD_3

#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)

0x00000080

◆ FSMC_BWTR4_ADDHLD_Msk

#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)

0x000000F0

◆ FSMC_BWTR4_ADDSET

#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR4_ADDSET_0

#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)

0x00000001

◆ FSMC_BWTR4_ADDSET_1

#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)

0x00000002

◆ FSMC_BWTR4_ADDSET_2

#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)

0x00000004

◆ FSMC_BWTR4_ADDSET_3

#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)

0x00000008

◆ FSMC_BWTR4_ADDSET_Msk

#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)

0x0000000F

◆ FSMC_BWTR4_BUSTURN

#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround duration)

◆ FSMC_BWTR4_BUSTURN_0

#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)

0x00010000

◆ FSMC_BWTR4_BUSTURN_1

#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)

0x00020000

◆ FSMC_BWTR4_BUSTURN_2

#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)

0x00040000

◆ FSMC_BWTR4_BUSTURN_3

#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)

0x00080000

◆ FSMC_BWTR4_BUSTURN_Msk

#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)

0x000F0000

◆ FSMC_BWTR4_DATAST

#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BWTR4_DATAST_0

#define FSMC_BWTR4_DATAST_0 0x00000100U

Bit 0

◆ FSMC_BWTR4_DATAST_1

#define FSMC_BWTR4_DATAST_1 0x00000200U

Bit 1

◆ FSMC_BWTR4_DATAST_2

#define FSMC_BWTR4_DATAST_2 0x00000400U

Bit 2

◆ FSMC_BWTR4_DATAST_3

#define FSMC_BWTR4_DATAST_3 0x00000800U

Bit 3

◆ FSMC_BWTR4_DATAST_4

#define FSMC_BWTR4_DATAST_4 0x00001000U

Bit 4

◆ FSMC_BWTR4_DATAST_5

#define FSMC_BWTR4_DATAST_5 0x00002000U

Bit 5

◆ FSMC_BWTR4_DATAST_6

#define FSMC_BWTR4_DATAST_6 0x00004000U

Bit 6

◆ FSMC_BWTR4_DATAST_7

#define FSMC_BWTR4_DATAST_7 0x00008000U

Bit 7

◆ FSMC_BWTR4_DATAST_Msk

#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)

0x0000FF00

◆ FSMC_ECCR2_ECC2

#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk

ECC result

◆ FSMC_ECCR2_ECC2_Msk

#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)

0xFFFFFFFF

◆ FSMC_ECCR3_ECC3

#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk

ECC result

◆ FSMC_ECCR3_ECC3_Msk

#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)

0xFFFFFFFF

◆ FSMC_PATT2_ATTHIZ2

#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

◆ FSMC_PATT2_ATTHIZ2_0

#define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)

0x01000000

◆ FSMC_PATT2_ATTHIZ2_1

#define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)

0x02000000

◆ FSMC_PATT2_ATTHIZ2_2

#define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)

0x04000000

◆ FSMC_PATT2_ATTHIZ2_3

#define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)

0x08000000

◆ FSMC_PATT2_ATTHIZ2_4

#define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)

0x10000000

◆ FSMC_PATT2_ATTHIZ2_5

#define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)

0x20000000

◆ FSMC_PATT2_ATTHIZ2_6

#define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)

0x40000000

◆ FSMC_PATT2_ATTHIZ2_7

#define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)

0x80000000

◆ FSMC_PATT2_ATTHIZ2_Msk

#define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)

0xFF000000

◆ FSMC_PATT2_ATTHOLD2

#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

◆ FSMC_PATT2_ATTHOLD2_0

#define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00010000

◆ FSMC_PATT2_ATTHOLD2_1

#define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00020000

◆ FSMC_PATT2_ATTHOLD2_2

#define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00040000

◆ FSMC_PATT2_ATTHOLD2_3

#define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00080000

◆ FSMC_PATT2_ATTHOLD2_4

#define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00100000

◆ FSMC_PATT2_ATTHOLD2_5

#define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00200000

◆ FSMC_PATT2_ATTHOLD2_6

#define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00400000

◆ FSMC_PATT2_ATTHOLD2_7

#define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)

0x00800000

◆ FSMC_PATT2_ATTHOLD2_Msk

#define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)

0x00FF0000

◆ FSMC_PATT2_ATTSET2

#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk

ATTSET2[7:0] bits (Attribute memory 2 setup time)

◆ FSMC_PATT2_ATTSET2_0

#define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)

0x00000001

◆ FSMC_PATT2_ATTSET2_1

#define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)

0x00000002

◆ FSMC_PATT2_ATTSET2_2

#define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)

0x00000004

◆ FSMC_PATT2_ATTSET2_3

#define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)

0x00000008

◆ FSMC_PATT2_ATTSET2_4

#define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)

0x00000010

◆ FSMC_PATT2_ATTSET2_5

#define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)

0x00000020

◆ FSMC_PATT2_ATTSET2_6

#define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)

0x00000040

◆ FSMC_PATT2_ATTSET2_7

#define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)

0x00000080

◆ FSMC_PATT2_ATTSET2_Msk

#define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)

0x000000FF

◆ FSMC_PATT2_ATTWAIT2

#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

◆ FSMC_PATT2_ATTWAIT2_0

#define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00000100

◆ FSMC_PATT2_ATTWAIT2_1

#define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00000200

◆ FSMC_PATT2_ATTWAIT2_2

#define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00000400

◆ FSMC_PATT2_ATTWAIT2_3

#define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00000800

◆ FSMC_PATT2_ATTWAIT2_4

#define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00001000

◆ FSMC_PATT2_ATTWAIT2_5

#define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00002000

◆ FSMC_PATT2_ATTWAIT2_6

#define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00004000

◆ FSMC_PATT2_ATTWAIT2_7

#define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)

0x00008000

◆ FSMC_PATT2_ATTWAIT2_Msk

#define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)

0x0000FF00

◆ FSMC_PATT3_ATTHIZ3

#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

◆ FSMC_PATT3_ATTHIZ3_0

#define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)

0x01000000

◆ FSMC_PATT3_ATTHIZ3_1

#define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)

0x02000000

◆ FSMC_PATT3_ATTHIZ3_2

#define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)

0x04000000

◆ FSMC_PATT3_ATTHIZ3_3

#define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)

0x08000000

◆ FSMC_PATT3_ATTHIZ3_4

#define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)

0x10000000

◆ FSMC_PATT3_ATTHIZ3_5

#define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)

0x20000000

◆ FSMC_PATT3_ATTHIZ3_6

#define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)

0x40000000

◆ FSMC_PATT3_ATTHIZ3_7

#define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)

0x80000000

◆ FSMC_PATT3_ATTHIZ3_Msk

#define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)

0xFF000000

◆ FSMC_PATT3_ATTHOLD3

#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

◆ FSMC_PATT3_ATTHOLD3_0

#define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00010000

◆ FSMC_PATT3_ATTHOLD3_1

#define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00020000

◆ FSMC_PATT3_ATTHOLD3_2

#define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00040000

◆ FSMC_PATT3_ATTHOLD3_3

#define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00080000

◆ FSMC_PATT3_ATTHOLD3_4

#define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00100000

◆ FSMC_PATT3_ATTHOLD3_5

#define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00200000

◆ FSMC_PATT3_ATTHOLD3_6

#define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00400000

◆ FSMC_PATT3_ATTHOLD3_7

#define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)

0x00800000

◆ FSMC_PATT3_ATTHOLD3_Msk

#define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)

0x00FF0000

◆ FSMC_PATT3_ATTSET3

#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk

ATTSET3[7:0] bits (Attribute memory 3 setup time)

◆ FSMC_PATT3_ATTSET3_0

#define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)

0x00000001

◆ FSMC_PATT3_ATTSET3_1

#define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)

0x00000002

◆ FSMC_PATT3_ATTSET3_2

#define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)

0x00000004

◆ FSMC_PATT3_ATTSET3_3

#define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)

0x00000008

◆ FSMC_PATT3_ATTSET3_4

#define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)

0x00000010

◆ FSMC_PATT3_ATTSET3_5

#define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)

0x00000020

◆ FSMC_PATT3_ATTSET3_6

#define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)

0x00000040

◆ FSMC_PATT3_ATTSET3_7

#define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)

0x00000080

◆ FSMC_PATT3_ATTSET3_Msk

#define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)

0x000000FF

◆ FSMC_PATT3_ATTWAIT3

#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

◆ FSMC_PATT3_ATTWAIT3_0

#define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00000100

◆ FSMC_PATT3_ATTWAIT3_1

#define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00000200

◆ FSMC_PATT3_ATTWAIT3_2

#define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00000400

◆ FSMC_PATT3_ATTWAIT3_3

#define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00000800

◆ FSMC_PATT3_ATTWAIT3_4

#define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00001000

◆ FSMC_PATT3_ATTWAIT3_5

#define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00002000

◆ FSMC_PATT3_ATTWAIT3_6

#define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00004000

◆ FSMC_PATT3_ATTWAIT3_7

#define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)

0x00008000

◆ FSMC_PATT3_ATTWAIT3_Msk

#define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)

0x0000FF00

◆ FSMC_PATT4_ATTHIZ4

#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

◆ FSMC_PATT4_ATTHIZ4_0

#define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)

0x01000000

◆ FSMC_PATT4_ATTHIZ4_1

#define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)

0x02000000

◆ FSMC_PATT4_ATTHIZ4_2

#define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)

0x04000000

◆ FSMC_PATT4_ATTHIZ4_3

#define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)

0x08000000

◆ FSMC_PATT4_ATTHIZ4_4

#define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)

0x10000000

◆ FSMC_PATT4_ATTHIZ4_5

#define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)

0x20000000

◆ FSMC_PATT4_ATTHIZ4_6

#define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)

0x40000000

◆ FSMC_PATT4_ATTHIZ4_7

#define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)

0x80000000

◆ FSMC_PATT4_ATTHIZ4_Msk

#define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)

0xFF000000

◆ FSMC_PATT4_ATTHOLD4

#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

◆ FSMC_PATT4_ATTHOLD4_0

#define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00010000

◆ FSMC_PATT4_ATTHOLD4_1

#define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00020000

◆ FSMC_PATT4_ATTHOLD4_2

#define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00040000

◆ FSMC_PATT4_ATTHOLD4_3

#define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00080000

◆ FSMC_PATT4_ATTHOLD4_4

#define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00100000

◆ FSMC_PATT4_ATTHOLD4_5

#define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00200000

◆ FSMC_PATT4_ATTHOLD4_6

#define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00400000

◆ FSMC_PATT4_ATTHOLD4_7

#define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)

0x00800000

◆ FSMC_PATT4_ATTHOLD4_Msk

#define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)

0x00FF0000

◆ FSMC_PATT4_ATTSET4

#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk

ATTSET4[7:0] bits (Attribute memory 4 setup time)

◆ FSMC_PATT4_ATTSET4_0

#define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)

0x00000001

◆ FSMC_PATT4_ATTSET4_1

#define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)

0x00000002

◆ FSMC_PATT4_ATTSET4_2

#define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)

0x00000004

◆ FSMC_PATT4_ATTSET4_3

#define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)

0x00000008

◆ FSMC_PATT4_ATTSET4_4

#define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)

0x00000010

◆ FSMC_PATT4_ATTSET4_5

#define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)

0x00000020

◆ FSMC_PATT4_ATTSET4_6

#define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)

0x00000040

◆ FSMC_PATT4_ATTSET4_7

#define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)

0x00000080

◆ FSMC_PATT4_ATTSET4_Msk

#define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)

0x000000FF

◆ FSMC_PATT4_ATTWAIT4

#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

◆ FSMC_PATT4_ATTWAIT4_0

#define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00000100

◆ FSMC_PATT4_ATTWAIT4_1

#define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00000200

◆ FSMC_PATT4_ATTWAIT4_2

#define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00000400

◆ FSMC_PATT4_ATTWAIT4_3

#define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00000800

◆ FSMC_PATT4_ATTWAIT4_4

#define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00001000

◆ FSMC_PATT4_ATTWAIT4_5

#define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00002000

◆ FSMC_PATT4_ATTWAIT4_6

#define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00004000

◆ FSMC_PATT4_ATTWAIT4_7

#define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)

0x00008000

◆ FSMC_PATT4_ATTWAIT4_Msk

#define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)

0x0000FF00

◆ FSMC_PCR2_ECCEN

#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk

ECC computation logic enable bit

◆ FSMC_PCR2_ECCEN_Msk

#define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)

0x00000040

◆ FSMC_PCR2_ECCPS

#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk

ECCPS[1:0] bits (ECC page size)

◆ FSMC_PCR2_ECCPS_0

#define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)

0x00020000

◆ FSMC_PCR2_ECCPS_1

#define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)

0x00040000

◆ FSMC_PCR2_ECCPS_2

#define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)

0x00080000

◆ FSMC_PCR2_ECCPS_Msk

#define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)

0x000E0000

◆ FSMC_PCR2_PBKEN

#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR2_PBKEN_Msk

#define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)

0x00000004

◆ FSMC_PCR2_PTYP

#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk

Memory type

◆ FSMC_PCR2_PTYP_Msk

#define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)

0x00000008

◆ FSMC_PCR2_PWAITEN

#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk

Wait feature enable bit

◆ FSMC_PCR2_PWAITEN_Msk

#define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)

0x00000002

◆ FSMC_PCR2_PWID

#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR2_PWID_0

#define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)

0x00000010

◆ FSMC_PCR2_PWID_1

#define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)

0x00000020

◆ FSMC_PCR2_PWID_Msk

#define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)

0x00000030

◆ FSMC_PCR2_TAR

#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR2_TAR_0

#define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)

0x00002000

◆ FSMC_PCR2_TAR_1

#define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)

0x00004000

◆ FSMC_PCR2_TAR_2

#define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)

0x00008000

◆ FSMC_PCR2_TAR_3

#define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)

0x00010000

◆ FSMC_PCR2_TAR_Msk

#define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)

0x0001E000

◆ FSMC_PCR2_TCLR

#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR2_TCLR_0

#define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)

0x00000200

◆ FSMC_PCR2_TCLR_1

#define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)

0x00000400

◆ FSMC_PCR2_TCLR_2

#define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)

0x00000800

◆ FSMC_PCR2_TCLR_3

#define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)

0x00001000

◆ FSMC_PCR2_TCLR_Msk

#define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)

0x00001E00

◆ FSMC_PCR3_ECCEN

#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk

ECC computation logic enable bit

◆ FSMC_PCR3_ECCEN_Msk

#define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)

0x00000040

◆ FSMC_PCR3_ECCPS

#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk

ECCPS[2:0] bits (ECC page size)

◆ FSMC_PCR3_ECCPS_0

#define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)

0x00020000

◆ FSMC_PCR3_ECCPS_1

#define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)

0x00040000

◆ FSMC_PCR3_ECCPS_2

#define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)

0x00080000

◆ FSMC_PCR3_ECCPS_Msk

#define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)

0x000E0000

◆ FSMC_PCR3_PBKEN

#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR3_PBKEN_Msk

#define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)

0x00000004

◆ FSMC_PCR3_PTYP

#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk

Memory type

◆ FSMC_PCR3_PTYP_Msk

#define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)

0x00000008

◆ FSMC_PCR3_PWAITEN

#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk

Wait feature enable bit

◆ FSMC_PCR3_PWAITEN_Msk

#define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)

0x00000002

◆ FSMC_PCR3_PWID

#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR3_PWID_0

#define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)

0x00000010

◆ FSMC_PCR3_PWID_1

#define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)

0x00000020

◆ FSMC_PCR3_PWID_Msk

#define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)

0x00000030

◆ FSMC_PCR3_TAR

#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR3_TAR_0

#define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)

0x00002000

◆ FSMC_PCR3_TAR_1

#define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)

0x00004000

◆ FSMC_PCR3_TAR_2

#define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)

0x00008000

◆ FSMC_PCR3_TAR_3

#define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)

0x00010000

◆ FSMC_PCR3_TAR_Msk

#define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)

0x0001E000

◆ FSMC_PCR3_TCLR

#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR3_TCLR_0

#define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)

0x00000200

◆ FSMC_PCR3_TCLR_1

#define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)

0x00000400

◆ FSMC_PCR3_TCLR_2

#define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)

0x00000800

◆ FSMC_PCR3_TCLR_3

#define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)

0x00001000

◆ FSMC_PCR3_TCLR_Msk

#define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)

0x00001E00

◆ FSMC_PCR4_ECCEN

#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk

ECC computation logic enable bit

◆ FSMC_PCR4_ECCEN_Msk

#define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)

0x00000040

◆ FSMC_PCR4_ECCPS

#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk

ECCPS[2:0] bits (ECC page size)

◆ FSMC_PCR4_ECCPS_0

#define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)

0x00020000

◆ FSMC_PCR4_ECCPS_1

#define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)

0x00040000

◆ FSMC_PCR4_ECCPS_2

#define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)

0x00080000

◆ FSMC_PCR4_ECCPS_Msk

#define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)

0x000E0000

◆ FSMC_PCR4_PBKEN

#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR4_PBKEN_Msk

#define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)

0x00000004

◆ FSMC_PCR4_PTYP

#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk

Memory type

◆ FSMC_PCR4_PTYP_Msk

#define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)

0x00000008

◆ FSMC_PCR4_PWAITEN

#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk

Wait feature enable bit

◆ FSMC_PCR4_PWAITEN_Msk

#define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)

0x00000002

◆ FSMC_PCR4_PWID

#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR4_PWID_0

#define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)

0x00000010

◆ FSMC_PCR4_PWID_1

#define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)

0x00000020

◆ FSMC_PCR4_PWID_Msk

#define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)

0x00000030

◆ FSMC_PCR4_TAR

#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR4_TAR_0

#define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)

0x00002000

◆ FSMC_PCR4_TAR_1

#define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)

0x00004000

◆ FSMC_PCR4_TAR_2

#define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)

0x00008000

◆ FSMC_PCR4_TAR_3

#define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)

0x00010000

◆ FSMC_PCR4_TAR_Msk

#define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)

0x0001E000

◆ FSMC_PCR4_TCLR

#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR4_TCLR_0

#define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)

0x00000200

◆ FSMC_PCR4_TCLR_1

#define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)

0x00000400

◆ FSMC_PCR4_TCLR_2

#define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)

0x00000800

◆ FSMC_PCR4_TCLR_3

#define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)

0x00001000

◆ FSMC_PCR4_TCLR_Msk

#define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)

0x00001E00

◆ FSMC_PIO4_IOHIZ4

#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

◆ FSMC_PIO4_IOHIZ4_0

#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)

0x01000000

◆ FSMC_PIO4_IOHIZ4_1

#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)

0x02000000

◆ FSMC_PIO4_IOHIZ4_2

#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)

0x04000000

◆ FSMC_PIO4_IOHIZ4_3

#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)

0x08000000

◆ FSMC_PIO4_IOHIZ4_4

#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)

0x10000000

◆ FSMC_PIO4_IOHIZ4_5

#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)

0x20000000

◆ FSMC_PIO4_IOHIZ4_6

#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)

0x40000000

◆ FSMC_PIO4_IOHIZ4_7

#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)

0x80000000

◆ FSMC_PIO4_IOHIZ4_Msk

#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)

0xFF000000

◆ FSMC_PIO4_IOHOLD4

#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk

IOHOLD4[7:0] bits (I/O 4 hold time)

◆ FSMC_PIO4_IOHOLD4_0

#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)

0x00010000

◆ FSMC_PIO4_IOHOLD4_1

#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)

0x00020000

◆ FSMC_PIO4_IOHOLD4_2

#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)

0x00040000

◆ FSMC_PIO4_IOHOLD4_3

#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)

0x00080000

◆ FSMC_PIO4_IOHOLD4_4

#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)

0x00100000

◆ FSMC_PIO4_IOHOLD4_5

#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)

0x00200000

◆ FSMC_PIO4_IOHOLD4_6

#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)

0x00400000

◆ FSMC_PIO4_IOHOLD4_7

#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)

0x00800000

◆ FSMC_PIO4_IOHOLD4_Msk

#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)

0x00FF0000

◆ FSMC_PIO4_IOSET4

#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk

IOSET4[7:0] bits (I/O 4 setup time)

◆ FSMC_PIO4_IOSET4_0

#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)

0x00000001

◆ FSMC_PIO4_IOSET4_1

#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)

0x00000002

◆ FSMC_PIO4_IOSET4_2

#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)

0x00000004

◆ FSMC_PIO4_IOSET4_3

#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)

0x00000008

◆ FSMC_PIO4_IOSET4_4

#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)

0x00000010

◆ FSMC_PIO4_IOSET4_5

#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)

0x00000020

◆ FSMC_PIO4_IOSET4_6

#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)

0x00000040

◆ FSMC_PIO4_IOSET4_7

#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)

0x00000080

◆ FSMC_PIO4_IOSET4_Msk

#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)

0x000000FF

◆ FSMC_PIO4_IOWAIT4

#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk

IOWAIT4[7:0] bits (I/O 4 wait time)

◆ FSMC_PIO4_IOWAIT4_0

#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)

0x00000100

◆ FSMC_PIO4_IOWAIT4_1

#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)

0x00000200

◆ FSMC_PIO4_IOWAIT4_2

#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)

0x00000400

◆ FSMC_PIO4_IOWAIT4_3

#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)

0x00000800

◆ FSMC_PIO4_IOWAIT4_4

#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)

0x00001000

◆ FSMC_PIO4_IOWAIT4_5

#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)

0x00002000

◆ FSMC_PIO4_IOWAIT4_6

#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)

0x00004000

◆ FSMC_PIO4_IOWAIT4_7

#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)

0x00008000

◆ FSMC_PIO4_IOWAIT4_Msk

#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)

0x0000FF00

◆ FSMC_PMEM2_MEMHIZ2

#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

◆ FSMC_PMEM2_MEMHIZ2_0

#define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x01000000

◆ FSMC_PMEM2_MEMHIZ2_1

#define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x02000000

◆ FSMC_PMEM2_MEMHIZ2_2

#define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x04000000

◆ FSMC_PMEM2_MEMHIZ2_3

#define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x08000000

◆ FSMC_PMEM2_MEMHIZ2_4

#define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x10000000

◆ FSMC_PMEM2_MEMHIZ2_5

#define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x20000000

◆ FSMC_PMEM2_MEMHIZ2_6

#define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x40000000

◆ FSMC_PMEM2_MEMHIZ2_7

#define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)

0x80000000

◆ FSMC_PMEM2_MEMHIZ2_Msk

#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)

0xFF000000

◆ FSMC_PMEM2_MEMHOLD2

#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk

MEMHOLD2[7:0] bits (Common memory 2 hold time)

◆ FSMC_PMEM2_MEMHOLD2_0

#define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00010000

◆ FSMC_PMEM2_MEMHOLD2_1

#define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00020000

◆ FSMC_PMEM2_MEMHOLD2_2

#define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00040000

◆ FSMC_PMEM2_MEMHOLD2_3

#define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00080000

◆ FSMC_PMEM2_MEMHOLD2_4

#define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00100000

◆ FSMC_PMEM2_MEMHOLD2_5

#define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00200000

◆ FSMC_PMEM2_MEMHOLD2_6

#define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00400000

◆ FSMC_PMEM2_MEMHOLD2_7

#define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00800000

◆ FSMC_PMEM2_MEMHOLD2_Msk

#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)

0x00FF0000

◆ FSMC_PMEM2_MEMSET2

#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk

MEMSET2[7:0] bits (Common memory 2 setup time)

◆ FSMC_PMEM2_MEMSET2_0

#define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000001

◆ FSMC_PMEM2_MEMSET2_1

#define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000002

◆ FSMC_PMEM2_MEMSET2_2

#define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000004

◆ FSMC_PMEM2_MEMSET2_3

#define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000008

◆ FSMC_PMEM2_MEMSET2_4

#define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000010

◆ FSMC_PMEM2_MEMSET2_5

#define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000020

◆ FSMC_PMEM2_MEMSET2_6

#define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000040

◆ FSMC_PMEM2_MEMSET2_7

#define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)

0x00000080

◆ FSMC_PMEM2_MEMSET2_Msk

#define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)

0x000000FF

◆ FSMC_PMEM2_MEMWAIT2

#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk

MEMWAIT2[7:0] bits (Common memory 2 wait time)

◆ FSMC_PMEM2_MEMWAIT2_0

#define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00000100

◆ FSMC_PMEM2_MEMWAIT2_1

#define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00000200

◆ FSMC_PMEM2_MEMWAIT2_2

#define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00000400

◆ FSMC_PMEM2_MEMWAIT2_3

#define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00000800

◆ FSMC_PMEM2_MEMWAIT2_4

#define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00001000

◆ FSMC_PMEM2_MEMWAIT2_5

#define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00002000

◆ FSMC_PMEM2_MEMWAIT2_6

#define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00004000

◆ FSMC_PMEM2_MEMWAIT2_7

#define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)

0x00008000

◆ FSMC_PMEM2_MEMWAIT2_Msk

#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)

0x0000FF00

◆ FSMC_PMEM3_MEMHIZ3

#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

◆ FSMC_PMEM3_MEMHIZ3_0

#define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x01000000

◆ FSMC_PMEM3_MEMHIZ3_1

#define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x02000000

◆ FSMC_PMEM3_MEMHIZ3_2

#define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x04000000

◆ FSMC_PMEM3_MEMHIZ3_3

#define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x08000000

◆ FSMC_PMEM3_MEMHIZ3_4

#define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x10000000

◆ FSMC_PMEM3_MEMHIZ3_5

#define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x20000000

◆ FSMC_PMEM3_MEMHIZ3_6

#define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x40000000

◆ FSMC_PMEM3_MEMHIZ3_7

#define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)

0x80000000

◆ FSMC_PMEM3_MEMHIZ3_Msk

#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)

0xFF000000

◆ FSMC_PMEM3_MEMHOLD3

#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk

MEMHOLD3[7:0] bits (Common memory 3 hold time)

◆ FSMC_PMEM3_MEMHOLD3_0

#define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00010000

◆ FSMC_PMEM3_MEMHOLD3_1

#define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00020000

◆ FSMC_PMEM3_MEMHOLD3_2

#define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00040000

◆ FSMC_PMEM3_MEMHOLD3_3

#define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00080000

◆ FSMC_PMEM3_MEMHOLD3_4

#define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00100000

◆ FSMC_PMEM3_MEMHOLD3_5

#define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00200000

◆ FSMC_PMEM3_MEMHOLD3_6

#define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00400000

◆ FSMC_PMEM3_MEMHOLD3_7

#define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00800000

◆ FSMC_PMEM3_MEMHOLD3_Msk

#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)

0x00FF0000

◆ FSMC_PMEM3_MEMSET3

#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk

MEMSET3[7:0] bits (Common memory 3 setup time)

◆ FSMC_PMEM3_MEMSET3_0

#define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000001

◆ FSMC_PMEM3_MEMSET3_1

#define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000002

◆ FSMC_PMEM3_MEMSET3_2

#define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000004

◆ FSMC_PMEM3_MEMSET3_3

#define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000008

◆ FSMC_PMEM3_MEMSET3_4

#define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000010

◆ FSMC_PMEM3_MEMSET3_5

#define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000020

◆ FSMC_PMEM3_MEMSET3_6

#define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000040

◆ FSMC_PMEM3_MEMSET3_7

#define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)

0x00000080

◆ FSMC_PMEM3_MEMSET3_Msk

#define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)

0x000000FF

◆ FSMC_PMEM3_MEMWAIT3

#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk

MEMWAIT3[7:0] bits (Common memory 3 wait time)

◆ FSMC_PMEM3_MEMWAIT3_0

#define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00000100

◆ FSMC_PMEM3_MEMWAIT3_1

#define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00000200

◆ FSMC_PMEM3_MEMWAIT3_2

#define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00000400

◆ FSMC_PMEM3_MEMWAIT3_3

#define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00000800

◆ FSMC_PMEM3_MEMWAIT3_4

#define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00001000

◆ FSMC_PMEM3_MEMWAIT3_5

#define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00002000

◆ FSMC_PMEM3_MEMWAIT3_6

#define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00004000

◆ FSMC_PMEM3_MEMWAIT3_7

#define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)

0x00008000

◆ FSMC_PMEM3_MEMWAIT3_Msk

#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)

0x0000FF00

◆ FSMC_PMEM4_MEMHIZ4

#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

◆ FSMC_PMEM4_MEMHIZ4_0

#define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x01000000

◆ FSMC_PMEM4_MEMHIZ4_1

#define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x02000000

◆ FSMC_PMEM4_MEMHIZ4_2

#define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x04000000

◆ FSMC_PMEM4_MEMHIZ4_3

#define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x08000000

◆ FSMC_PMEM4_MEMHIZ4_4

#define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x10000000

◆ FSMC_PMEM4_MEMHIZ4_5

#define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x20000000

◆ FSMC_PMEM4_MEMHIZ4_6

#define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x40000000

◆ FSMC_PMEM4_MEMHIZ4_7

#define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)

0x80000000

◆ FSMC_PMEM4_MEMHIZ4_Msk

#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)

0xFF000000

◆ FSMC_PMEM4_MEMHOLD4

#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk

MEMHOLD4[7:0] bits (Common memory 4 hold time)

◆ FSMC_PMEM4_MEMHOLD4_0

#define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00010000

◆ FSMC_PMEM4_MEMHOLD4_1

#define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00020000

◆ FSMC_PMEM4_MEMHOLD4_2

#define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00040000

◆ FSMC_PMEM4_MEMHOLD4_3

#define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00080000

◆ FSMC_PMEM4_MEMHOLD4_4

#define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00100000

◆ FSMC_PMEM4_MEMHOLD4_5

#define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00200000

◆ FSMC_PMEM4_MEMHOLD4_6

#define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00400000

◆ FSMC_PMEM4_MEMHOLD4_7

#define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00800000

◆ FSMC_PMEM4_MEMHOLD4_Msk

#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)

0x00FF0000

◆ FSMC_PMEM4_MEMSET4

#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk

MEMSET4[7:0] bits (Common memory 4 setup time)

◆ FSMC_PMEM4_MEMSET4_0

#define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000001

◆ FSMC_PMEM4_MEMSET4_1

#define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000002

◆ FSMC_PMEM4_MEMSET4_2

#define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000004

◆ FSMC_PMEM4_MEMSET4_3

#define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000008

◆ FSMC_PMEM4_MEMSET4_4

#define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000010

◆ FSMC_PMEM4_MEMSET4_5

#define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000020

◆ FSMC_PMEM4_MEMSET4_6

#define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000040

◆ FSMC_PMEM4_MEMSET4_7

#define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)

0x00000080

◆ FSMC_PMEM4_MEMSET4_Msk

#define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)

0x000000FF

◆ FSMC_PMEM4_MEMWAIT4

#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk

MEMWAIT4[7:0] bits (Common memory 4 wait time)

◆ FSMC_PMEM4_MEMWAIT4_0

#define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00000100

◆ FSMC_PMEM4_MEMWAIT4_1

#define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00000200

◆ FSMC_PMEM4_MEMWAIT4_2

#define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00000400

◆ FSMC_PMEM4_MEMWAIT4_3

#define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00000800

◆ FSMC_PMEM4_MEMWAIT4_4

#define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00001000

◆ FSMC_PMEM4_MEMWAIT4_5

#define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00002000

◆ FSMC_PMEM4_MEMWAIT4_6

#define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00004000

◆ FSMC_PMEM4_MEMWAIT4_7

#define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)

0x00008000

◆ FSMC_PMEM4_MEMWAIT4_Msk

#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)

0x0000FF00

◆ FSMC_SR2_FEMPT

#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk

FIFO empty

◆ FSMC_SR2_FEMPT_Msk

#define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)

0x00000040

◆ FSMC_SR2_IFEN

#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR2_IFEN_Msk

#define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)

0x00000020

◆ FSMC_SR2_IFS

#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk

Interrupt Falling Edge status

◆ FSMC_SR2_IFS_Msk

#define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)

0x00000004

◆ FSMC_SR2_ILEN

#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk

Interrupt Level detection Enable bit

◆ FSMC_SR2_ILEN_Msk

#define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)

0x00000010

◆ FSMC_SR2_ILS

#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk

Interrupt Level status

◆ FSMC_SR2_ILS_Msk

#define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)

0x00000002

◆ FSMC_SR2_IREN

#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR2_IREN_Msk

#define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)

0x00000008

◆ FSMC_SR2_IRS

#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk

Interrupt Rising Edge status

◆ FSMC_SR2_IRS_Msk

#define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)

0x00000001

◆ FSMC_SR3_FEMPT

#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk

FIFO empty

◆ FSMC_SR3_FEMPT_Msk

#define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)

0x00000040

◆ FSMC_SR3_IFEN

#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR3_IFEN_Msk

#define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)

0x00000020

◆ FSMC_SR3_IFS

#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk

Interrupt Falling Edge status

◆ FSMC_SR3_IFS_Msk

#define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)

0x00000004

◆ FSMC_SR3_ILEN

#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk

Interrupt Level detection Enable bit

◆ FSMC_SR3_ILEN_Msk

#define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)

0x00000010

◆ FSMC_SR3_ILS

#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk

Interrupt Level status

◆ FSMC_SR3_ILS_Msk

#define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)

0x00000002

◆ FSMC_SR3_IREN

#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR3_IREN_Msk

#define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)

0x00000008

◆ FSMC_SR3_IRS

#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk

Interrupt Rising Edge status

◆ FSMC_SR3_IRS_Msk

#define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)

0x00000001

◆ FSMC_SR4_FEMPT

#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk

FIFO empty

◆ FSMC_SR4_FEMPT_Msk

#define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)

0x00000040

◆ FSMC_SR4_IFEN

#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR4_IFEN_Msk

#define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)

0x00000020

◆ FSMC_SR4_IFS

#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk

Interrupt Falling Edge status

◆ FSMC_SR4_IFS_Msk

#define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)

0x00000004

◆ FSMC_SR4_ILEN

#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk

Interrupt Level detection Enable bit

◆ FSMC_SR4_ILEN_Msk

#define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)

0x00000010

◆ FSMC_SR4_ILS

#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk

Interrupt Level status

◆ FSMC_SR4_ILS_Msk

#define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)

0x00000002

◆ FSMC_SR4_IREN

#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR4_IREN_Msk

#define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)

0x00000008

◆ FSMC_SR4_IRS

#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk

Interrupt Rising Edge status

◆ FSMC_SR4_IRS_Msk

#define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)

0x00000001

◆ GPIO_AFRH_AFSEL10_0

#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

0x00000100

◆ GPIO_AFRH_AFSEL10_1

#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

0x00000200

◆ GPIO_AFRH_AFSEL10_2

#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

0x00000400

◆ GPIO_AFRH_AFSEL10_3

#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

0x00000800

◆ GPIO_AFRH_AFSEL10_Msk

#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

0x00000F00

◆ GPIO_AFRH_AFSEL11_0

#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

0x00001000

◆ GPIO_AFRH_AFSEL11_1

#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

0x00002000

◆ GPIO_AFRH_AFSEL11_2

#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

0x00004000

◆ GPIO_AFRH_AFSEL11_3

#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

0x00008000

◆ GPIO_AFRH_AFSEL11_Msk

#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

0x0000F000

◆ GPIO_AFRH_AFSEL12_0

#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

0x00010000

◆ GPIO_AFRH_AFSEL12_1

#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

0x00020000

◆ GPIO_AFRH_AFSEL12_2

#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

0x00040000

◆ GPIO_AFRH_AFSEL12_3

#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

0x00080000

◆ GPIO_AFRH_AFSEL12_Msk

#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

0x000F0000

◆ GPIO_AFRH_AFSEL13_0

#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

0x00100000

◆ GPIO_AFRH_AFSEL13_1

#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

0x00200000

◆ GPIO_AFRH_AFSEL13_2

#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

0x00400000

◆ GPIO_AFRH_AFSEL13_3

#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

0x00800000

◆ GPIO_AFRH_AFSEL13_Msk

#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

0x00F00000

◆ GPIO_AFRH_AFSEL14_0

#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

0x01000000

◆ GPIO_AFRH_AFSEL14_1

#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

0x02000000

◆ GPIO_AFRH_AFSEL14_2

#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

0x04000000

◆ GPIO_AFRH_AFSEL14_3

#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

0x08000000

◆ GPIO_AFRH_AFSEL14_Msk

#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

0x0F000000

◆ GPIO_AFRH_AFSEL15_0

#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

0x10000000

◆ GPIO_AFRH_AFSEL15_1

#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

0x20000000

◆ GPIO_AFRH_AFSEL15_2

#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

0x40000000

◆ GPIO_AFRH_AFSEL15_3

#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

0x80000000

◆ GPIO_AFRH_AFSEL15_Msk

#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

0xF0000000

◆ GPIO_AFRH_AFSEL8_0

#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

0x00000001

◆ GPIO_AFRH_AFSEL8_1

#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

0x00000002

◆ GPIO_AFRH_AFSEL8_2

#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

0x00000004

◆ GPIO_AFRH_AFSEL8_3

#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

0x00000008

◆ GPIO_AFRH_AFSEL8_Msk

#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

0x0000000F

◆ GPIO_AFRH_AFSEL9_0

#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

0x00000010

◆ GPIO_AFRH_AFSEL9_1

#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

0x00000020

◆ GPIO_AFRH_AFSEL9_2

#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

0x00000040

◆ GPIO_AFRH_AFSEL9_3

#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

0x00000080

◆ GPIO_AFRH_AFSEL9_Msk

#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

0x000000F0

◆ GPIO_AFRL_AFSEL0_0

#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

0x00000001

◆ GPIO_AFRL_AFSEL0_1

#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

0x00000002

◆ GPIO_AFRL_AFSEL0_2

#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

0x00000004

◆ GPIO_AFRL_AFSEL0_3

#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

0x00000008

◆ GPIO_AFRL_AFSEL0_Msk

#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

0x0000000F

◆ GPIO_AFRL_AFSEL1_0

#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

0x00000010

◆ GPIO_AFRL_AFSEL1_1

#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

0x00000020

◆ GPIO_AFRL_AFSEL1_2

#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

0x00000040

◆ GPIO_AFRL_AFSEL1_3

#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

0x00000080

◆ GPIO_AFRL_AFSEL1_Msk

#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

0x000000F0

◆ GPIO_AFRL_AFSEL2_0

#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

0x00000100

◆ GPIO_AFRL_AFSEL2_1

#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

0x00000200

◆ GPIO_AFRL_AFSEL2_2

#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

0x00000400

◆ GPIO_AFRL_AFSEL2_3

#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

0x00000800

◆ GPIO_AFRL_AFSEL2_Msk

#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

0x00000F00

◆ GPIO_AFRL_AFSEL3_0

#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

0x00001000

◆ GPIO_AFRL_AFSEL3_1

#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

0x00002000

◆ GPIO_AFRL_AFSEL3_2

#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

0x00004000

◆ GPIO_AFRL_AFSEL3_3

#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

0x00008000

◆ GPIO_AFRL_AFSEL3_Msk

#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

0x0000F000

◆ GPIO_AFRL_AFSEL4_0

#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

0x00010000

◆ GPIO_AFRL_AFSEL4_1

#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

0x00020000

◆ GPIO_AFRL_AFSEL4_2

#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

0x00040000

◆ GPIO_AFRL_AFSEL4_3

#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

0x00080000

◆ GPIO_AFRL_AFSEL4_Msk

#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

0x000F0000

◆ GPIO_AFRL_AFSEL5_0

#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

0x00100000

◆ GPIO_AFRL_AFSEL5_1

#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

0x00200000

◆ GPIO_AFRL_AFSEL5_2

#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

0x00400000

◆ GPIO_AFRL_AFSEL5_3

#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

0x00800000

◆ GPIO_AFRL_AFSEL5_Msk

#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

0x00F00000

◆ GPIO_AFRL_AFSEL6_0

#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

0x01000000

◆ GPIO_AFRL_AFSEL6_1

#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

0x02000000

◆ GPIO_AFRL_AFSEL6_2

#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

0x04000000

◆ GPIO_AFRL_AFSEL6_3

#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

0x08000000

◆ GPIO_AFRL_AFSEL6_Msk

#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

0x0F000000

◆ GPIO_AFRL_AFSEL7_0

#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

0x10000000

◆ GPIO_AFRL_AFSEL7_1

#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

0x20000000

◆ GPIO_AFRL_AFSEL7_2

#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

0x40000000

◆ GPIO_AFRL_AFSEL7_3

#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

0x80000000

◆ GPIO_AFRL_AFSEL7_Msk

#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

0xF0000000

◆ GPIO_BSRR_BR0_Msk

#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

0x00010000

◆ GPIO_BSRR_BR10_Msk

#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

0x04000000

◆ GPIO_BSRR_BR11_Msk

#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

0x08000000

◆ GPIO_BSRR_BR12_Msk

#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

0x10000000

◆ GPIO_BSRR_BR13_Msk

#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

0x20000000

◆ GPIO_BSRR_BR14_Msk

#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

0x40000000

◆ GPIO_BSRR_BR15_Msk

#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

0x80000000

◆ GPIO_BSRR_BR1_Msk

#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

0x00020000

◆ GPIO_BSRR_BR2_Msk

#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

0x00040000

◆ GPIO_BSRR_BR3_Msk

#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

0x00080000

◆ GPIO_BSRR_BR4_Msk

#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

0x00100000

◆ GPIO_BSRR_BR5_Msk

#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

0x00200000

◆ GPIO_BSRR_BR6_Msk

#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

0x00400000

◆ GPIO_BSRR_BR7_Msk

#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

0x00800000

◆ GPIO_BSRR_BR8_Msk

#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

0x01000000

◆ GPIO_BSRR_BR9_Msk

#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

0x02000000

◆ GPIO_BSRR_BS0_Msk

#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

0x00000001

◆ GPIO_BSRR_BS10_Msk

#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

0x00000400

◆ GPIO_BSRR_BS11_Msk

#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

0x00000800

◆ GPIO_BSRR_BS12_Msk

#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

0x00001000

◆ GPIO_BSRR_BS13_Msk

#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

0x00002000

◆ GPIO_BSRR_BS14_Msk

#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

0x00004000

◆ GPIO_BSRR_BS15_Msk

#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

0x00008000

◆ GPIO_BSRR_BS1_Msk

#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

0x00000002

◆ GPIO_BSRR_BS2_Msk

#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

0x00000004

◆ GPIO_BSRR_BS3_Msk

#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

0x00000008

◆ GPIO_BSRR_BS4_Msk

#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

0x00000010

◆ GPIO_BSRR_BS5_Msk

#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

0x00000020

◆ GPIO_BSRR_BS6_Msk

#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

0x00000040

◆ GPIO_BSRR_BS7_Msk

#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

0x00000080

◆ GPIO_BSRR_BS8_Msk

#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

0x00000100

◆ GPIO_BSRR_BS9_Msk

#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

0x00000200

◆ GPIO_IDR_ID0_Msk

#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

0x00000001

◆ GPIO_IDR_ID10_Msk

#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

0x00000400

◆ GPIO_IDR_ID11_Msk

#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

0x00000800

◆ GPIO_IDR_ID12_Msk

#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

0x00001000

◆ GPIO_IDR_ID13_Msk

#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

0x00002000

◆ GPIO_IDR_ID14_Msk

#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

0x00004000

◆ GPIO_IDR_ID15_Msk

#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

0x00008000

◆ GPIO_IDR_ID1_Msk

#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

0x00000002

◆ GPIO_IDR_ID2_Msk

#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

0x00000004

◆ GPIO_IDR_ID3_Msk

#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

0x00000008

◆ GPIO_IDR_ID4_Msk

#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

0x00000010

◆ GPIO_IDR_ID5_Msk

#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

0x00000020

◆ GPIO_IDR_ID6_Msk

#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

0x00000040

◆ GPIO_IDR_ID7_Msk

#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

0x00000080

◆ GPIO_IDR_ID8_Msk

#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

0x00000100

◆ GPIO_IDR_ID9_Msk

#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

0x00000200

◆ GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

0x00000001

◆ GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

0x00000400

◆ GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

0x00000800

◆ GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

0x00001000

◆ GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

0x00002000

◆ GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

0x00004000

◆ GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

0x00008000

◆ GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

0x00000002

◆ GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

0x00000004

◆ GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

0x00000008

◆ GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

0x00000010

◆ GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

0x00000020

◆ GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

0x00000040

◆ GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

0x00000080

◆ GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

0x00000100

◆ GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

0x00000200

◆ GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

0x00010000

◆ GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)

0x00000001

◆ GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)

0x00000002

◆ GPIO_MODER_MODER0_Msk

#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)

0x00000003

◆ GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)

0x00100000

◆ GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)

0x00200000

◆ GPIO_MODER_MODER10_Msk

#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)

0x00300000

◆ GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)

0x00400000

◆ GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)

0x00800000

◆ GPIO_MODER_MODER11_Msk

#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)

0x00C00000

◆ GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)

0x01000000

◆ GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)

0x02000000

◆ GPIO_MODER_MODER12_Msk

#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)

0x03000000

◆ GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)

0x04000000

◆ GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)

0x08000000

◆ GPIO_MODER_MODER13_Msk

#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)

0x0C000000

◆ GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)

0x10000000

◆ GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)

0x20000000

◆ GPIO_MODER_MODER14_Msk

#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)

0x30000000

◆ GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)

0x40000000

◆ GPIO_MODER_MODER15_1

#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)

0x80000000

◆ GPIO_MODER_MODER15_Msk

#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)

0xC0000000

◆ GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)

0x00000004

◆ GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)

0x00000008

◆ GPIO_MODER_MODER1_Msk

#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)

0x0000000C

◆ GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)

0x00000010

◆ GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)

0x00000020

◆ GPIO_MODER_MODER2_Msk

#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)

0x00000030

◆ GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)

0x00000040

◆ GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)

0x00000080

◆ GPIO_MODER_MODER3_Msk

#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)

0x000000C0

◆ GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)

0x00000100

◆ GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)

0x00000200

◆ GPIO_MODER_MODER4_Msk

#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)

0x00000300

◆ GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)

0x00000400

◆ GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)

0x00000800

◆ GPIO_MODER_MODER5_Msk

#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)

0x00000C00

◆ GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)

0x00001000

◆ GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)

0x00002000

◆ GPIO_MODER_MODER6_Msk

#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)

0x00003000

◆ GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)

0x00004000

◆ GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)

0x00008000

◆ GPIO_MODER_MODER7_Msk

#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)

0x0000C000

◆ GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)

0x00010000

◆ GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)

0x00020000

◆ GPIO_MODER_MODER8_Msk

#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)

0x00030000

◆ GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)

0x00040000

◆ GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)

0x00080000

◆ GPIO_MODER_MODER9_Msk

#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)

0x000C0000

◆ GPIO_ODR_OD0_Msk

#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

0x00000001

◆ GPIO_ODR_OD10_Msk

#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

0x00000400

◆ GPIO_ODR_OD11_Msk

#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

0x00000800

◆ GPIO_ODR_OD12_Msk

#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

0x00001000

◆ GPIO_ODR_OD13_Msk

#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

0x00002000

◆ GPIO_ODR_OD14_Msk

#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

0x00004000

◆ GPIO_ODR_OD15_Msk

#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

0x00008000

◆ GPIO_ODR_OD1_Msk

#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

0x00000002

◆ GPIO_ODR_OD2_Msk

#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

0x00000004

◆ GPIO_ODR_OD3_Msk

#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

0x00000008

◆ GPIO_ODR_OD4_Msk

#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

0x00000010

◆ GPIO_ODR_OD5_Msk

#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

0x00000020

◆ GPIO_ODR_OD6_Msk

#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

0x00000040

◆ GPIO_ODR_OD7_Msk

#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

0x00000080

◆ GPIO_ODR_OD8_Msk

#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

0x00000100

◆ GPIO_ODR_OD9_Msk

#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

0x00000200

◆ GPIO_OSPEEDR_OSPEED0_0

#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000001

◆ GPIO_OSPEEDR_OSPEED0_1

#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000002

◆ GPIO_OSPEEDR_OSPEED0_Msk

#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000003

◆ GPIO_OSPEEDR_OSPEED10_0

#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00100000

◆ GPIO_OSPEEDR_OSPEED10_1

#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00200000

◆ GPIO_OSPEEDR_OSPEED10_Msk

#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00300000

◆ GPIO_OSPEEDR_OSPEED11_0

#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00400000

◆ GPIO_OSPEEDR_OSPEED11_1

#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00800000

◆ GPIO_OSPEEDR_OSPEED11_Msk

#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00C00000

◆ GPIO_OSPEEDR_OSPEED12_0

#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x01000000

◆ GPIO_OSPEEDR_OSPEED12_1

#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x02000000

◆ GPIO_OSPEEDR_OSPEED12_Msk

#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x03000000

◆ GPIO_OSPEEDR_OSPEED13_0

#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x04000000

◆ GPIO_OSPEEDR_OSPEED13_1

#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x08000000

◆ GPIO_OSPEEDR_OSPEED13_Msk

#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x0C000000

◆ GPIO_OSPEEDR_OSPEED14_0

#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x10000000

◆ GPIO_OSPEEDR_OSPEED14_1

#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x20000000

◆ GPIO_OSPEEDR_OSPEED14_Msk

#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x30000000

◆ GPIO_OSPEEDR_OSPEED15_0

#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x40000000

◆ GPIO_OSPEEDR_OSPEED15_1

#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x80000000

◆ GPIO_OSPEEDR_OSPEED15_Msk

#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

0xC0000000

◆ GPIO_OSPEEDR_OSPEED1_0

#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000004

◆ GPIO_OSPEEDR_OSPEED1_1

#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000008

◆ GPIO_OSPEEDR_OSPEED1_Msk

#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x0000000C

◆ GPIO_OSPEEDR_OSPEED2_0

#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000010

◆ GPIO_OSPEEDR_OSPEED2_1

#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000020

◆ GPIO_OSPEEDR_OSPEED2_Msk

#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000030

◆ GPIO_OSPEEDR_OSPEED3_0

#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000040

◆ GPIO_OSPEEDR_OSPEED3_1

#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000080

◆ GPIO_OSPEEDR_OSPEED3_Msk

#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x000000C0

◆ GPIO_OSPEEDR_OSPEED4_0

#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000100

◆ GPIO_OSPEEDR_OSPEED4_1

#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000200

◆ GPIO_OSPEEDR_OSPEED4_Msk

#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000300

◆ GPIO_OSPEEDR_OSPEED5_0

#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000400

◆ GPIO_OSPEEDR_OSPEED5_1

#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000800

◆ GPIO_OSPEEDR_OSPEED5_Msk

#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000C00

◆ GPIO_OSPEEDR_OSPEED6_0

#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00001000

◆ GPIO_OSPEEDR_OSPEED6_1

#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00002000

◆ GPIO_OSPEEDR_OSPEED6_Msk

#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00003000

◆ GPIO_OSPEEDR_OSPEED7_0

#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00004000

◆ GPIO_OSPEEDR_OSPEED7_1

#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00008000

◆ GPIO_OSPEEDR_OSPEED7_Msk

#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x0000C000

◆ GPIO_OSPEEDR_OSPEED8_0

#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00010000

◆ GPIO_OSPEEDR_OSPEED8_1

#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00020000

◆ GPIO_OSPEEDR_OSPEED8_Msk

#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00030000

◆ GPIO_OSPEEDR_OSPEED9_0

#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00040000

◆ GPIO_OSPEEDR_OSPEED9_1

#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00080000

◆ GPIO_OSPEEDR_OSPEED9_Msk

#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x000C0000

◆ GPIO_OTYPER_OT0_Msk

#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

0x00000001

◆ GPIO_OTYPER_OT10_Msk

#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

0x00000400

◆ GPIO_OTYPER_OT11_Msk

#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

0x00000800

◆ GPIO_OTYPER_OT12_Msk

#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

0x00001000

◆ GPIO_OTYPER_OT13_Msk

#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

0x00002000

◆ GPIO_OTYPER_OT14_Msk

#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

0x00004000

◆ GPIO_OTYPER_OT15_Msk

#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

0x00008000

◆ GPIO_OTYPER_OT1_Msk

#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

0x00000002

◆ GPIO_OTYPER_OT2_Msk

#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

0x00000004

◆ GPIO_OTYPER_OT3_Msk

#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

0x00000008

◆ GPIO_OTYPER_OT4_Msk

#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

0x00000010

◆ GPIO_OTYPER_OT5_Msk

#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

0x00000020

◆ GPIO_OTYPER_OT6_Msk

#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

0x00000040

◆ GPIO_OTYPER_OT7_Msk

#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

0x00000080

◆ GPIO_OTYPER_OT8_Msk

#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

0x00000100

◆ GPIO_OTYPER_OT9_Msk

#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

0x00000200

◆ GPIO_PUPDR_PUPD0_0

#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

0x00000001

◆ GPIO_PUPDR_PUPD0_1

#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

0x00000002

◆ GPIO_PUPDR_PUPD0_Msk

#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

0x00000003

◆ GPIO_PUPDR_PUPD10_0

#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

0x00100000

◆ GPIO_PUPDR_PUPD10_1

#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

0x00200000

◆ GPIO_PUPDR_PUPD10_Msk

#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

0x00300000

◆ GPIO_PUPDR_PUPD11_0

#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

0x00400000

◆ GPIO_PUPDR_PUPD11_1

#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

0x00800000

◆ GPIO_PUPDR_PUPD11_Msk

#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

0x00C00000

◆ GPIO_PUPDR_PUPD12_0

#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

0x01000000

◆ GPIO_PUPDR_PUPD12_1

#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

0x02000000

◆ GPIO_PUPDR_PUPD12_Msk

#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

0x03000000

◆ GPIO_PUPDR_PUPD13_0

#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

0x04000000

◆ GPIO_PUPDR_PUPD13_1

#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

0x08000000

◆ GPIO_PUPDR_PUPD13_Msk

#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

0x0C000000

◆ GPIO_PUPDR_PUPD14_0

#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

0x10000000

◆ GPIO_PUPDR_PUPD14_1

#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

0x20000000

◆ GPIO_PUPDR_PUPD14_Msk

#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

0x30000000

◆ GPIO_PUPDR_PUPD15_0

#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

0x40000000

◆ GPIO_PUPDR_PUPD15_1

#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

0x80000000

◆ GPIO_PUPDR_PUPD15_Msk

#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

0xC0000000

◆ GPIO_PUPDR_PUPD1_0

#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

0x00000004

◆ GPIO_PUPDR_PUPD1_1

#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

0x00000008

◆ GPIO_PUPDR_PUPD1_Msk

#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

0x0000000C

◆ GPIO_PUPDR_PUPD2_0

#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

0x00000010

◆ GPIO_PUPDR_PUPD2_1

#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

0x00000020

◆ GPIO_PUPDR_PUPD2_Msk

#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

0x00000030

◆ GPIO_PUPDR_PUPD3_0

#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

0x00000040

◆ GPIO_PUPDR_PUPD3_1

#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

0x00000080

◆ GPIO_PUPDR_PUPD3_Msk

#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

0x000000C0

◆ GPIO_PUPDR_PUPD4_0

#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

0x00000100

◆ GPIO_PUPDR_PUPD4_1

#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

0x00000200

◆ GPIO_PUPDR_PUPD4_Msk

#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

0x00000300

◆ GPIO_PUPDR_PUPD5_0

#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

0x00000400

◆ GPIO_PUPDR_PUPD5_1

#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

0x00000800

◆ GPIO_PUPDR_PUPD5_Msk

#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

0x00000C00

◆ GPIO_PUPDR_PUPD6_0

#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

0x00001000

◆ GPIO_PUPDR_PUPD6_1

#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

0x00002000

◆ GPIO_PUPDR_PUPD6_Msk

#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

0x00003000

◆ GPIO_PUPDR_PUPD7_0

#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

0x00004000

◆ GPIO_PUPDR_PUPD7_1

#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

0x00008000

◆ GPIO_PUPDR_PUPD7_Msk

#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

0x0000C000

◆ GPIO_PUPDR_PUPD8_0

#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

0x00010000

◆ GPIO_PUPDR_PUPD8_1

#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

0x00020000

◆ GPIO_PUPDR_PUPD8_Msk

#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

0x00030000

◆ GPIO_PUPDR_PUPD9_0

#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

0x00040000

◆ GPIO_PUPDR_PUPD9_1

#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

0x00080000

◆ GPIO_PUPDR_PUPD9_Msk

#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

0x000C0000

◆ I2C_CCR_CCR

#define I2C_CCR_CCR I2C_CCR_CCR_Msk

Clock Control Register in Fast/Standard mode (Master mode)

◆ I2C_CCR_CCR_Msk

#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)

0x00000FFF

◆ I2C_CCR_DUTY

#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk

Fast Mode Duty Cycle

◆ I2C_CCR_DUTY_Msk

#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)

0x00004000

◆ I2C_CCR_FS

#define I2C_CCR_FS I2C_CCR_FS_Msk

I2C Master Mode Selection

◆ I2C_CCR_FS_Msk

#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)

0x00008000

◆ I2C_CR1_ACK

#define I2C_CR1_ACK I2C_CR1_ACK_Msk

Acknowledge Enable

◆ I2C_CR1_ACK_Msk

#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)

0x00000400

◆ I2C_CR1_ALERT

#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk

SMBus Alert

◆ I2C_CR1_ALERT_Msk

#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)

0x00002000

◆ I2C_CR1_ENARP

#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk

ARP Enable

◆ I2C_CR1_ENARP_Msk

#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)

0x00000010

◆ I2C_CR1_ENGC

#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk

General Call Enable

◆ I2C_CR1_ENGC_Msk

#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)

0x00000040

◆ I2C_CR1_ENPEC

#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk

PEC Enable

◆ I2C_CR1_ENPEC_Msk

#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)

0x00000020

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

Clock Stretching Disable (Slave mode)

◆ I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

0x00000080

◆ I2C_CR1_PE

#define I2C_CR1_PE I2C_CR1_PE_Msk

Peripheral Enable

◆ I2C_CR1_PE_Msk

#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

0x00000001

◆ I2C_CR1_PEC

#define I2C_CR1_PEC I2C_CR1_PEC_Msk

Packet Error Checking

◆ I2C_CR1_PEC_Msk

#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)

0x00001000

◆ I2C_CR1_POS

#define I2C_CR1_POS I2C_CR1_POS_Msk

Acknowledge/PEC Position (for data reception)

◆ I2C_CR1_POS_Msk

#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)

0x00000800

◆ I2C_CR1_SMBTYPE

#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk

SMBus Type

◆ I2C_CR1_SMBTYPE_Msk

#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)

0x00000008

◆ I2C_CR1_SMBUS

#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk

SMBus Mode

◆ I2C_CR1_SMBUS_Msk

#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)

0x00000002

◆ I2C_CR1_START

#define I2C_CR1_START I2C_CR1_START_Msk

Start Generation

◆ I2C_CR1_START_Msk

#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)

0x00000100

◆ I2C_CR1_STOP

#define I2C_CR1_STOP I2C_CR1_STOP_Msk

Stop Generation

◆ I2C_CR1_STOP_Msk

#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)

0x00000200

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk

Software Reset

◆ I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

0x00008000

◆ I2C_CR2_DMAEN

#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk

DMA Requests Enable

◆ I2C_CR2_DMAEN_Msk

#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)

0x00000800

◆ I2C_CR2_FREQ

#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk

FREQ[5:0] bits (Peripheral Clock Frequency)

◆ I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)

0x00000001

◆ I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)

0x00000002

◆ I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)

0x00000004

◆ I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)

0x00000008

◆ I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)

0x00000010

◆ I2C_CR2_FREQ_5

#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)

0x00000020

◆ I2C_CR2_FREQ_Msk

#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)

0x0000003F

◆ I2C_CR2_ITBUFEN

#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk

Buffer Interrupt Enable

◆ I2C_CR2_ITBUFEN_Msk

#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)

0x00000400

◆ I2C_CR2_ITERREN

#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk

Error Interrupt Enable

◆ I2C_CR2_ITERREN_Msk

#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)

0x00000100

◆ I2C_CR2_ITEVTEN

#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk

Event Interrupt Enable

◆ I2C_CR2_ITEVTEN_Msk

#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)

0x00000200

◆ I2C_CR2_LAST

#define I2C_CR2_LAST I2C_CR2_LAST_Msk

DMA Last Transfer

◆ I2C_CR2_LAST_Msk

#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)

0x00001000

◆ I2C_DR_DR

#define I2C_DR_DR I2C_DR_DR_Msk

8-bit Data Register

◆ I2C_DR_DR_Msk

#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)

0x000000FF

◆ I2C_OAR1_ADD0

#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk

Bit 0

◆ I2C_OAR1_ADD0_Msk

#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)

0x00000001

◆ I2C_OAR1_ADD1

#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk

Bit 1

◆ I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD1_7 0x000000FEU

Interface Address

◆ I2C_OAR1_ADD1_Msk

#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)

0x00000002

◆ I2C_OAR1_ADD2

#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk

Bit 2

◆ I2C_OAR1_ADD2_Msk

#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)

0x00000004

◆ I2C_OAR1_ADD3

#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk

Bit 3

◆ I2C_OAR1_ADD3_Msk

#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)

0x00000008

◆ I2C_OAR1_ADD4

#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk

Bit 4

◆ I2C_OAR1_ADD4_Msk

#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)

0x00000010

◆ I2C_OAR1_ADD5

#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk

Bit 5

◆ I2C_OAR1_ADD5_Msk

#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)

0x00000020

◆ I2C_OAR1_ADD6

#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk

Bit 6

◆ I2C_OAR1_ADD6_Msk

#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)

0x00000040

◆ I2C_OAR1_ADD7

#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk

Bit 7

◆ I2C_OAR1_ADD7_Msk

#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)

0x00000080

◆ I2C_OAR1_ADD8

#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk

Bit 8

◆ I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD8_9 0x00000300U

Interface Address

◆ I2C_OAR1_ADD8_Msk

#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)

0x00000100

◆ I2C_OAR1_ADD9

#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk

Bit 9

◆ I2C_OAR1_ADD9_Msk

#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)

0x00000200

◆ I2C_OAR1_ADDMODE

#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk

Addressing Mode (Slave mode)

◆ I2C_OAR1_ADDMODE_Msk

#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)

0x00008000

◆ I2C_OAR2_ADD2

#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk

Interface address

◆ I2C_OAR2_ADD2_Msk

#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)

0x000000FE

◆ I2C_OAR2_ENDUAL

#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk

Dual addressing mode enable

◆ I2C_OAR2_ENDUAL_Msk

#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)

0x00000001

◆ I2C_SR1_ADD10

#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk

10-bit header sent (Master mode)

◆ I2C_SR1_ADD10_Msk

#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)

0x00000008

◆ I2C_SR1_ADDR

#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk

Address sent (master mode)/matched (slave mode)

◆ I2C_SR1_ADDR_Msk

#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)

0x00000002

◆ I2C_SR1_AF

#define I2C_SR1_AF I2C_SR1_AF_Msk

Acknowledge Failure

◆ I2C_SR1_AF_Msk

#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)

0x00000400

◆ I2C_SR1_ARLO

#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk

Arbitration Lost (master mode)

◆ I2C_SR1_ARLO_Msk

#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)

0x00000200

◆ I2C_SR1_BERR

#define I2C_SR1_BERR I2C_SR1_BERR_Msk

Bus Error

◆ I2C_SR1_BERR_Msk

#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)

0x00000100

◆ I2C_SR1_BTF

#define I2C_SR1_BTF I2C_SR1_BTF_Msk

Byte Transfer Finished

◆ I2C_SR1_BTF_Msk

#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)

0x00000004

◆ I2C_SR1_OVR

#define I2C_SR1_OVR I2C_SR1_OVR_Msk

Overrun/Underrun

◆ I2C_SR1_OVR_Msk

#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)

0x00000800

◆ I2C_SR1_PECERR

#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk

PEC Error in reception

◆ I2C_SR1_PECERR_Msk

#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)

0x00001000

◆ I2C_SR1_RXNE

#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk

Data Register not Empty (receivers)

◆ I2C_SR1_RXNE_Msk

#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)

0x00000040

◆ I2C_SR1_SB

#define I2C_SR1_SB I2C_SR1_SB_Msk

Start Bit (Master mode)

◆ I2C_SR1_SB_Msk

#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)

0x00000001

◆ I2C_SR1_SMBALERT

#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk

SMBus Alert

◆ I2C_SR1_SMBALERT_Msk

#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)

0x00008000

◆ I2C_SR1_STOPF

#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk

Stop detection (Slave mode)

◆ I2C_SR1_STOPF_Msk

#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)

0x00000010

◆ I2C_SR1_TIMEOUT

#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk

Timeout or Tlow Error

◆ I2C_SR1_TIMEOUT_Msk

#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)

0x00004000

◆ I2C_SR1_TXE

#define I2C_SR1_TXE I2C_SR1_TXE_Msk

Data Register Empty (transmitters)

◆ I2C_SR1_TXE_Msk

#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)

0x00000080

◆ I2C_SR2_BUSY

#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk

Bus Busy

◆ I2C_SR2_BUSY_Msk

#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)

0x00000002

◆ I2C_SR2_DUALF

#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk

Dual Flag (Slave mode)

◆ I2C_SR2_DUALF_Msk

#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)

0x00000080

◆ I2C_SR2_GENCALL

#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk

General Call Address (Slave mode)

◆ I2C_SR2_GENCALL_Msk

#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)

0x00000010

◆ I2C_SR2_MSL

#define I2C_SR2_MSL I2C_SR2_MSL_Msk

Master/Slave

◆ I2C_SR2_MSL_Msk

#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)

0x00000001

◆ I2C_SR2_PEC

#define I2C_SR2_PEC I2C_SR2_PEC_Msk

Packet Error Checking Register

◆ I2C_SR2_PEC_Msk

#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)

0x0000FF00

◆ I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk

SMBus Device Default Address (Slave mode)

◆ I2C_SR2_SMBDEFAULT_Msk

#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)

0x00000020

◆ I2C_SR2_SMBHOST

#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk

SMBus Host Header (Slave mode)

◆ I2C_SR2_SMBHOST_Msk

#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)

0x00000040

◆ I2C_SR2_TRA

#define I2C_SR2_TRA I2C_SR2_TRA_Msk

Transmitter/Receiver

◆ I2C_SR2_TRA_Msk

#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)

0x00000004

◆ I2C_TRISE_TRISE

#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk

Maximum Rise Time in Fast/Standard mode (Master mode)

◆ I2C_TRISE_TRISE_Msk

#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)

0x0000003F

◆ IWDG_KR_KEY

#define IWDG_KR_KEY IWDG_KR_KEY_Msk

Key value (write only, read 0000h)

◆ IWDG_KR_KEY_Msk

#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

0x0000FFFF

◆ IWDG_PR_PR

#define IWDG_PR_PR IWDG_PR_PR_Msk

PR[2:0] (Prescaler divider)

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

0x01

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

0x02

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

0x04

◆ IWDG_PR_PR_Msk

#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

0x00000007

◆ IWDG_RLR_RL

#define IWDG_RLR_RL IWDG_RLR_RL_Msk

Watchdog counter reload value

◆ IWDG_RLR_RL_Msk

#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

0x00000FFF

◆ IWDG_SR_PVU

#define IWDG_SR_PVU IWDG_SR_PVU_Msk

Watchdog prescaler value update

◆ IWDG_SR_PVU_Msk

#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

0x00000001

◆ IWDG_SR_RVU

#define IWDG_SR_RVU IWDG_SR_RVU_Msk

Watchdog counter reload value update

◆ IWDG_SR_RVU_Msk

#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

0x00000002

◆ PWR_CR_CSBF

#define PWR_CR_CSBF PWR_CR_CSBF_Msk

Clear Standby Flag

◆ PWR_CR_CSBF_Msk

#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)

0x00000008

◆ PWR_CR_CWUF

#define PWR_CR_CWUF PWR_CR_CWUF_Msk

Clear Wakeup Flag

◆ PWR_CR_CWUF_Msk

#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)

0x00000004

◆ PWR_CR_DBP

#define PWR_CR_DBP PWR_CR_DBP_Msk

Disable Backup Domain write protection

◆ PWR_CR_DBP_Msk

#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)

0x00000100

◆ PWR_CR_FPDS

#define PWR_CR_FPDS PWR_CR_FPDS_Msk

Flash power down in Stop mode

◆ PWR_CR_FPDS_Msk

#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)

0x00000200

◆ PWR_CR_LPDS

#define PWR_CR_LPDS PWR_CR_LPDS_Msk

Low-Power Deepsleep

◆ PWR_CR_LPDS_Msk

#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)

0x00000001

◆ PWR_CR_PDDS

#define PWR_CR_PDDS PWR_CR_PDDS_Msk

Power Down Deepsleep

◆ PWR_CR_PDDS_Msk

#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)

0x00000002

◆ PWR_CR_PLS

#define PWR_CR_PLS PWR_CR_PLS_Msk

PLS[2:0] bits (PVD Level Selection)

◆ PWR_CR_PLS_0

#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)

0x00000020

◆ PWR_CR_PLS_1

#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)

0x00000040

◆ PWR_CR_PLS_2

#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)

0x00000080 PVD level configuration

◆ PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV0 0x00000000U

PVD level 0

◆ PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV1 0x00000020U

PVD level 1

◆ PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV2 0x00000040U

PVD level 2

◆ PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV3 0x00000060U

PVD level 3

◆ PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV4 0x00000080U

PVD level 4

◆ PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV5 0x000000A0U

PVD level 5

◆ PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV6 0x000000C0U

PVD level 6

◆ PWR_CR_PLS_LEV7

#define PWR_CR_PLS_LEV7 0x000000E0U

PVD level 7

◆ PWR_CR_PLS_Msk

#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)

0x000000E0

◆ PWR_CR_PVDE

#define PWR_CR_PVDE PWR_CR_PVDE_Msk

Power Voltage Detector Enable

◆ PWR_CR_PVDE_Msk

#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)

0x00000010

◆ PWR_CR_VOS

#define PWR_CR_VOS PWR_CR_VOS_Msk

VOS bit (Regulator voltage scaling output selection)

◆ PWR_CR_VOS_Msk

#define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)

0x00004000

◆ PWR_CSR_BRE

#define PWR_CSR_BRE PWR_CSR_BRE_Msk

Backup regulator enable

◆ PWR_CSR_BRE_Msk

#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)

0x00000200

◆ PWR_CSR_BRR

#define PWR_CSR_BRR PWR_CSR_BRR_Msk

Backup regulator ready

◆ PWR_CSR_BRR_Msk

#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)

0x00000008

◆ PWR_CSR_EWUP

#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk

Enable WKUP pin

◆ PWR_CSR_EWUP_Msk

#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)

0x00000100

◆ PWR_CSR_PVDO

#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk

PVD Output

◆ PWR_CSR_PVDO_Msk

#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)

0x00000004

◆ PWR_CSR_SBF

#define PWR_CSR_SBF PWR_CSR_SBF_Msk

Standby Flag

◆ PWR_CSR_SBF_Msk

#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)

0x00000002

◆ PWR_CSR_VOSRDY

#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk

Regulator voltage scaling output selection ready

◆ PWR_CSR_VOSRDY_Msk

#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)

0x00004000

◆ PWR_CSR_WUF

#define PWR_CSR_WUF PWR_CSR_WUF_Msk

Wakeup Flag

◆ PWR_CSR_WUF_Msk

#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)

0x00000001

◆ RCC_AHB1ENR_BKPSRAMEN_Msk

#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)

0x00040000

◆ RCC_AHB1ENR_CCMDATARAMEN_Msk

#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)

0x00100000

◆ RCC_AHB1ENR_CRCEN_Msk

#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)

0x00001000

◆ RCC_AHB1ENR_DMA1EN_Msk

#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)

0x00200000

◆ RCC_AHB1ENR_DMA2EN_Msk

#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)

0x00400000

◆ RCC_AHB1ENR_ETHMACEN_Msk

#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)

0x02000000

◆ RCC_AHB1ENR_ETHMACPTPEN_Msk

#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)

0x10000000

◆ RCC_AHB1ENR_ETHMACRXEN_Msk

#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)

0x08000000

◆ RCC_AHB1ENR_ETHMACTXEN_Msk

#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)

0x04000000

◆ RCC_AHB1ENR_GPIOAEN_Msk

#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)

0x00000001

◆ RCC_AHB1ENR_GPIOBEN_Msk

#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)

0x00000002

◆ RCC_AHB1ENR_GPIOCEN_Msk

#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)

0x00000004

◆ RCC_AHB1ENR_GPIODEN_Msk

#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)

0x00000008

◆ RCC_AHB1ENR_GPIOEEN_Msk

#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)

0x00000010

◆ RCC_AHB1ENR_GPIOFEN_Msk

#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)

0x00000020

◆ RCC_AHB1ENR_GPIOGEN_Msk

#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)

0x00000040

◆ RCC_AHB1ENR_GPIOHEN_Msk

#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)

0x00000080

◆ RCC_AHB1ENR_GPIOIEN_Msk

#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)

0x00000100

◆ RCC_AHB1ENR_OTGHSEN_Msk

#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)

0x20000000

◆ RCC_AHB1ENR_OTGHSULPIEN_Msk

#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)

0x40000000

◆ RCC_AHB1LPENR_BKPSRAMLPEN_Msk

#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)

0x00040000

◆ RCC_AHB1LPENR_CRCLPEN_Msk

#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)

0x00001000

◆ RCC_AHB1LPENR_DMA1LPEN_Msk

#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)

0x00200000

◆ RCC_AHB1LPENR_DMA2LPEN_Msk

#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)

0x00400000

◆ RCC_AHB1LPENR_ETHMACLPEN_Msk

#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)

0x02000000

◆ RCC_AHB1LPENR_ETHMACPTPLPEN_Msk

#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)

0x10000000

◆ RCC_AHB1LPENR_ETHMACRXLPEN_Msk

#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)

0x08000000

◆ RCC_AHB1LPENR_ETHMACTXLPEN_Msk

#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)

0x04000000

◆ RCC_AHB1LPENR_FLITFLPEN_Msk

#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)

0x00008000

◆ RCC_AHB1LPENR_GPIOALPEN_Msk

#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)

0x00000001

◆ RCC_AHB1LPENR_GPIOBLPEN_Msk

#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)

0x00000002

◆ RCC_AHB1LPENR_GPIOCLPEN_Msk

#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)

0x00000004

◆ RCC_AHB1LPENR_GPIODLPEN_Msk

#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)

0x00000008

◆ RCC_AHB1LPENR_GPIOELPEN_Msk

#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)

0x00000010

◆ RCC_AHB1LPENR_GPIOFLPEN_Msk

#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)

0x00000020

◆ RCC_AHB1LPENR_GPIOGLPEN_Msk

#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)

0x00000040

◆ RCC_AHB1LPENR_GPIOHLPEN_Msk

#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)

0x00000080

◆ RCC_AHB1LPENR_GPIOILPEN_Msk

#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)

0x00000100

◆ RCC_AHB1LPENR_OTGHSLPEN_Msk

#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)

0x20000000

◆ RCC_AHB1LPENR_OTGHSULPILPEN_Msk

#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)

0x40000000

◆ RCC_AHB1LPENR_SRAM1LPEN_Msk

#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)

0x00010000

◆ RCC_AHB1LPENR_SRAM2LPEN_Msk

#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)

0x00020000

◆ RCC_AHB1RSTR_CRCRST_Msk

#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)

0x00001000

◆ RCC_AHB1RSTR_DMA1RST_Msk

#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)

0x00200000

◆ RCC_AHB1RSTR_DMA2RST_Msk

#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)

0x00400000

◆ RCC_AHB1RSTR_ETHMACRST_Msk

#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)

0x02000000

◆ RCC_AHB1RSTR_GPIOARST_Msk

#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)

0x00000001

◆ RCC_AHB1RSTR_GPIOBRST_Msk

#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)

0x00000002

◆ RCC_AHB1RSTR_GPIOCRST_Msk

#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)

0x00000004

◆ RCC_AHB1RSTR_GPIODRST_Msk

#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)

0x00000008

◆ RCC_AHB1RSTR_GPIOERST_Msk

#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)

0x00000010

◆ RCC_AHB1RSTR_GPIOFRST_Msk

#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)

0x00000020

◆ RCC_AHB1RSTR_GPIOGRST_Msk

#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)

0x00000040

◆ RCC_AHB1RSTR_GPIOHRST_Msk

#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)

0x00000080

◆ RCC_AHB1RSTR_GPIOIRST_Msk

#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)

0x00000100

◆ RCC_AHB1RSTR_OTGHRST_Msk

#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)

0x20000000

◆ RCC_AHB2_SUPPORT

#define RCC_AHB2_SUPPORT

AHB2 Bus is supported

◆ RCC_AHB2ENR_DCMIEN_Msk

#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)

0x00000001

◆ RCC_AHB2ENR_OTGFSEN_Msk

#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)

0x00000080

◆ RCC_AHB2ENR_RNGEN_Msk

#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)

0x00000040

◆ RCC_AHB2LPENR_DCMILPEN_Msk

#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)

0x00000001

◆ RCC_AHB2LPENR_OTGFSLPEN_Msk

#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)

0x00000080

◆ RCC_AHB2LPENR_RNGLPEN_Msk

#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)

0x00000040

◆ RCC_AHB2RSTR_DCMIRST_Msk

#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)

0x00000001

◆ RCC_AHB2RSTR_OTGFSRST_Msk

#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)

0x00000080

◆ RCC_AHB2RSTR_RNGRST_Msk

#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)

0x00000040

◆ RCC_AHB3_SUPPORT

#define RCC_AHB3_SUPPORT

AHB3 Bus is supported

◆ RCC_AHB3ENR_FSMCEN_Msk

#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)

0x00000001

◆ RCC_AHB3LPENR_FSMCLPEN_Msk

#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)

0x00000001

◆ RCC_AHB3RSTR_FSMCRST_Msk

#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)

0x00000001

◆ RCC_APB1ENR_CAN1EN_Msk

#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)

0x02000000

◆ RCC_APB1ENR_CAN2EN_Msk

#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)

0x04000000

◆ RCC_APB1ENR_DACEN_Msk

#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)

0x20000000

◆ RCC_APB1ENR_I2C1EN_Msk

#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)

0x00200000

◆ RCC_APB1ENR_I2C2EN_Msk

#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)

0x00400000

◆ RCC_APB1ENR_I2C3EN_Msk

#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)

0x00800000

◆ RCC_APB1ENR_PWREN_Msk

#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)

0x10000000

◆ RCC_APB1ENR_SPI2EN_Msk

#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)

0x00004000

◆ RCC_APB1ENR_SPI3EN_Msk

#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)

0x00008000

◆ RCC_APB1ENR_TIM12EN_Msk

#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)

0x00000040

◆ RCC_APB1ENR_TIM13EN_Msk

#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)

0x00000080

◆ RCC_APB1ENR_TIM14EN_Msk

#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)

0x00000100

◆ RCC_APB1ENR_TIM2EN_Msk

#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)

0x00000001

◆ RCC_APB1ENR_TIM3EN_Msk

#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)

0x00000002

◆ RCC_APB1ENR_TIM4EN_Msk

#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)

0x00000004

◆ RCC_APB1ENR_TIM5EN_Msk

#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)

0x00000008

◆ RCC_APB1ENR_TIM6EN_Msk

#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)

0x00000010

◆ RCC_APB1ENR_TIM7EN_Msk

#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)

0x00000020

◆ RCC_APB1ENR_UART4EN_Msk

#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)

0x00080000

◆ RCC_APB1ENR_UART5EN_Msk

#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)

0x00100000

◆ RCC_APB1ENR_USART2EN_Msk

#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)

0x00020000

◆ RCC_APB1ENR_USART3EN_Msk

#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)

0x00040000

◆ RCC_APB1ENR_WWDGEN_Msk

#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)

0x00000800

◆ RCC_APB1LPENR_CAN1LPEN_Msk

#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)

0x02000000

◆ RCC_APB1LPENR_CAN2LPEN_Msk

#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)

0x04000000

◆ RCC_APB1LPENR_DACLPEN_Msk

#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)

0x20000000

◆ RCC_APB1LPENR_I2C1LPEN_Msk

#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)

0x00200000

◆ RCC_APB1LPENR_I2C2LPEN_Msk

#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)

0x00400000

◆ RCC_APB1LPENR_I2C3LPEN_Msk

#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)

0x00800000

◆ RCC_APB1LPENR_PWRLPEN_Msk

#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)

0x10000000

◆ RCC_APB1LPENR_SPI2LPEN_Msk

#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)

0x00004000

◆ RCC_APB1LPENR_SPI3LPEN_Msk

#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)

0x00008000

◆ RCC_APB1LPENR_TIM12LPEN_Msk

#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)

0x00000040

◆ RCC_APB1LPENR_TIM13LPEN_Msk

#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)

0x00000080

◆ RCC_APB1LPENR_TIM14LPEN_Msk

#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)

0x00000100

◆ RCC_APB1LPENR_TIM2LPEN_Msk

#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)

0x00000001

◆ RCC_APB1LPENR_TIM3LPEN_Msk

#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)

0x00000002

◆ RCC_APB1LPENR_TIM4LPEN_Msk

#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)

0x00000004

◆ RCC_APB1LPENR_TIM5LPEN_Msk

#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)

0x00000008

◆ RCC_APB1LPENR_TIM6LPEN_Msk

#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)

0x00000010

◆ RCC_APB1LPENR_TIM7LPEN_Msk

#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)

0x00000020

◆ RCC_APB1LPENR_UART4LPEN_Msk

#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)

0x00080000

◆ RCC_APB1LPENR_UART5LPEN_Msk

#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)

0x00100000

◆ RCC_APB1LPENR_USART2LPEN_Msk

#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)

0x00020000

◆ RCC_APB1LPENR_USART3LPEN_Msk

#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)

0x00040000

◆ RCC_APB1LPENR_WWDGLPEN_Msk

#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)

0x00000800

◆ RCC_APB1RSTR_CAN1RST_Msk

#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)

0x02000000

◆ RCC_APB1RSTR_CAN2RST_Msk

#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)

0x04000000

◆ RCC_APB1RSTR_DACRST_Msk

#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)

0x20000000

◆ RCC_APB1RSTR_I2C1RST_Msk

#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)

0x00200000

◆ RCC_APB1RSTR_I2C2RST_Msk

#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)

0x00400000

◆ RCC_APB1RSTR_I2C3RST_Msk

#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)

0x00800000

◆ RCC_APB1RSTR_PWRRST_Msk

#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)

0x10000000

◆ RCC_APB1RSTR_SPI2RST_Msk

#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)

0x00004000

◆ RCC_APB1RSTR_SPI3RST_Msk

#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)

0x00008000

◆ RCC_APB1RSTR_TIM12RST_Msk

#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)

0x00000040

◆ RCC_APB1RSTR_TIM13RST_Msk

#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)

0x00000080

◆ RCC_APB1RSTR_TIM14RST_Msk

#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)

0x00000100

◆ RCC_APB1RSTR_TIM2RST_Msk

#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)

0x00000001

◆ RCC_APB1RSTR_TIM3RST_Msk

#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)

0x00000002

◆ RCC_APB1RSTR_TIM4RST_Msk

#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)

0x00000004

◆ RCC_APB1RSTR_TIM5RST_Msk

#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)

0x00000008

◆ RCC_APB1RSTR_TIM6RST_Msk

#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)

0x00000010

◆ RCC_APB1RSTR_TIM7RST_Msk

#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)

0x00000020

◆ RCC_APB1RSTR_UART4RST_Msk

#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)

0x00080000

◆ RCC_APB1RSTR_UART5RST_Msk

#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)

0x00100000

◆ RCC_APB1RSTR_USART2RST_Msk

#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)

0x00020000

◆ RCC_APB1RSTR_USART3RST_Msk

#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)

0x00040000

◆ RCC_APB1RSTR_WWDGRST_Msk

#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)

0x00000800

◆ RCC_APB2ENR_ADC1EN_Msk

#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)

0x00000100

◆ RCC_APB2ENR_ADC2EN_Msk

#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)

0x00000200

◆ RCC_APB2ENR_ADC3EN_Msk

#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)

0x00000400

◆ RCC_APB2ENR_SDIOEN_Msk

#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)

0x00000800

◆ RCC_APB2ENR_SPI1EN_Msk

#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

0x00001000

◆ RCC_APB2ENR_SYSCFGEN_Msk

#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

0x00004000

◆ RCC_APB2ENR_TIM10EN_Msk

#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)

0x00020000

◆ RCC_APB2ENR_TIM11EN_Msk

#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)

0x00040000

◆ RCC_APB2ENR_TIM1EN_Msk

#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

0x00000001

◆ RCC_APB2ENR_TIM8EN_Msk

#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)

0x00000002

◆ RCC_APB2ENR_TIM9EN_Msk

#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)

0x00010000

◆ RCC_APB2ENR_USART1EN_Msk

#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

0x00000010

◆ RCC_APB2ENR_USART6EN_Msk

#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)

0x00000020

◆ RCC_APB2LPENR_ADC1LPEN_Msk

#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)

0x00000100

◆ RCC_APB2LPENR_ADC2LPEN_Msk

#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)

0x00000200

◆ RCC_APB2LPENR_ADC3LPEN_Msk

#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)

0x00000400

◆ RCC_APB2LPENR_SDIOLPEN_Msk

#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)

0x00000800

◆ RCC_APB2LPENR_SPI1LPEN_Msk

#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)

0x00001000

◆ RCC_APB2LPENR_SYSCFGLPEN_Msk

#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)

0x00004000

◆ RCC_APB2LPENR_TIM10LPEN_Msk

#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)

0x00020000

◆ RCC_APB2LPENR_TIM11LPEN_Msk

#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)

0x00040000

◆ RCC_APB2LPENR_TIM1LPEN_Msk

#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)

0x00000001

◆ RCC_APB2LPENR_TIM8LPEN_Msk

#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)

0x00000002

◆ RCC_APB2LPENR_TIM9LPEN_Msk

#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)

0x00010000

◆ RCC_APB2LPENR_USART1LPEN_Msk

#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)

0x00000010

◆ RCC_APB2LPENR_USART6LPEN_Msk

#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)

0x00000020

◆ RCC_APB2RSTR_ADCRST_Msk

#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)

0x00000100

◆ RCC_APB2RSTR_SDIORST_Msk

#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)

0x00000800

◆ RCC_APB2RSTR_SPI1RST_Msk

#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

0x00001000

◆ RCC_APB2RSTR_SYSCFGRST_Msk

#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

0x00004000

◆ RCC_APB2RSTR_TIM10RST_Msk

#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)

0x00020000

◆ RCC_APB2RSTR_TIM11RST_Msk

#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)

0x00040000

◆ RCC_APB2RSTR_TIM1RST_Msk

#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

0x00000001

◆ RCC_APB2RSTR_TIM8RST_Msk

#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)

0x00000002

◆ RCC_APB2RSTR_TIM9RST_Msk

#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)

0x00010000

◆ RCC_APB2RSTR_USART1RST_Msk

#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

0x00000010

◆ RCC_APB2RSTR_USART6RST_Msk

#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)

0x00000020

◆ RCC_BDCR_BDRST_Msk

#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

0x00010000

◆ RCC_BDCR_LSEBYP_Msk

#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

0x00000004

◆ RCC_BDCR_LSEON_Msk

#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

0x00000001

◆ RCC_BDCR_LSERDY_Msk

#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

0x00000002

◆ RCC_BDCR_RTCEN_Msk

#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

0x00008000

◆ RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

0x00000100

◆ RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

0x00000200

◆ RCC_BDCR_RTCSEL_Msk

#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

0x00000300

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

HPRE[3:0] bits (AHB prescaler)

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

0x00000010

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

0x00000020

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

0x00000040

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

0x00000080

◆ RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1 0x00000000U

SYSCLK not divided

◆ RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV128 0x000000D0U

SYSCLK divided by 128

◆ RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV16 0x000000B0U

SYSCLK divided by 16

◆ RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV2 0x00000080U

SYSCLK divided by 2

◆ RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV256 0x000000E0U

SYSCLK divided by 256

◆ RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV4 0x00000090U

SYSCLK divided by 4

◆ RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_HPRE_DIV512 0x000000F0U

SYSCLK divided by 512 PPRE1 configuration

◆ RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV64 0x000000C0U

SYSCLK divided by 64

◆ RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV8 0x000000A0U

SYSCLK divided by 8

◆ RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

0x000000F0

◆ RCC_CFGR_I2SSRC_Msk

#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)

0x00800000

◆ RCC_CFGR_MCO1_0

#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)

0x00200000

◆ RCC_CFGR_MCO1_1

#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)

0x00400000

◆ RCC_CFGR_MCO1_Msk

#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)

0x00600000

◆ RCC_CFGR_MCO1PRE_0

#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)

0x01000000

◆ RCC_CFGR_MCO1PRE_1

#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)

0x02000000

◆ RCC_CFGR_MCO1PRE_2

#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)

0x04000000

◆ RCC_CFGR_MCO1PRE_Msk

#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)

0x07000000

◆ RCC_CFGR_MCO2_0

#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)

0x40000000

◆ RCC_CFGR_MCO2_1

#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)

0x80000000

◆ RCC_CFGR_MCO2_Msk

#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)

0xC0000000

◆ RCC_CFGR_MCO2PRE_0

#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)

0x08000000

◆ RCC_CFGR_MCO2PRE_1

#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)

0x10000000

◆ RCC_CFGR_MCO2PRE_2

#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)

0x20000000

◆ RCC_CFGR_MCO2PRE_Msk

#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)

0x38000000

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

PRE1[2:0] bits (APB1 prescaler)

◆ RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

0x00000400

◆ RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

0x00000800

◆ RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

0x00001000

◆ RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV1 0x00000000U

HCLK not divided

◆ RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE1_DIV16 0x00001C00U

HCLK divided by 16 PPRE2 configuration

◆ RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV2 0x00001000U

HCLK divided by 2

◆ RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4 0x00001400U

HCLK divided by 4

◆ RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV8 0x00001800U

HCLK divided by 8

◆ RCC_CFGR_PPRE1_Msk

#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

0x00001C00

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

PRE2[2:0] bits (APB2 prescaler)

◆ RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

0x00002000

◆ RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

0x00004000

◆ RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

0x00008000

◆ RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV1 0x00000000U

HCLK not divided

◆ RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PPRE2_DIV16 0x0000E000U

HCLK divided by 16 RTCPRE configuration

◆ RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2 0x00008000U

HCLK divided by 2

◆ RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV4 0x0000A000U

HCLK divided by 4

◆ RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV8 0x0000C000U

HCLK divided by 8

◆ RCC_CFGR_PPRE2_Msk

#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

0x0000E000

◆ RCC_CFGR_RTCPRE_0

#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)

0x00010000

◆ RCC_CFGR_RTCPRE_1

#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)

0x00020000

◆ RCC_CFGR_RTCPRE_2

#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)

0x00040000

◆ RCC_CFGR_RTCPRE_3

#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)

0x00080000

◆ RCC_CFGR_RTCPRE_4

#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)

0x00100000 MCO1 configuration

◆ RCC_CFGR_RTCPRE_Msk

#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)

0x001F0000

◆ RCC_CFGR_SW

#define RCC_CFGR_SW RCC_CFGR_SW_Msk

SW[1:0] bits (System clock Switch)

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

0x00000001

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

0x00000002

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE 0x00000001U

HSE selected as system clock

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI 0x00000000U

HSI selected as system clock

◆ RCC_CFGR_SW_Msk

#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

0x00000003

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL 0x00000002U

PLL selected as system clock SWS configuration

◆ RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Pos (0U)

< SW configuration

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk

SWS[1:0] bits (System Clock Switch Status)

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

0x00000004

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

0x00000008

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE 0x00000004U

HSE oscillator used as system clock

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI 0x00000000U

HSI oscillator used as system clock

◆ RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

0x0000000C

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL 0x00000008U

PLL used as system clock HPRE configuration

◆ RCC_CIR_CSSC_Msk

#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)

0x00800000

◆ RCC_CIR_CSSF_Msk

#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)

0x00000080

◆ RCC_CIR_HSERDYC_Msk

#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)

0x00080000

◆ RCC_CIR_HSERDYF_Msk

#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)

0x00000008

◆ RCC_CIR_HSERDYIE_Msk

#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)

0x00000800

◆ RCC_CIR_HSIRDYC_Msk

#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)

0x00040000

◆ RCC_CIR_HSIRDYF_Msk

#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)

0x00000004

◆ RCC_CIR_HSIRDYIE_Msk

#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)

0x00000400

◆ RCC_CIR_LSERDYC_Msk

#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)

0x00020000

◆ RCC_CIR_LSERDYF_Msk

#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)

0x00000002

◆ RCC_CIR_LSERDYIE_Msk

#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)

0x00000200

◆ RCC_CIR_LSIRDYC_Msk

#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)

0x00010000

◆ RCC_CIR_LSIRDYF_Msk

#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)

0x00000001

◆ RCC_CIR_LSIRDYIE_Msk

#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)

0x00000100

◆ RCC_CIR_PLLI2SRDYC_Msk

#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)

0x00200000

◆ RCC_CIR_PLLI2SRDYF_Msk

#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)

0x00000020

◆ RCC_CIR_PLLI2SRDYIE_Msk

#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)

0x00002000

◆ RCC_CIR_PLLRDYC_Msk

#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)

0x00100000

◆ RCC_CIR_PLLRDYF_Msk

#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)

0x00000010

◆ RCC_CIR_PLLRDYIE_Msk

#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)

0x00001000

◆ RCC_CR_CSSON_Msk

#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

0x00080000

◆ RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

0x00040000

◆ RCC_CR_HSEON_Msk

#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

0x00010000

◆ RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

0x00020000

◆ RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)

0x00000100

◆ RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)

0x00000200

◆ RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)

0x00000400

◆ RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)

0x00000800

◆ RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)

0x00001000

◆ RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)

0x00002000

◆ RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)

0x00004000

◆ RCC_CR_HSICAL_7

#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)

0x00008000

◆ RCC_CR_HSICAL_Msk

#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)

0x0000FF00

◆ RCC_CR_HSION_Msk

#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

0x00000001

◆ RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

0x00000002

◆ RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)

0x00000008

◆ RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)

0x00000010

◆ RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)

0x00000020

◆ RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)

0x00000040

◆ RCC_CR_HSITRIM_4

#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)

0x00000080

◆ RCC_CR_HSITRIM_Msk

#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)

0x000000F8

◆ RCC_CR_PLLI2SON_Msk

#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)

0x04000000

◆ RCC_CR_PLLI2SRDY_Msk

#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)

0x08000000

◆ RCC_CR_PLLON_Msk

#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

0x01000000

◆ RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

0x02000000

◆ RCC_CSR_BORRSTF_Msk

#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)

0x02000000

◆ RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

0x20000000

◆ RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

0x80000000

◆ RCC_CSR_LSION_Msk

#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

0x00000001

◆ RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

0x00000002

◆ RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

0x04000000

◆ RCC_CSR_PORRSTF_Msk

#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)

0x08000000

◆ RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

0x01000000

◆ RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

0x10000000

◆ RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

0x40000000

◆ RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)

0x00000001

◆ RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)

0x00000002

◆ RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)

0x00000004

◆ RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)

0x00000008

◆ RCC_PLLCFGR_PLLM_4

#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)

0x00000010

◆ RCC_PLLCFGR_PLLM_5

#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)

0x00000020

◆ RCC_PLLCFGR_PLLM_Msk

#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)

0x0000003F

◆ RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)

0x00000040

◆ RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)

0x00000080

◆ RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)

0x00000100

◆ RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)

0x00000200

◆ RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)

0x00000400

◆ RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)

0x00000800

◆ RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)

0x00001000

◆ RCC_PLLCFGR_PLLN_7

#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)

0x00002000

◆ RCC_PLLCFGR_PLLN_8

#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)

0x00004000

◆ RCC_PLLCFGR_PLLN_Msk

#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)

0x00007FC0

◆ RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)

0x00010000

◆ RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)

0x00020000

◆ RCC_PLLCFGR_PLLP_Msk

#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)

0x00030000

◆ RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)

0x01000000

◆ RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)

0x02000000

◆ RCC_PLLCFGR_PLLQ_2

#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)

0x04000000

◆ RCC_PLLCFGR_PLLQ_3

#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)

0x08000000

◆ RCC_PLLCFGR_PLLQ_Msk

#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)

0x0F000000

◆ RCC_PLLCFGR_PLLSRC_HSE_Msk

#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)

0x00400000

◆ RCC_PLLCFGR_PLLSRC_Msk

#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00400000

◆ RCC_PLLI2S_SUPPORT

#define RCC_PLLI2S_SUPPORT

Support PLLI2S oscillator

◆ RCC_PLLI2SCFGR_PLLI2SN_0

#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000040

◆ RCC_PLLI2SCFGR_PLLI2SN_1

#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000080

◆ RCC_PLLI2SCFGR_PLLI2SN_2

#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000100

◆ RCC_PLLI2SCFGR_PLLI2SN_3

#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000200

◆ RCC_PLLI2SCFGR_PLLI2SN_4

#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000400

◆ RCC_PLLI2SCFGR_PLLI2SN_5

#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00000800

◆ RCC_PLLI2SCFGR_PLLI2SN_6

#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00001000

◆ RCC_PLLI2SCFGR_PLLI2SN_7

#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00002000

◆ RCC_PLLI2SCFGR_PLLI2SN_8

#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00004000

◆ RCC_PLLI2SCFGR_PLLI2SN_Msk

#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)

0x00007FC0

◆ RCC_PLLI2SCFGR_PLLI2SR_0

#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)

0x10000000

◆ RCC_PLLI2SCFGR_PLLI2SR_1

#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)

0x20000000

◆ RCC_PLLI2SCFGR_PLLI2SR_2

#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)

0x40000000

◆ RCC_PLLI2SCFGR_PLLI2SR_Msk

#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)

0x70000000

◆ RCC_SSCGR_INCSTEP_Msk

#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)

0x0FFFE000

◆ RCC_SSCGR_MODPER_Msk

#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)

0x00001FFF

◆ RCC_SSCGR_SPREADSEL_Msk

#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)

0x40000000

◆ RCC_SSCGR_SSCGEN_Msk

#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)

0x80000000

◆ RNG_CR_IE_Msk

#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)

0x00000008

◆ RNG_CR_RNGEN_Msk

#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)

0x00000004

◆ RNG_SR_CECS_Msk

#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)

0x00000002

◆ RNG_SR_CEIS_Msk

#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)

0x00000020

◆ RNG_SR_DRDY_Msk

#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)

0x00000001

◆ RNG_SR_SECS_Msk

#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)

0x00000004

◆ RNG_SR_SEIS_Msk

#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)

0x00000040

◆ RTC_AF2_SUPPORT

#define RTC_AF2_SUPPORT

RTC Alternate Function 2 mapping support

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

0x10000000

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

0x20000000

◆ RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

0x30000000

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

0x01000000

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

0x02000000

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

0x04000000

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

0x08000000

◆ RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

0x0F000000

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

0x00100000

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

0x00200000

◆ RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

0x00300000

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

0x00010000

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

0x00020000

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

0x00040000

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

0x00080000

◆ RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

0x000F0000

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

0x00001000

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

0x00002000

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

0x00004000

◆ RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

0x00007000

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

0x00000100

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

0x00000200

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

0x00000400

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

0x00000800

◆ RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

0x00000F00

◆ RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

0x00000080

◆ RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

0x00008000

◆ RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

0x00800000

◆ RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

0x80000000

◆ RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

0x00400000

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

0x00000010

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

0x00000020

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

0x00000040

◆ RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

0x00000070

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

0x00000001

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

0x00000002

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

0x00000004

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

0x00000008

◆ RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

0x0000000F

◆ RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

0x10000000

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

0x20000000

◆ RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

0x30000000

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

0x01000000

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

0x02000000

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

0x04000000

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

0x08000000

◆ RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

0x0F000000

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

0x00100000

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

0x00200000

◆ RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

0x00300000

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

0x00010000

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

0x00020000

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

0x00040000

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

0x00080000

◆ RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

0x000F0000

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

0x00001000

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

0x00002000

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

0x00004000

◆ RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

0x00007000

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

0x00000100

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

0x00000200

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

0x00000400

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

0x00000800

◆ RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

0x00000F00

◆ RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

0x00000080

◆ RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

0x00008000

◆ RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

0x00800000

◆ RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

0x80000000

◆ RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

0x00400000

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

0x00000010

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

0x00000020

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

0x00000040

◆ RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

0x00000070

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

0x00000001

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

0x00000002

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

0x00000004

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

0x00000008

◆ RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

0x0000000F

◆ RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

0x00007FFF

◆ RTC_BKP0R_Msk

#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)

0xFFFFFFFF

◆ RTC_BKP10R_Msk

#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)

0xFFFFFFFF

◆ RTC_BKP11R_Msk

#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)

0xFFFFFFFF

◆ RTC_BKP12R_Msk

#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)

0xFFFFFFFF

◆ RTC_BKP13R_Msk

#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)

0xFFFFFFFF

◆ RTC_BKP14R_Msk

#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)

0xFFFFFFFF

◆ RTC_BKP15R_Msk

#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)

0xFFFFFFFF

◆ RTC_BKP16R_Msk

#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)

0xFFFFFFFF

◆ RTC_BKP17R_Msk

#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)

0xFFFFFFFF

◆ RTC_BKP18R_Msk

#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)

0xFFFFFFFF

◆ RTC_BKP19R_Msk

#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)

0xFFFFFFFF

◆ RTC_BKP1R_Msk

#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)

0xFFFFFFFF

◆ RTC_BKP2R_Msk

#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)

0xFFFFFFFF

◆ RTC_BKP3R_Msk

#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)

0xFFFFFFFF

◆ RTC_BKP4R_Msk

#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)

0xFFFFFFFF

◆ RTC_BKP5R_Msk

#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)

0xFFFFFFFF

◆ RTC_BKP6R_Msk

#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)

0xFFFFFFFF

◆ RTC_BKP7R_Msk

#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)

0xFFFFFFFF

◆ RTC_BKP8R_Msk

#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)

0xFFFFFFFF

◆ RTC_BKP9R_Msk

#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)

0xFFFFFFFF

◆ RTC_CALIBR_DC_Msk

#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)

0x0000001F

◆ RTC_CALIBR_DCS_Msk

#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)

0x00000080

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

0x00000001

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

0x00000002

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

0x00000004

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

0x00000008

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

0x00000010

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

0x00000020

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

0x00000040

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

0x00000080

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

0x00000100

◆ RTC_CALR_CALM_Msk

#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

0x000001FF

◆ RTC_CALR_CALP_Msk

#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

0x00008000

◆ RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

0x00002000

◆ RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

0x00004000

◆ RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

0x00010000

◆ RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

0x00000100

◆ RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

0x00001000

◆ RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

0x00000200

◆ RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

0x00002000

◆ RTC_CR_BKP_Msk

#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

0x00040000

◆ RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

0x00000020

◆ RTC_CR_COE_Msk

#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

0x00800000

◆ RTC_CR_COSEL_Msk

#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

0x00080000

◆ RTC_CR_DCE_Msk

#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)

0x00000080

◆ RTC_CR_FMT_Msk

#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

0x00000040

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

0x00200000

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

0x00400000

◆ RTC_CR_OSEL_Msk

#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

0x00600000

◆ RTC_CR_POL_Msk

#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

0x00100000

◆ RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

0x00000010

◆ RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

0x00020000

◆ RTC_CR_TSE_Msk

#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

0x00000800

◆ RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

0x00000008

◆ RTC_CR_TSIE_Msk

#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

0x00008000

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

0x00000001

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

0x00000002

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

0x00000004

◆ RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

0x00000007

◆ RTC_CR_WUTE_Msk

#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

0x00000400

◆ RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

0x00004000

◆ RTC_DR_DT_0

#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

0x00000010

◆ RTC_DR_DT_1

#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

0x00000020

◆ RTC_DR_DT_Msk

#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

0x00000030

◆ RTC_DR_DU_0

#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

0x00000001

◆ RTC_DR_DU_1

#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

0x00000002

◆ RTC_DR_DU_2

#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

0x00000004

◆ RTC_DR_DU_3

#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

0x00000008

◆ RTC_DR_DU_Msk

#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

0x0000000F

◆ RTC_DR_MT_Msk

#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

0x00001000

◆ RTC_DR_MU_0

#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

0x00000100

◆ RTC_DR_MU_1

#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

0x00000200

◆ RTC_DR_MU_2

#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

0x00000400

◆ RTC_DR_MU_3

#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

0x00000800

◆ RTC_DR_MU_Msk

#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

0x00000F00

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

0x00002000

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

0x00004000

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

0x00008000

◆ RTC_DR_WDU_Msk

#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

0x0000E000

◆ RTC_DR_YT_0

#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

0x00100000

◆ RTC_DR_YT_1

#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

0x00200000

◆ RTC_DR_YT_2

#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

0x00400000

◆ RTC_DR_YT_3

#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

0x00800000

◆ RTC_DR_YT_Msk

#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

0x00F00000

◆ RTC_DR_YU_0

#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

0x00010000

◆ RTC_DR_YU_1

#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

0x00020000

◆ RTC_DR_YU_2

#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

0x00040000

◆ RTC_DR_YU_3

#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

0x00080000

◆ RTC_DR_YU_Msk

#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

0x000F0000

◆ RTC_ISR_ALRAF_Msk

#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)

0x00000100

◆ RTC_ISR_ALRAWF_Msk

#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)

0x00000001

◆ RTC_ISR_ALRBF_Msk

#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)

0x00000200

◆ RTC_ISR_ALRBWF_Msk

#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)

0x00000002

◆ RTC_ISR_INIT_Msk

#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)

0x00000080

◆ RTC_ISR_INITF_Msk

#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)

0x00000040

◆ RTC_ISR_INITS_Msk

#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)

0x00000010

◆ RTC_ISR_RECALPF_Msk

#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)

0x00010000

◆ RTC_ISR_RSF_Msk

#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)

0x00000020

◆ RTC_ISR_SHPF_Msk

#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)

0x00000008

◆ RTC_ISR_TAMP1F_Msk

#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)

0x00002000

◆ RTC_ISR_TAMP2F_Msk

#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)

0x00004000

◆ RTC_ISR_TSF_Msk

#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)

0x00000800

◆ RTC_ISR_TSOVF_Msk

#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)

0x00001000

◆ RTC_ISR_WUTF_Msk

#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)

0x00000400

◆ RTC_ISR_WUTWF_Msk

#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)

0x00000004

◆ RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

0x007F0000

◆ RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

0x00007FFF

◆ RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

0x80000000

◆ RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

0x00007FFF

◆ RTC_SSR_SS_Msk

#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

0x0000FFFF

◆ RTC_TAFCR_ALARMOUTTYPE_Msk

#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)

0x00040000

◆ RTC_TAFCR_TAMP1E_Msk

#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)

0x00000001

◆ RTC_TAFCR_TAMP1INSEL_Msk

#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)

0x00010000

◆ RTC_TAFCR_TAMP1TRG_Msk

#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)

0x00000002

◆ RTC_TAFCR_TAMP2E_Msk

#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)

0x00000008

◆ RTC_TAFCR_TAMP2TRG_Msk

#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)

0x00000010

◆ RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)

0x00000800

◆ RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)

0x00001000

◆ RTC_TAFCR_TAMPFLT_Msk

#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)

0x00001800

◆ RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000100

◆ RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000200

◆ RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000400

◆ RTC_TAFCR_TAMPFREQ_Msk

#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000700

◆ RTC_TAFCR_TAMPIE_Msk

#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)

0x00000004

◆ RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00002000

◆ RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00004000

◆ RTC_TAFCR_TAMPPRCH_Msk

#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00006000

◆ RTC_TAFCR_TAMPPUDIS_Msk

#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)

0x00008000

◆ RTC_TAFCR_TAMPTS_Msk

#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)

0x00000080

◆ RTC_TAFCR_TSINSEL_Msk

#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)

0x00020000

◆ RTC_TAMPER2_SUPPORT

#define RTC_TAMPER2_SUPPORT

TAMPER 2 feature support

◆ RTC_TR_HT_0

#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

0x00100000

◆ RTC_TR_HT_1

#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

0x00200000

◆ RTC_TR_HT_Msk

#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

0x00300000

◆ RTC_TR_HU_0

#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

0x00010000

◆ RTC_TR_HU_1

#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

0x00020000

◆ RTC_TR_HU_2

#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

0x00040000

◆ RTC_TR_HU_3

#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

0x00080000

◆ RTC_TR_HU_Msk

#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

0x000F0000

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

0x00001000

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

0x00002000

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

0x00004000

◆ RTC_TR_MNT_Msk

#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

0x00007000

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

0x00000100

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

0x00000200

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

0x00000400

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

0x00000800

◆ RTC_TR_MNU_Msk

#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

0x00000F00

◆ RTC_TR_PM_Msk

#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

0x00400000

◆ RTC_TR_ST_0

#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

0x00000010

◆ RTC_TR_ST_1

#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

0x00000020

◆ RTC_TR_ST_2

#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

0x00000040

◆ RTC_TR_ST_Msk

#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

0x00000070

◆ RTC_TR_SU_0

#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

0x00000001

◆ RTC_TR_SU_1

#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

0x00000002

◆ RTC_TR_SU_2

#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

0x00000004

◆ RTC_TR_SU_3

#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

0x00000008

◆ RTC_TR_SU_Msk

#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

0x0000000F

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

0x00000010

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

0x00000020

◆ RTC_TSDR_DT_Msk

#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

0x00000030

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

0x00000001

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

0x00000002

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

0x00000004

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

0x00000008

◆ RTC_TSDR_DU_Msk

#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

0x0000000F

◆ RTC_TSDR_MT_Msk

#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

0x00001000

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

0x00000100

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

0x00000200

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

0x00000400

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

0x00000800

◆ RTC_TSDR_MU_Msk

#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

0x00000F00

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

0x00002000

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

0x00004000

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

0x00008000

◆ RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

0x0000E000

◆ RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

0x0000FFFF

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

0x00100000

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

0x00200000

◆ RTC_TSTR_HT_Msk

#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

0x00300000

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

0x00010000

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

0x00020000

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

0x00040000

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

0x00080000

◆ RTC_TSTR_HU_Msk

#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

0x000F0000

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

0x00001000

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

0x00002000

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

0x00004000

◆ RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

0x00007000

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

0x00000100

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

0x00000200

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

0x00000400

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

0x00000800

◆ RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

0x00000F00

◆ RTC_TSTR_PM_Msk

#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

0x00400000

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

0x00000010

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

0x00000020

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

0x00000040

◆ RTC_TSTR_ST_Msk

#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

0x00000070

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

0x00000001

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

0x00000002

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

0x00000004

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

0x00000008

◆ RTC_TSTR_SU_Msk

#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

0x0000000F

◆ RTC_WPR_KEY_Msk

#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

0x000000FF

◆ RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

0x0000FFFF

◆ SDIO_ARG_CMDARG

#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk

Command argument

◆ SDIO_ARG_CMDARG_Msk

#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)

0xFFFFFFFF

◆ SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk

Clock divider bypass enable bit

◆ SDIO_CLKCR_BYPASS_Msk

#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)

0x00000400

◆ SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk

Clock divide factor

◆ SDIO_CLKCR_CLKDIV_Msk

#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)

0x000000FF

◆ SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk

Clock enable bit

◆ SDIO_CLKCR_CLKEN_Msk

#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)

0x00000100

◆ SDIO_CLKCR_HWFC_EN

#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk

HW Flow Control enable

◆ SDIO_CLKCR_HWFC_EN_Msk

#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)

0x00004000

◆ SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk

SDIO_CK dephasing selection bit

◆ SDIO_CLKCR_NEGEDGE_Msk

#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)

0x00002000

◆ SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk

Power saving configuration bit

◆ SDIO_CLKCR_PWRSAV_Msk

#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)

0x00000200

◆ SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk

WIDBUS[1:0] bits (Wide bus mode enable bit)

◆ SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)

0x0800

◆ SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)

0x1000

◆ SDIO_CLKCR_WIDBUS_Msk

#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)

0x00001800

◆ SDIO_CMD_CEATACMD

#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk

CE-ATA command

◆ SDIO_CMD_CEATACMD_Msk

#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)

0x00004000

◆ SDIO_CMD_CMDINDEX

#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk

Command Index

◆ SDIO_CMD_CMDINDEX_Msk

#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)

0x0000003F

◆ SDIO_CMD_CPSMEN

#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk

Command path state machine (CPSM) Enable bit

◆ SDIO_CMD_CPSMEN_Msk

#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)

0x00000400

◆ SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk

Enable CMD completion

◆ SDIO_CMD_ENCMDCOMPL_Msk

#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)

0x00001000

◆ SDIO_CMD_NIEN

#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk

Not Interrupt Enable

◆ SDIO_CMD_NIEN_Msk

#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)

0x00002000

◆ SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk

SD I/O suspend command

◆ SDIO_CMD_SDIOSUSPEND_Msk

#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)

0x00000800

◆ SDIO_CMD_WAITINT

#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk

CPSM Waits for Interrupt Request

◆ SDIO_CMD_WAITINT_Msk

#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)

0x00000100

◆ SDIO_CMD_WAITPEND

#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk

CPSM Waits for ends of data transfer (CmdPend internal signal)

◆ SDIO_CMD_WAITPEND_Msk

#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)

0x00000200

◆ SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk

WAITRESP[1:0] bits (Wait for response bits)

◆ SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)

0x0040

◆ SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)

0x0080

◆ SDIO_CMD_WAITRESP_Msk

#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)

0x000000C0

◆ SDIO_DCOUNT_DATACOUNT

#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk

Data count value

◆ SDIO_DCOUNT_DATACOUNT_Msk

#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)

0x01FFFFFF

◆ SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk

DBLOCKSIZE[3:0] bits (Data block size)

◆ SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)

0x0010

◆ SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)

0x0020

◆ SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)

0x0040

◆ SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)

0x0080

◆ SDIO_DCTRL_DBLOCKSIZE_Msk

#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)

0x000000F0

◆ SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk

DMA enabled bit

◆ SDIO_DCTRL_DMAEN_Msk

#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)

0x00000008

◆ SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk

Data transfer direction selection

◆ SDIO_DCTRL_DTDIR_Msk

#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)

0x00000002

◆ SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk

Data transfer enabled bit

◆ SDIO_DCTRL_DTEN_Msk

#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)

0x00000001

◆ SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk

Data transfer mode selection

◆ SDIO_DCTRL_DTMODE_Msk

#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)

0x00000004

◆ SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk

Read wait mode

◆ SDIO_DCTRL_RWMOD_Msk

#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)

0x00000400

◆ SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk

Read wait start

◆ SDIO_DCTRL_RWSTART_Msk

#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)

0x00000100

◆ SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk

Read wait stop

◆ SDIO_DCTRL_RWSTOP_Msk

#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)

0x00000200

◆ SDIO_DCTRL_SDIOEN

#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk

SD I/O enable functions

◆ SDIO_DCTRL_SDIOEN_Msk

#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)

0x00000800

◆ SDIO_DLEN_DATALENGTH

#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk

Data length value

◆ SDIO_DLEN_DATALENGTH_Msk

#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)

0x01FFFFFF

◆ SDIO_DTIMER_DATATIME

#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk

Data timeout period.

◆ SDIO_DTIMER_DATATIME_Msk

#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)

0xFFFFFFFF

◆ SDIO_FIFO_FIFODATA

#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk

Receive and transmit FIFO data

◆ SDIO_FIFO_FIFODATA_Msk

#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)

0xFFFFFFFF

◆ SDIO_FIFOCNT_FIFOCOUNT

#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk

Remaining number of words to be written to or read from the FIFO

◆ SDIO_FIFOCNT_FIFOCOUNT_Msk

#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)

0x00FFFFFF

◆ SDIO_ICR_CCRCFAILC

#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk

CCRCFAIL flag clear bit

◆ SDIO_ICR_CCRCFAILC_Msk

#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)

0x00000001

◆ SDIO_ICR_CEATAENDC

#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk

CEATAEND flag clear bit

◆ SDIO_ICR_CEATAENDC_Msk

#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)

0x00800000

◆ SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk

CMDREND flag clear bit

◆ SDIO_ICR_CMDRENDC_Msk

#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)

0x00000040

◆ SDIO_ICR_CMDSENTC

#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk

CMDSENT flag clear bit

◆ SDIO_ICR_CMDSENTC_Msk

#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)

0x00000080

◆ SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk

CTIMEOUT flag clear bit

◆ SDIO_ICR_CTIMEOUTC_Msk

#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)

0x00000004

◆ SDIO_ICR_DATAENDC

#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk

DATAEND flag clear bit

◆ SDIO_ICR_DATAENDC_Msk

#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)

0x00000100

◆ SDIO_ICR_DBCKENDC

#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk

DBCKEND flag clear bit

◆ SDIO_ICR_DBCKENDC_Msk

#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)

0x00000400

◆ SDIO_ICR_DCRCFAILC

#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk

DCRCFAIL flag clear bit

◆ SDIO_ICR_DCRCFAILC_Msk

#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)

0x00000002

◆ SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk

DTIMEOUT flag clear bit

◆ SDIO_ICR_DTIMEOUTC_Msk

#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)

0x00000008

◆ SDIO_ICR_RXOVERRC

#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk

RXOVERR flag clear bit

◆ SDIO_ICR_RXOVERRC_Msk

#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)

0x00000020

◆ SDIO_ICR_SDIOITC

#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk

SDIOIT flag clear bit

◆ SDIO_ICR_SDIOITC_Msk

#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)

0x00400000

◆ SDIO_ICR_STBITERRC

#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk

STBITERR flag clear bit

◆ SDIO_ICR_STBITERRC_Msk

#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)

0x00000200

◆ SDIO_ICR_TXUNDERRC

#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk

TXUNDERR flag clear bit

◆ SDIO_ICR_TXUNDERRC_Msk

#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)

0x00000010

◆ SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk

Command CRC Fail Interrupt Enable

◆ SDIO_MASK_CCRCFAILIE_Msk

#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)

0x00000001

◆ SDIO_MASK_CEATAENDIE

#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk

CE-ATA command completion signal received Interrupt Enable

◆ SDIO_MASK_CEATAENDIE_Msk

#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)

0x00800000

◆ SDIO_MASK_CMDACTIE

#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk

CCommand Acting Interrupt Enable

◆ SDIO_MASK_CMDACTIE_Msk

#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)

0x00000800

◆ SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk

Command Response Received Interrupt Enable

◆ SDIO_MASK_CMDRENDIE_Msk

#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)

0x00000040

◆ SDIO_MASK_CMDSENTIE

#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk

Command Sent Interrupt Enable

◆ SDIO_MASK_CMDSENTIE_Msk

#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)

0x00000080

◆ SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk

Command TimeOut Interrupt Enable

◆ SDIO_MASK_CTIMEOUTIE_Msk

#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)

0x00000004

◆ SDIO_MASK_DATAENDIE

#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk

Data End Interrupt Enable

◆ SDIO_MASK_DATAENDIE_Msk

#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)

0x00000100

◆ SDIO_MASK_DBCKENDIE

#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk

Data Block End Interrupt Enable

◆ SDIO_MASK_DBCKENDIE_Msk

#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)

0x00000400

◆ SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk

Data CRC Fail Interrupt Enable

◆ SDIO_MASK_DCRCFAILIE_Msk

#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)

0x00000002

◆ SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk

Data TimeOut Interrupt Enable

◆ SDIO_MASK_DTIMEOUTIE_Msk

#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)

0x00000008

◆ SDIO_MASK_RXACTIE

#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk

Data receive acting interrupt enabled

◆ SDIO_MASK_RXACTIE_Msk

#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)

0x00002000

◆ SDIO_MASK_RXDAVLIE

#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk

Data available in Rx FIFO interrupt Enable

◆ SDIO_MASK_RXDAVLIE_Msk

#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)

0x00200000

◆ SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk

Rx FIFO Empty interrupt Enable

◆ SDIO_MASK_RXFIFOEIE_Msk

#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)

0x00080000

◆ SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk

Rx FIFO Full interrupt Enable

◆ SDIO_MASK_RXFIFOFIE_Msk

#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)

0x00020000

◆ SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk

Rx FIFO Half Full interrupt Enable

◆ SDIO_MASK_RXFIFOHFIE_Msk

#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)

0x00008000

◆ SDIO_MASK_RXOVERRIE

#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk

Rx FIFO OverRun Error Interrupt Enable

◆ SDIO_MASK_RXOVERRIE_Msk

#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)

0x00000020

◆ SDIO_MASK_SDIOITIE

#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk

SDIO Mode Interrupt Received interrupt Enable

◆ SDIO_MASK_SDIOITIE_Msk

#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)

0x00400000

◆ SDIO_MASK_STBITERRIE

#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk

Start Bit Error Interrupt Enable

◆ SDIO_MASK_STBITERRIE_Msk

#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)

0x00000200

◆ SDIO_MASK_TXACTIE

#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk

Data Transmit Acting Interrupt Enable

◆ SDIO_MASK_TXACTIE_Msk

#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)

0x00001000

◆ SDIO_MASK_TXDAVLIE

#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk

Data available in Tx FIFO interrupt Enable

◆ SDIO_MASK_TXDAVLIE_Msk

#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)

0x00100000

◆ SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk

Tx FIFO Empty interrupt Enable

◆ SDIO_MASK_TXFIFOEIE_Msk

#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)

0x00040000

◆ SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk

Tx FIFO Full interrupt Enable

◆ SDIO_MASK_TXFIFOFIE_Msk

#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)

0x00010000

◆ SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk

Tx FIFO Half Empty interrupt Enable

◆ SDIO_MASK_TXFIFOHEIE_Msk

#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)

0x00004000

◆ SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk

Tx FIFO UnderRun Error Interrupt Enable

◆ SDIO_MASK_TXUNDERRIE_Msk

#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)

0x00000010

◆ SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk

PWRCTRL[1:0] bits (Power supply control bits)

◆ SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)

0x01

◆ SDIO_POWER_PWRCTRL_1

#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)

0x02

◆ SDIO_POWER_PWRCTRL_Msk

#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)

0x00000003

◆ SDIO_RESP0_CARDSTATUS0

#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk

Card Status

◆ SDIO_RESP0_CARDSTATUS0_Msk

#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)

0xFFFFFFFF

◆ SDIO_RESP1_CARDSTATUS1

#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk

Card Status

◆ SDIO_RESP1_CARDSTATUS1_Msk

#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)

0xFFFFFFFF

◆ SDIO_RESP2_CARDSTATUS2

#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk

Card Status

◆ SDIO_RESP2_CARDSTATUS2_Msk

#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)

0xFFFFFFFF

◆ SDIO_RESP3_CARDSTATUS3

#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk

Card Status

◆ SDIO_RESP3_CARDSTATUS3_Msk

#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)

0xFFFFFFFF

◆ SDIO_RESP4_CARDSTATUS4

#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk

Card Status

◆ SDIO_RESP4_CARDSTATUS4_Msk

#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)

0xFFFFFFFF

◆ SDIO_RESPCMD_RESPCMD

#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk

Response command index

◆ SDIO_RESPCMD_RESPCMD_Msk

#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)

0x0000003F

◆ SDIO_STA_CCRCFAIL

#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk

Command response received (CRC check failed)

◆ SDIO_STA_CCRCFAIL_Msk

#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)

0x00000001

◆ SDIO_STA_CEATAEND

#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk

CE-ATA command completion signal received for CMD61

◆ SDIO_STA_CEATAEND_Msk

#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)

0x00800000

◆ SDIO_STA_CMDACT

#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk

Command transfer in progress

◆ SDIO_STA_CMDACT_Msk

#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)

0x00000800

◆ SDIO_STA_CMDREND

#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk

Command response received (CRC check passed)

◆ SDIO_STA_CMDREND_Msk

#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)

0x00000040

◆ SDIO_STA_CMDSENT

#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk

Command sent (no response required)

◆ SDIO_STA_CMDSENT_Msk

#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)

0x00000080

◆ SDIO_STA_CTIMEOUT

#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk

Command response timeout

◆ SDIO_STA_CTIMEOUT_Msk

#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)

0x00000004

◆ SDIO_STA_DATAEND

#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk

Data end (data counter, SDIDCOUNT, is zero)

◆ SDIO_STA_DATAEND_Msk

#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)

0x00000100

◆ SDIO_STA_DBCKEND

#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk

Data block sent/received (CRC check passed)

◆ SDIO_STA_DBCKEND_Msk

#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)

0x00000400

◆ SDIO_STA_DCRCFAIL

#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk

Data block sent/received (CRC check failed)

◆ SDIO_STA_DCRCFAIL_Msk

#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)

0x00000002

◆ SDIO_STA_DTIMEOUT

#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk

Data timeout

◆ SDIO_STA_DTIMEOUT_Msk

#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)

0x00000008

◆ SDIO_STA_RXACT

#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk

Data receive in progress

◆ SDIO_STA_RXACT_Msk

#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)

0x00002000

◆ SDIO_STA_RXDAVL

#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk

Data available in receive FIFO

◆ SDIO_STA_RXDAVL_Msk

#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)

0x00200000

◆ SDIO_STA_RXFIFOE

#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk

Receive FIFO empty

◆ SDIO_STA_RXFIFOE_Msk

#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)

0x00080000

◆ SDIO_STA_RXFIFOF

#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk

Receive FIFO full

◆ SDIO_STA_RXFIFOF_Msk

#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)

0x00020000

◆ SDIO_STA_RXFIFOHF

#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk

Receive FIFO Half Full: there are at least 8 words in the FIFO

◆ SDIO_STA_RXFIFOHF_Msk

#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)

0x00008000

◆ SDIO_STA_RXOVERR

#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk

Received FIFO overrun error

◆ SDIO_STA_RXOVERR_Msk

#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)

0x00000020

◆ SDIO_STA_SDIOIT

#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk

SDIO interrupt received

◆ SDIO_STA_SDIOIT_Msk

#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)

0x00400000

◆ SDIO_STA_STBITERR

#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk

Start bit not detected on all data signals in wide bus mode

◆ SDIO_STA_STBITERR_Msk

#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)

0x00000200

◆ SDIO_STA_TXACT

#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk

Data transmit in progress

◆ SDIO_STA_TXACT_Msk

#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)

0x00001000

◆ SDIO_STA_TXDAVL

#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk

Data available in transmit FIFO

◆ SDIO_STA_TXDAVL_Msk

#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)

0x00100000

◆ SDIO_STA_TXFIFOE

#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk

Transmit FIFO empty

◆ SDIO_STA_TXFIFOE_Msk

#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)

0x00040000

◆ SDIO_STA_TXFIFOF

#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk

Transmit FIFO full

◆ SDIO_STA_TXFIFOF_Msk

#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)

0x00010000

◆ SDIO_STA_TXFIFOHE

#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

◆ SDIO_STA_TXFIFOHE_Msk

#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)

0x00004000

◆ SDIO_STA_TXUNDERR

#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk

Transmit FIFO underrun error

◆ SDIO_STA_TXUNDERR_Msk

#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)

0x00000010

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

Bidirectional data mode enable

◆ SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

0x00008000

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

Output enable in bidirectional mode

◆ SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

0x00004000

◆ SPI_CR1_BR

#define SPI_CR1_BR SPI_CR1_BR_Msk

BR[2:0] bits (Baud Rate Control)

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

0x00000008

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

0x00000010

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

0x00000020

◆ SPI_CR1_BR_Msk

#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

0x00000038

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk

Clock Phase

◆ SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

0x00000001

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk

Clock Polarity

◆ SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

0x00000002

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

Hardware CRC calculation enable

◆ SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

0x00002000

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

Transmit CRC next

◆ SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

0x00001000

◆ SPI_CR1_DFF

#define SPI_CR1_DFF SPI_CR1_DFF_Msk

Data Frame Format

◆ SPI_CR1_DFF_Msk

#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)

0x00000800

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

Frame Format

◆ SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

0x00000080

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk

Master Selection

◆ SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

0x00000004

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

Receive only

◆ SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

0x00000400

◆ SPI_CR1_SPE

#define SPI_CR1_SPE SPI_CR1_SPE_Msk

SPI Enable

◆ SPI_CR1_SPE_Msk

#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

0x00000040

◆ SPI_CR1_SSI

#define SPI_CR1_SSI SPI_CR1_SSI_Msk

Internal slave select

◆ SPI_CR1_SSI_Msk

#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

0x00000100

◆ SPI_CR1_SSM

#define SPI_CR1_SSM SPI_CR1_SSM_Msk

Software slave management

◆ SPI_CR1_SSM_Msk

#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

0x00000200

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

Error Interrupt Enable

◆ SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

0x00000020

◆ SPI_CR2_FRF

#define SPI_CR2_FRF SPI_CR2_FRF_Msk

Frame Format

◆ SPI_CR2_FRF_Msk

#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

0x00000010

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

Rx Buffer DMA Enable

◆ SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

0x00000001

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

RX buffer Not Empty Interrupt Enable

◆ SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

0x00000040

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk

SS Output Enable

◆ SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

0x00000004

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

Tx Buffer DMA Enable

◆ SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

0x00000002

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

Tx buffer Empty Interrupt Enable

◆ SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

0x00000080

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

CRC polynomial register

◆ SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

0x0000FFFF

◆ SPI_DR_DR

#define SPI_DR_DR SPI_DR_DR_Msk

Data Register

◆ SPI_DR_DR_Msk

#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

0x0000FFFF

◆ SPI_I2S_FULLDUPLEX_SUPPORT

#define SPI_I2S_FULLDUPLEX_SUPPORT

I2S Full-Duplex support

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

Channel length (number of bits per audio channel)

◆ SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

0x00000001

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

steady state clock polarity

◆ SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

0x00000008

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

DATLEN[1:0] bits (Data length to be transferred)

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000002

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000004

◆ SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000006

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

I2SCFG[1:0] bits (I2S configuration mode)

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000100

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000200

◆ SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000300

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

I2S Enable

◆ SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

0x00000400

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

I2S mode selection

◆ SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

0x00000800

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

I2SSTD[1:0] bits (I2S standard selection)

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000010

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000020

◆ SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000030

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

PCM frame synchronization

◆ SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

0x00000080

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

I2S Linear prescaler

◆ SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

0x000000FF

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

Master Clock Output Enable

◆ SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

0x00000200

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

Odd factor for the prescaler

◆ SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

0x00000100

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

Rx CRC Register

◆ SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

0x0000FFFF

◆ SPI_SR_BSY

#define SPI_SR_BSY SPI_SR_BSY_Msk

Busy flag

◆ SPI_SR_BSY_Msk

#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

0x00000080

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

Channel side

◆ SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

0x00000004

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk

CRC Error flag

◆ SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

0x00000010

◆ SPI_SR_FRE

#define SPI_SR_FRE SPI_SR_FRE_Msk

Frame format error flag

◆ SPI_SR_FRE_Msk

#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

0x00000100

◆ SPI_SR_MODF

#define SPI_SR_MODF SPI_SR_MODF_Msk

Mode fault

◆ SPI_SR_MODF_Msk

#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

0x00000020

◆ SPI_SR_OVR

#define SPI_SR_OVR SPI_SR_OVR_Msk

Overrun flag

◆ SPI_SR_OVR_Msk

#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

0x00000040

◆ SPI_SR_RXNE

#define SPI_SR_RXNE SPI_SR_RXNE_Msk

Receive buffer Not Empty

◆ SPI_SR_RXNE_Msk

#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

0x00000001

◆ SPI_SR_TXE

#define SPI_SR_TXE SPI_SR_TXE_Msk

Transmit buffer Empty

◆ SPI_SR_TXE_Msk

#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

0x00000002

◆ SPI_SR_UDR

#define SPI_SR_UDR SPI_SR_UDR_Msk

Underrun flag

◆ SPI_SR_UDR_Msk

#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

0x00000008

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

Tx CRC Register

◆ SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

0x0000FFFF

◆ SYSCFG_CMPCR_CMP_PD

#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk

Compensation cell ready flag

◆ SYSCFG_CMPCR_CMP_PD_Msk

#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)

0x00000001

◆ SYSCFG_CMPCR_READY

#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk

Compensation cell power-down

◆ SYSCFG_CMPCR_READY_Msk

#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)

0x00000100

◆ SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

EXTI 0 configuration

◆ SYSCFG_EXTICR1_EXTI0_Msk

#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)

0x0000000F

◆ SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U

EXTI0 configuration.

PA[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U

PB[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U

PC[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U

PD[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U

PE[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U

PF[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U

PG[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U

PH[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PI

#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U

PI[0] pin

◆ SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

EXTI 1 configuration

◆ SYSCFG_EXTICR1_EXTI1_Msk

#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)

0x000000F0

◆ SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U

EXTI1 configuration.

PA[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U

PB[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U

PC[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U

PD[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U

PE[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U

PF[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U

PG[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U

PH[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PI

#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U

PI[1] pin

◆ SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

EXTI 2 configuration

◆ SYSCFG_EXTICR1_EXTI2_Msk

#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)

0x00000F00

◆ SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U

EXTI2 configuration.

PA[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U

PB[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U

PC[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U

PD[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U

PE[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U

PF[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U

PG[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U

PH[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PI

#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U

PI[2] pin

◆ SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk

EXTI 3 configuration

◆ SYSCFG_EXTICR1_EXTI3_Msk

#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)

0x0000F000

◆ SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U

EXTI3 configuration.

PA[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U

PB[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U

PC[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U

PD[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U

PE[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U

PF[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U

PG[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PH

#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U

PH[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PI

#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U

PI[3] pin

◆ SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

EXTI 4 configuration

◆ SYSCFG_EXTICR2_EXTI4_Msk

#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)

0x0000000F

◆ SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U

EXTI4 configuration.

PA[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U

PB[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U

PC[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U

PD[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U

PE[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U

PF[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U

PG[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PH

#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U

PH[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PI

#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U

PI[4] pin

◆ SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

EXTI 5 configuration

◆ SYSCFG_EXTICR2_EXTI5_Msk

#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)

0x000000F0

◆ SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U

EXTI5 configuration.

PA[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U

PB[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U

PC[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U

PD[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U

PE[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U

PF[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U

PG[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PH

#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U

PH[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PI

#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U

PI[5] pin

◆ SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

EXTI 6 configuration

◆ SYSCFG_EXTICR2_EXTI6_Msk

#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)

0x00000F00

◆ SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U

EXTI6 configuration.

PA[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U

PB[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U

PC[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U

PD[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U

PE[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U

PF[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U

PG[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PH

#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U

PH[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PI

#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U

PI[6] pin

◆ SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk

EXTI 7 configuration

◆ SYSCFG_EXTICR2_EXTI7_Msk

#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)

0x0000F000

◆ SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U

EXTI7 configuration.

PA[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U

PB[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U

PC[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U

PD[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U

PE[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U

PF[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U

PG[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PH

#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U

PH[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PI

#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U

PI[7] pin

◆ SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

EXTI 10 configuration

◆ SYSCFG_EXTICR3_EXTI10_Msk

#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)

0x00000F00

◆ SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U

EXTI10 configuration.

PA[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U

PB[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U

PC[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U

PD[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U

PE[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U

PF[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U

PG[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PH

#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U

PH[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PI

#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U

PI[10] pin

◆ SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk

EXTI 11 configuration

◆ SYSCFG_EXTICR3_EXTI11_Msk

#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)

0x0000F000

◆ SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U

EXTI11 configuration.

PA[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U

PB[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U

PC[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U

PD[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U

PE[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U

PF[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U

PG[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PH

#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U

PH[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PI

#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U

PI[11] pin

◆ SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

EXTI 8 configuration

◆ SYSCFG_EXTICR3_EXTI8_Msk

#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)

0x0000000F

◆ SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U

EXTI8 configuration.

PA[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U

PB[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U

PC[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U

PD[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U

PE[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U

PF[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U

PG[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PH

#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U

PH[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PI

#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U

PI[8] pin

◆ SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

EXTI 9 configuration

◆ SYSCFG_EXTICR3_EXTI9_Msk

#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)

0x000000F0

◆ SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U

EXTI9 configuration.

PA[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U

PB[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U

PC[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U

PD[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U

PE[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U

PF[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U

PG[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PH

#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U

PH[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PI

#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U

PI[9] pin

◆ SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

EXTI 12 configuration

◆ SYSCFG_EXTICR4_EXTI12_Msk

#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)

0x0000000F

◆ SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U

EXTI12 configuration.

PA[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U

PB[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U

PC[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U

PD[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U

PE[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U

PF[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U

PG[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PH

#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U

PH[12] pin

◆ SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

EXTI 13 configuration

◆ SYSCFG_EXTICR4_EXTI13_Msk

#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)

0x000000F0

◆ SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U

EXTI13 configuration.

PA[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U

PB[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U

PC[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U

PD[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U

PE[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U

PF[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U

PG[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PH

#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U

PH[13] pin

◆ SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

EXTI 14 configuration

◆ SYSCFG_EXTICR4_EXTI14_Msk

#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)

0x00000F00

◆ SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U

EXTI14 configuration.

PA[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U

PB[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U

PC[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U

PD[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U

PE[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U

PF[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U

PG[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PH

#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U

PH[14] pin

◆ SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk

EXTI 15 configuration

◆ SYSCFG_EXTICR4_EXTI15_Msk

#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)

0x0000F000

◆ SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U

EXTI15 configuration.

PA[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U

PB[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U

PC[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U

PD[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U

PE[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U

PF[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U

PG[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PH

#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U

PH[15] pin

◆ SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk

SYSCFG_Memory Remap Config

◆ SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000001

◆ SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000002

◆ SYSCFG_MEMRMP_MEM_MODE_Msk

#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000003

◆ SYSCFG_PMC_MII_RMII_SEL

#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk

Ethernet PHY interface selection

◆ SYSCFG_PMC_MII_RMII_SEL_Msk

#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)

0x00800000

◆ TIM_ARR_ARR

#define TIM_ARR_ARR TIM_ARR_ARR_Msk

actual auto-reload Value

◆ TIM_ARR_ARR_Msk

#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

0xFFFFFFFF

◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk

Automatic Output enable

◆ TIM_BDTR_AOE_Msk

#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

0x00004000

◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk

Break enable

◆ TIM_BDTR_BKE_Msk

#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

0x00001000

◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk

Break Polarity

◆ TIM_BDTR_BKP_Msk

#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

0x00002000

◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk

DTG[0:7] bits (Dead-Time Generator set-up)

◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

0x0001

◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

0x0002

◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

0x0004

◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

0x0008

◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

0x0010

◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

0x0020

◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

0x0040

◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

0x0080

◆ TIM_BDTR_DTG_Msk

#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

0x000000FF

◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

LOCK[1:0] bits (Lock Configuration)

◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

0x0100

◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

0x0200

◆ TIM_BDTR_LOCK_Msk

#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

0x00000300

◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk

Main Output enable

◆ TIM_BDTR_MOE_Msk

#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

0x00008000

◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

Off-State Selection for Idle mode

◆ TIM_BDTR_OSSI_Msk

#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

0x00000400

◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

Off-State Selection for Run mode

◆ TIM_BDTR_OSSR_Msk

#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

0x00000800

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk

Capture/Compare 1 output enable

◆ TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

0x00000001

◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

Capture/Compare 1 Complementary output enable

◆ TIM_CCER_CC1NE_Msk

#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

0x00000004

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

Capture/Compare 1 Complementary output Polarity

◆ TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

0x00000008

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk

Capture/Compare 1 output Polarity

◆ TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

0x00000002

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk

Capture/Compare 2 output enable

◆ TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

0x00000010

◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

Capture/Compare 2 Complementary output enable

◆ TIM_CCER_CC2NE_Msk

#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

0x00000040

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

Capture/Compare 2 Complementary output Polarity

◆ TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

0x00000080

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk

Capture/Compare 2 output Polarity

◆ TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

0x00000020

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk

Capture/Compare 3 output enable

◆ TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

0x00000100

◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

Capture/Compare 3 Complementary output enable

◆ TIM_CCER_CC3NE_Msk

#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

0x00000400

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

Capture/Compare 3 Complementary output Polarity

◆ TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

0x00000800

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk

Capture/Compare 3 output Polarity

◆ TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

0x00000200

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk

Capture/Compare 4 output enable

◆ TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

0x00001000

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

Capture/Compare 4 Complementary output Polarity

◆ TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

0x00008000

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk

Capture/Compare 4 output Polarity

◆ TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

0x00002000

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

CC1S[1:0] bits (Capture/Compare 1 Selection)

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

0x0001

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

0x0002

◆ TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

0x00000003

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

CC2S[1:0] bits (Capture/Compare 2 Selection)

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

0x0100

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

0x0200

◆ TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

0x00000300

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

IC1F[3:0] bits (Input Capture 1 Filter)

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

0x0010

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

0x0020

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

0x0040

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

0x0080

◆ TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

0x000000F0

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

0x0004

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

0x0008

◆ TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

0x0000000C

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

IC2F[3:0] bits (Input Capture 2 Filter)

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

0x1000

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

0x2000

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

0x4000

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

0x8000

◆ TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

0x0000F000

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

0x0400

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

0x0800

◆ TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

0x00000C00

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

Output Compare 1Clear Enable

◆ TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

0x00000080

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

Output Compare 1 Fast enable

◆ TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

0x00000004

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

OC1M[2:0] bits (Output Compare 1 Mode)

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)

0x0010

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)

0x0020

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)

0x0040

◆ TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)

0x00000070

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

Output Compare 1 Preload enable

◆ TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

0x00000008

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

Output Compare 2 Clear Enable

◆ TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

0x00008000

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

Output Compare 2 Fast enable

◆ TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

0x00000400

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

OC2M[2:0] bits (Output Compare 2 Mode)

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)

0x1000

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)

0x2000

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)

0x4000

◆ TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)

0x00007000

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

Output Compare 2 Preload enable

◆ TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

0x00000800

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

CC3S[1:0] bits (Capture/Compare 3 Selection)

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

0x0001

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

0x0002

◆ TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

0x00000003

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

CC4S[1:0] bits (Capture/Compare 4 Selection)

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

0x0100

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

0x0200

◆ TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

0x00000300

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

IC3F[3:0] bits (Input Capture 3 Filter)

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

0x0010

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

0x0020

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

0x0040

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

0x0080

◆ TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

0x000000F0

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

0x0004

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

0x0008

◆ TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

0x0000000C

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

IC4F[3:0] bits (Input Capture 4 Filter)

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

0x1000

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

0x2000

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

0x4000

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

0x8000

◆ TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

0x0000F000

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

0x0400

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

0x0800

◆ TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

0x00000C00

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

Output Compare 3 Clear Enable

◆ TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

0x00000080

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

Output Compare 3 Fast enable

◆ TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

0x00000004

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

OC3M[2:0] bits (Output Compare 3 Mode)

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)

0x0010

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)

0x0020

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)

0x0040

◆ TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)

0x00000070

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

Output Compare 3 Preload enable

◆ TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

0x00000008

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

Output Compare 4 Clear Enable

◆ TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

0x00008000

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

Output Compare 4 Fast enable

◆ TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

0x00000400

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

OC4M[2:0] bits (Output Compare 4 Mode)

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)

0x1000

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)

0x2000

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)

0x4000

◆ TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)

0x00007000

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

Output Compare 4 Preload enable

◆ TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

0x00000800

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

Capture/Compare 1 Value

◆ TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

0x0000FFFF

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

Capture/Compare 2 Value

◆ TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

0x0000FFFF

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

Capture/Compare 3 Value

◆ TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

0x0000FFFF

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

Capture/Compare 4 Value

◆ TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

0x0000FFFF

◆ TIM_CNT_CNT

#define TIM_CNT_CNT TIM_CNT_CNT_Msk

Counter Value

◆ TIM_CNT_CNT_Msk

#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

0xFFFFFFFF

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk

Auto-reload preload enable

◆ TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

0x00000080

◆ TIM_CR1_CEN

#define TIM_CR1_CEN TIM_CR1_CEN_Msk

Counter enable

◆ TIM_CR1_CEN_Msk

#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

0x00000001

◆ TIM_CR1_CKD

#define TIM_CR1_CKD TIM_CR1_CKD_Msk

CKD[1:0] bits (clock division)

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

0x0100

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

0x0200

◆ TIM_CR1_CKD_Msk

#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

0x00000300

◆ TIM_CR1_CMS

#define TIM_CR1_CMS TIM_CR1_CMS_Msk

CMS[1:0] bits (Center-aligned mode selection)

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

0x0020

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

0x0040

◆ TIM_CR1_CMS_Msk

#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

0x00000060

◆ TIM_CR1_DIR

#define TIM_CR1_DIR TIM_CR1_DIR_Msk

Direction

◆ TIM_CR1_DIR_Msk

#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

0x00000010

◆ TIM_CR1_OPM

#define TIM_CR1_OPM TIM_CR1_OPM_Msk

One pulse mode

◆ TIM_CR1_OPM_Msk

#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

0x00000008

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk

Update disable

◆ TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

0x00000002

◆ TIM_CR1_URS

#define TIM_CR1_URS TIM_CR1_URS_Msk

Update request source

◆ TIM_CR1_URS_Msk

#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

0x00000004

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk

Capture/Compare DMA Selection

◆ TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

0x00000008

◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk

Capture/Compare Preloaded Control

◆ TIM_CR2_CCPC_Msk

#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

0x00000001

◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk

Capture/Compare Control Update Selection

◆ TIM_CR2_CCUS_Msk

#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

0x00000004

◆ TIM_CR2_MMS

#define TIM_CR2_MMS TIM_CR2_MMS_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

0x0010

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

0x0020

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

0x0040

◆ TIM_CR2_MMS_Msk

#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

0x00000070

◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

Output Idle state 1 (OC1 output)

◆ TIM_CR2_OIS1_Msk

#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

0x00000100

◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

Output Idle state 1 (OC1N output)

◆ TIM_CR2_OIS1N_Msk

#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

0x00000200

◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

Output Idle state 2 (OC2 output)

◆ TIM_CR2_OIS2_Msk

#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

0x00000400

◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

Output Idle state 2 (OC2N output)

◆ TIM_CR2_OIS2N_Msk

#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

0x00000800

◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

Output Idle state 3 (OC3 output)

◆ TIM_CR2_OIS3_Msk

#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

0x00001000

◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

Output Idle state 3 (OC3N output)

◆ TIM_CR2_OIS3N_Msk

#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

0x00002000

◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

Output Idle state 4 (OC4 output)

◆ TIM_CR2_OIS4_Msk

#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

0x00004000

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk

TI1 Selection

◆ TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

0x00000080

◆ TIM_DCR_DBA

#define TIM_DCR_DBA TIM_DCR_DBA_Msk

DBA[4:0] bits (DMA Base Address)

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

0x0001

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

0x0002

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

0x0004

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

0x0008

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

0x0010

◆ TIM_DCR_DBA_Msk

#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

0x0000001F

◆ TIM_DCR_DBL

#define TIM_DCR_DBL TIM_DCR_DBL_Msk

DBL[4:0] bits (DMA Burst Length)

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

0x0100

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

0x0200

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

0x0400

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

0x0800

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

0x1000

◆ TIM_DCR_DBL_Msk

#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

0x00001F00

◆ TIM_DIER_BIE

#define TIM_DIER_BIE TIM_DIER_BIE_Msk

Break interrupt enable

◆ TIM_DIER_BIE_Msk

#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

0x00000080

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

Capture/Compare 1 DMA request enable

◆ TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

0x00000200

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

Capture/Compare 1 interrupt enable

◆ TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

0x00000002

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

Capture/Compare 2 DMA request enable

◆ TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

0x00000400

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

Capture/Compare 2 interrupt enable

◆ TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

0x00000004

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

Capture/Compare 3 DMA request enable

◆ TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

0x00000800

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

Capture/Compare 3 interrupt enable

◆ TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

0x00000008

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

Capture/Compare 4 DMA request enable

◆ TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

0x00001000

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

Capture/Compare 4 interrupt enable

◆ TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

0x00000010

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk

COM DMA request enable

◆ TIM_DIER_COMDE_Msk

#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

0x00002000

◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk

COM interrupt enable

◆ TIM_DIER_COMIE_Msk

#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

0x00000020

◆ TIM_DIER_TDE

#define TIM_DIER_TDE TIM_DIER_TDE_Msk

Trigger DMA request enable

◆ TIM_DIER_TDE_Msk

#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

0x00004000

◆ TIM_DIER_TIE

#define TIM_DIER_TIE TIM_DIER_TIE_Msk

Trigger interrupt enable

◆ TIM_DIER_TIE_Msk

#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

0x00000040

◆ TIM_DIER_UDE

#define TIM_DIER_UDE TIM_DIER_UDE_Msk

Update DMA request enable

◆ TIM_DIER_UDE_Msk

#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

0x00000100

◆ TIM_DIER_UIE

#define TIM_DIER_UIE TIM_DIER_UIE_Msk

Update interrupt enable

◆ TIM_DIER_UIE_Msk

#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

0x00000001

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

DMA register for burst accesses

◆ TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

0x0000FFFF

◆ TIM_EGR_BG

#define TIM_EGR_BG TIM_EGR_BG_Msk

Break Generation

◆ TIM_EGR_BG_Msk

#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

0x00000080

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk

Capture/Compare 1 Generation

◆ TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

0x00000002

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk

Capture/Compare 2 Generation

◆ TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

0x00000004

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk

Capture/Compare 3 Generation

◆ TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

0x00000008

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk

Capture/Compare 4 Generation

◆ TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

0x00000010

◆ TIM_EGR_COMG

#define TIM_EGR_COMG TIM_EGR_COMG_Msk

Capture/Compare Control Update Generation

◆ TIM_EGR_COMG_Msk

#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

0x00000020

◆ TIM_EGR_TG

#define TIM_EGR_TG TIM_EGR_TG_Msk

Trigger Generation

◆ TIM_EGR_TG_Msk

#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

0x00000040

◆ TIM_EGR_UG

#define TIM_EGR_UG TIM_EGR_UG_Msk

Update Generation

◆ TIM_EGR_UG_Msk

#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

0x00000001

◆ TIM_OR_ITR1_RMP

#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

◆ TIM_OR_ITR1_RMP_0

#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)

0x0400

◆ TIM_OR_ITR1_RMP_1

#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)

0x0800

◆ TIM_OR_ITR1_RMP_Msk

#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)

0x00000C00

◆ TIM_OR_TI1_RMP

#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk

TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap)

◆ TIM_OR_TI1_RMP_0

#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)

0x00000001

◆ TIM_OR_TI1_RMP_1

#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)

0x00000002

◆ TIM_OR_TI1_RMP_Msk

#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)

0x00000003

◆ TIM_OR_TI4_RMP

#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

◆ TIM_OR_TI4_RMP_0

#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)

0x0040

◆ TIM_OR_TI4_RMP_1

#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)

0x0080

◆ TIM_OR_TI4_RMP_Msk

#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)

0x000000C0

◆ TIM_PSC_PSC

#define TIM_PSC_PSC TIM_PSC_PSC_Msk

Prescaler Value

◆ TIM_PSC_PSC_Msk

#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

0x0000FFFF

◆ TIM_RCR_REP

#define TIM_RCR_REP TIM_RCR_REP_Msk

Repetition Counter Value

◆ TIM_RCR_REP_Msk

#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)

0x000000FF

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk

External clock enable

◆ TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

0x00004000

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk

ETF[3:0] bits (External trigger filter)

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

0x0100

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

0x0200

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

0x0400

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

0x0800

◆ TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

0x00000F00

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk

External trigger polarity

◆ TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

0x00008000

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

ETPS[1:0] bits (External trigger prescaler)

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

0x1000

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

0x2000

◆ TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

0x00003000

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk

Master/slave mode

◆ TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

0x00000080

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk

SMS[2:0] bits (Slave mode selection)

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)

0x0001

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)

0x0002

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)

0x0004

◆ TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)

0x00000007

◆ TIM_SMCR_TS

#define TIM_SMCR_TS TIM_SMCR_TS_Msk

TS[2:0] bits (Trigger selection)

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)

0x0010

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)

0x0020

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)

0x0040

◆ TIM_SMCR_TS_Msk

#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)

0x00000070

◆ TIM_SR_BIF

#define TIM_SR_BIF TIM_SR_BIF_Msk

Break interrupt Flag

◆ TIM_SR_BIF_Msk

#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

0x00000080

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk

Capture/Compare 1 interrupt Flag

◆ TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

0x00000002

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk

Capture/Compare 1 Overcapture Flag

◆ TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

0x00000200

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk

Capture/Compare 2 interrupt Flag

◆ TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

0x00000004

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk

Capture/Compare 2 Overcapture Flag

◆ TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

0x00000400

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk

Capture/Compare 3 interrupt Flag

◆ TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

0x00000008

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk

Capture/Compare 3 Overcapture Flag

◆ TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

0x00000800

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk

Capture/Compare 4 interrupt Flag

◆ TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

0x00000010

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk

Capture/Compare 4 Overcapture Flag

◆ TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

0x00001000

◆ TIM_SR_COMIF

#define TIM_SR_COMIF TIM_SR_COMIF_Msk

COM interrupt Flag

◆ TIM_SR_COMIF_Msk

#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

0x00000020

◆ TIM_SR_TIF

#define TIM_SR_TIF TIM_SR_TIF_Msk

Trigger interrupt Flag

◆ TIM_SR_TIF_Msk

#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

0x00000040

◆ TIM_SR_UIF

#define TIM_SR_UIF TIM_SR_UIF_Msk

Update interrupt Flag

◆ TIM_SR_UIF_Msk

#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

0x00000001

◆ USART_BRR_DIV_Fraction

#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk

Fraction of USARTDIV

◆ USART_BRR_DIV_Fraction_Msk

#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)

0x0000000F

◆ USART_BRR_DIV_Mantissa

#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk

Mantissa of USARTDIV

◆ USART_BRR_DIV_Mantissa_Msk

#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)

0x0000FFF0

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

IDLE Interrupt Enable

◆ USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

0x00000010

◆ USART_CR1_M

#define USART_CR1_M USART_CR1_M_Msk

Word length

◆ USART_CR1_M_Msk

#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)

0x00001000

◆ USART_CR1_OVER8

#define USART_CR1_OVER8 USART_CR1_OVER8_Msk

USART Oversampling by 8 enable

◆ USART_CR1_OVER8_Msk

#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

0x00008000

◆ USART_CR1_PCE

#define USART_CR1_PCE USART_CR1_PCE_Msk

Parity Control Enable

◆ USART_CR1_PCE_Msk

#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

0x00000400

◆ USART_CR1_PEIE

#define USART_CR1_PEIE USART_CR1_PEIE_Msk

PE Interrupt Enable

◆ USART_CR1_PEIE_Msk

#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

0x00000100

◆ USART_CR1_PS

#define USART_CR1_PS USART_CR1_PS_Msk

Parity Selection

◆ USART_CR1_PS_Msk

#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

0x00000200

◆ USART_CR1_RE

#define USART_CR1_RE USART_CR1_RE_Msk

Receiver Enable

◆ USART_CR1_RE_Msk

#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

0x00000004

◆ USART_CR1_RWU

#define USART_CR1_RWU USART_CR1_RWU_Msk

Receiver wakeup

◆ USART_CR1_RWU_Msk

#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)

0x00000002

◆ USART_CR1_RXNEIE

#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

RXNE Interrupt Enable

◆ USART_CR1_RXNEIE_Msk

#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

0x00000020

◆ USART_CR1_SBK

#define USART_CR1_SBK USART_CR1_SBK_Msk

Send Break

◆ USART_CR1_SBK_Msk

#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)

0x00000001

◆ USART_CR1_TCIE

#define USART_CR1_TCIE USART_CR1_TCIE_Msk

Transmission Complete Interrupt Enable

◆ USART_CR1_TCIE_Msk

#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

0x00000040

◆ USART_CR1_TE

#define USART_CR1_TE USART_CR1_TE_Msk

Transmitter Enable

◆ USART_CR1_TE_Msk

#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

0x00000008

◆ USART_CR1_TXEIE

#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk

TXE Interrupt Enable

◆ USART_CR1_TXEIE_Msk

#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

0x00000080

◆ USART_CR1_UE

#define USART_CR1_UE USART_CR1_UE_Msk

USART Enable

◆ USART_CR1_UE_Msk

#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

0x00002000

◆ USART_CR1_WAKE

#define USART_CR1_WAKE USART_CR1_WAKE_Msk

Wakeup method

◆ USART_CR1_WAKE_Msk

#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

0x00000800

◆ USART_CR2_ADD

#define USART_CR2_ADD USART_CR2_ADD_Msk

Address of the USART node

◆ USART_CR2_ADD_Msk

#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)

0x0000000F

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk

Clock Enable

◆ USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

0x00000800

◆ USART_CR2_CPHA

#define USART_CR2_CPHA USART_CR2_CPHA_Msk

Clock Phase

◆ USART_CR2_CPHA_Msk

#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

0x00000200

◆ USART_CR2_CPOL

#define USART_CR2_CPOL USART_CR2_CPOL_Msk

Clock Polarity

◆ USART_CR2_CPOL_Msk

#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

0x00000400

◆ USART_CR2_LBCL

#define USART_CR2_LBCL USART_CR2_LBCL_Msk

Last Bit Clock pulse

◆ USART_CR2_LBCL_Msk

#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

0x00000100

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk

LIN Break Detection Interrupt Enable

◆ USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

0x00000040

◆ USART_CR2_LBDL

#define USART_CR2_LBDL USART_CR2_LBDL_Msk

LIN Break Detection Length

◆ USART_CR2_LBDL_Msk

#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

0x00000020

◆ USART_CR2_LINEN

#define USART_CR2_LINEN USART_CR2_LINEN_Msk

LIN mode enable

◆ USART_CR2_LINEN_Msk

#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

0x00004000

◆ USART_CR2_STOP

#define USART_CR2_STOP USART_CR2_STOP_Msk

STOP[1:0] bits (STOP bits)

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

0x1000

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

0x2000

◆ USART_CR2_STOP_Msk

#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

0x00003000

◆ USART_CR3_CTSE

#define USART_CR3_CTSE USART_CR3_CTSE_Msk

CTS Enable

◆ USART_CR3_CTSE_Msk

#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

0x00000200

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk

CTS Interrupt Enable

◆ USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

0x00000400

◆ USART_CR3_DMAR

#define USART_CR3_DMAR USART_CR3_DMAR_Msk

DMA Enable Receiver

◆ USART_CR3_DMAR_Msk

#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

0x00000040

◆ USART_CR3_DMAT

#define USART_CR3_DMAT USART_CR3_DMAT_Msk

DMA Enable Transmitter

◆ USART_CR3_DMAT_Msk

#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

0x00000080

◆ USART_CR3_EIE

#define USART_CR3_EIE USART_CR3_EIE_Msk

Error Interrupt Enable

◆ USART_CR3_EIE_Msk

#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

0x00000001

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk

Half-Duplex Selection

◆ USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

0x00000008

◆ USART_CR3_IREN

#define USART_CR3_IREN USART_CR3_IREN_Msk

IrDA mode Enable

◆ USART_CR3_IREN_Msk

#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

0x00000002

◆ USART_CR3_IRLP

#define USART_CR3_IRLP USART_CR3_IRLP_Msk

IrDA Low-Power

◆ USART_CR3_IRLP_Msk

#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

0x00000004

◆ USART_CR3_NACK

#define USART_CR3_NACK USART_CR3_NACK_Msk

Smartcard NACK enable

◆ USART_CR3_NACK_Msk

#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

0x00000010

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

USART One bit method enable

◆ USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

0x00000800

◆ USART_CR3_RTSE

#define USART_CR3_RTSE USART_CR3_RTSE_Msk

RTS Enable

◆ USART_CR3_RTSE_Msk

#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

0x00000100

◆ USART_CR3_SCEN

#define USART_CR3_SCEN USART_CR3_SCEN_Msk

Smartcard mode enable

◆ USART_CR3_SCEN_Msk

#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

0x00000020

◆ USART_DR_DR

#define USART_DR_DR USART_DR_DR_Msk

Data value

◆ USART_DR_DR_Msk

#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)

0x000001FF

◆ USART_GTPR_GT

#define USART_GTPR_GT USART_GTPR_GT_Msk

Guard time value

◆ USART_GTPR_GT_Msk

#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

0x0000FF00

◆ USART_GTPR_PSC

#define USART_GTPR_PSC USART_GTPR_PSC_Msk

PSC[7:0] bits (Prescaler value)

◆ USART_GTPR_PSC_0

#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)

0x0001

◆ USART_GTPR_PSC_1

#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)

0x0002

◆ USART_GTPR_PSC_2

#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)

0x0004

◆ USART_GTPR_PSC_3

#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)

0x0008

◆ USART_GTPR_PSC_4

#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)

0x0010

◆ USART_GTPR_PSC_5

#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)

0x0020

◆ USART_GTPR_PSC_6

#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)

0x0040

◆ USART_GTPR_PSC_7

#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)

0x0080

◆ USART_GTPR_PSC_Msk

#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

0x000000FF

◆ USART_SR_CTS

#define USART_SR_CTS USART_SR_CTS_Msk

CTS Flag

◆ USART_SR_CTS_Msk

#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)

0x00000200

◆ USART_SR_FE

#define USART_SR_FE USART_SR_FE_Msk

Framing Error

◆ USART_SR_FE_Msk

#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)

0x00000002

◆ USART_SR_IDLE

#define USART_SR_IDLE USART_SR_IDLE_Msk

IDLE line detected

◆ USART_SR_IDLE_Msk

#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)

0x00000010

◆ USART_SR_LBD

#define USART_SR_LBD USART_SR_LBD_Msk

LIN Break Detection Flag

◆ USART_SR_LBD_Msk

#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)

0x00000100

◆ USART_SR_NE

#define USART_SR_NE USART_SR_NE_Msk

Noise Error Flag

◆ USART_SR_NE_Msk

#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)

0x00000004

◆ USART_SR_ORE

#define USART_SR_ORE USART_SR_ORE_Msk

OverRun Error

◆ USART_SR_ORE_Msk

#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)

0x00000008

◆ USART_SR_PE

#define USART_SR_PE USART_SR_PE_Msk

Parity Error

◆ USART_SR_PE_Msk

#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)

0x00000001

◆ USART_SR_RXNE

#define USART_SR_RXNE USART_SR_RXNE_Msk

Read Data Register Not Empty

◆ USART_SR_RXNE_Msk

#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)

0x00000020

◆ USART_SR_TC

#define USART_SR_TC USART_SR_TC_Msk

Transmission Complete

◆ USART_SR_TC_Msk

#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)

0x00000040

◆ USART_SR_TXE

#define USART_SR_TXE USART_SR_TXE_Msk

Transmit Data Register Empty

◆ USART_SR_TXE_Msk

#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)

0x00000080

◆ USB_OTG_BCNT

#define USB_OTG_BCNT USB_OTG_BCNT_Msk

Byte count

◆ USB_OTG_BCNT_Msk

#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)

0x00007FF0

◆ USB_OTG_CHNUM

#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk

Channel number

◆ USB_OTG_CHNUM_0

#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)

0x00000001

◆ USB_OTG_CHNUM_1

#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)

0x00000002

◆ USB_OTG_CHNUM_2

#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)

0x00000004

◆ USB_OTG_CHNUM_3

#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)

0x00000008

◆ USB_OTG_CHNUM_Msk

#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)

0x0000000F

◆ USB_OTG_CID_PRODUCT_ID

#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk

Product ID field

◆ USB_OTG_CID_PRODUCT_ID_Msk

#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)

0xFFFFFFFF

◆ USB_OTG_DAINT_IEPINT

#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk

IN endpoint interrupt bits

◆ USB_OTG_DAINT_IEPINT_Msk

#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)

0x0000FFFF

◆ USB_OTG_DAINT_OEPINT

#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk

OUT endpoint interrupt bits

◆ USB_OTG_DAINT_OEPINT_Msk

#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)

0xFFFF0000

◆ USB_OTG_DAINTMSK_IEPM

#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk

IN EP interrupt mask bits

◆ USB_OTG_DAINTMSK_IEPM_Msk

#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)

0x0000FFFF

◆ USB_OTG_DAINTMSK_OEPM

#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk

OUT EP interrupt mask bits

◆ USB_OTG_DAINTMSK_OEPM_Msk

#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)

0xFFFF0000

◆ USB_OTG_DCFG_DAD

#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk

Device address

◆ USB_OTG_DCFG_DAD_0

#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)

0x00000010

◆ USB_OTG_DCFG_DAD_1

#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)

0x00000020

◆ USB_OTG_DCFG_DAD_2

#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)

0x00000040

◆ USB_OTG_DCFG_DAD_3

#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)

0x00000080

◆ USB_OTG_DCFG_DAD_4

#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)

0x00000100

◆ USB_OTG_DCFG_DAD_5

#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)

0x00000200

◆ USB_OTG_DCFG_DAD_6

#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)

0x00000400

◆ USB_OTG_DCFG_DAD_Msk

#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)

0x000007F0

◆ USB_OTG_DCFG_DSPD

#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk

Device speed

◆ USB_OTG_DCFG_DSPD_0

#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)

0x00000001

◆ USB_OTG_DCFG_DSPD_1

#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)

0x00000002

◆ USB_OTG_DCFG_DSPD_Msk

#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)

0x00000003

◆ USB_OTG_DCFG_ERRATIM

#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk

Erratic error interrupt mask

◆ USB_OTG_DCFG_ERRATIM_Msk

#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)

0x00008000

◆ USB_OTG_DCFG_NZLSOHSK

#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk

Nonzero-length status OUT handshake

◆ USB_OTG_DCFG_NZLSOHSK_Msk

#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)

0x00000004

◆ USB_OTG_DCFG_PERSCHIVL

#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk

Periodic scheduling interval

◆ USB_OTG_DCFG_PERSCHIVL_0

#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)

0x01000000

◆ USB_OTG_DCFG_PERSCHIVL_1

#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)

0x02000000

◆ USB_OTG_DCFG_PERSCHIVL_Msk

#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)

0x03000000

◆ USB_OTG_DCFG_PFIVL

#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk

Periodic (micro)frame interval

◆ USB_OTG_DCFG_PFIVL_0

#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)

0x00000800

◆ USB_OTG_DCFG_PFIVL_1

#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)

0x00001000

◆ USB_OTG_DCFG_PFIVL_Msk

#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)

0x00001800

◆ USB_OTG_DCFG_XCVRDLY

#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk

Transceiver delay

◆ USB_OTG_DCFG_XCVRDLY_Msk

#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)

0x00004000

◆ USB_OTG_DCTL_CGINAK

#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk

Clear global IN NAK

◆ USB_OTG_DCTL_CGINAK_Msk

#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)

0x00000100

◆ USB_OTG_DCTL_CGONAK

#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk

Clear global OUT NAK

◆ USB_OTG_DCTL_CGONAK_Msk

#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)

0x00000400

◆ USB_OTG_DCTL_GINSTS

#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk

Global IN NAK status

◆ USB_OTG_DCTL_GINSTS_Msk

#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)

0x00000004

◆ USB_OTG_DCTL_GONSTS

#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk

Global OUT NAK status

◆ USB_OTG_DCTL_GONSTS_Msk

#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)

0x00000008

◆ USB_OTG_DCTL_POPRGDNE

#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk

Power-on programming done

◆ USB_OTG_DCTL_POPRGDNE_Msk

#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)

0x00000800

◆ USB_OTG_DCTL_RWUSIG

#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk

Remote wakeup signaling

◆ USB_OTG_DCTL_RWUSIG_Msk

#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)

0x00000001

◆ USB_OTG_DCTL_SDIS

#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk

Soft disconnect

◆ USB_OTG_DCTL_SDIS_Msk

#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)

0x00000002

◆ USB_OTG_DCTL_SGINAK

#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk

Set global IN NAK

◆ USB_OTG_DCTL_SGINAK_Msk

#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)

0x00000080

◆ USB_OTG_DCTL_SGONAK

#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk

Set global OUT NAK

◆ USB_OTG_DCTL_SGONAK_Msk

#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)

0x00000200

◆ USB_OTG_DCTL_TCTL

#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk

Test control

◆ USB_OTG_DCTL_TCTL_0

#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)

0x00000010

◆ USB_OTG_DCTL_TCTL_1

#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)

0x00000020

◆ USB_OTG_DCTL_TCTL_2

#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)

0x00000040

◆ USB_OTG_DCTL_TCTL_Msk

#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)

0x00000070

◆ USB_OTG_DEACHINT_IEP1INT

#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk

IN endpoint 1interrupt bit

◆ USB_OTG_DEACHINT_IEP1INT_Msk

#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)

0x00000002

◆ USB_OTG_DEACHINT_OEP1INT

#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk

OUT endpoint 1 interrupt bit

◆ USB_OTG_DEACHINT_OEP1INT_Msk

#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)

0x00020000

◆ USB_OTG_DEACHINTMSK_IEP1INTM

#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk

IN Endpoint 1 interrupt mask bit

◆ USB_OTG_DEACHINTMSK_IEP1INTM_Msk

#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)

0x00000002

◆ USB_OTG_DEACHINTMSK_OEP1INTM

#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk

OUT Endpoint 1 interrupt mask bit

◆ USB_OTG_DEACHINTMSK_OEP1INTM_Msk

#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)

0x00020000

◆ USB_OTG_DIEPCTL_CNAK

#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk

Clear NAK

◆ USB_OTG_DIEPCTL_CNAK_Msk

#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)

0x04000000

◆ USB_OTG_DIEPCTL_EONUM_DPID

#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk

Even/odd frame

◆ USB_OTG_DIEPCTL_EONUM_DPID_Msk

#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)

0x00010000

◆ USB_OTG_DIEPCTL_EPDIS

#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk

Endpoint disable

◆ USB_OTG_DIEPCTL_EPDIS_Msk

#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)

0x40000000

◆ USB_OTG_DIEPCTL_EPENA

#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk

Endpoint enable

◆ USB_OTG_DIEPCTL_EPENA_Msk

#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)

0x80000000

◆ USB_OTG_DIEPCTL_EPTYP

#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk

Endpoint type

◆ USB_OTG_DIEPCTL_EPTYP_0

#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)

0x00040000

◆ USB_OTG_DIEPCTL_EPTYP_1

#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)

0x00080000

◆ USB_OTG_DIEPCTL_EPTYP_Msk

#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)

0x000C0000

◆ USB_OTG_DIEPCTL_MPSIZ

#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk

Maximum packet size

◆ USB_OTG_DIEPCTL_MPSIZ_Msk

#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)

0x000007FF

◆ USB_OTG_DIEPCTL_NAKSTS

#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk

NAK status

◆ USB_OTG_DIEPCTL_NAKSTS_Msk

#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)

0x00020000

◆ USB_OTG_DIEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk

Set DATA0 PID

◆ USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)

0x10000000

◆ USB_OTG_DIEPCTL_SNAK

#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk

Set NAK

◆ USB_OTG_DIEPCTL_SNAK_Msk

#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)

0x08000000

◆ USB_OTG_DIEPCTL_SODDFRM

#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk

Set odd frame

◆ USB_OTG_DIEPCTL_SODDFRM_Msk

#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)

0x20000000

◆ USB_OTG_DIEPCTL_STALL

#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk

STALL handshake

◆ USB_OTG_DIEPCTL_STALL_Msk

#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)

0x00200000

◆ USB_OTG_DIEPCTL_TXFNUM

#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk

TxFIFO number

◆ USB_OTG_DIEPCTL_TXFNUM_0

#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

0x00400000

◆ USB_OTG_DIEPCTL_TXFNUM_1

#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

0x00800000

◆ USB_OTG_DIEPCTL_TXFNUM_2

#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

0x01000000

◆ USB_OTG_DIEPCTL_TXFNUM_3

#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

0x02000000

◆ USB_OTG_DIEPCTL_TXFNUM_Msk

#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)

0x03C00000

◆ USB_OTG_DIEPCTL_USBAEP

#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk

USB active endpoint

◆ USB_OTG_DIEPCTL_USBAEP_Msk

#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)

0x00008000

◆ USB_OTG_DIEPDMA_DMAADDR

#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk

DMA address

◆ USB_OTG_DIEPDMA_DMAADDR_Msk

#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)

0xFFFFFFFF

◆ USB_OTG_DIEPEACHMSK1_BIM

#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk

BNA interrupt mask

◆ USB_OTG_DIEPEACHMSK1_BIM_Msk

#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)

0x00000200

◆ USB_OTG_DIEPEACHMSK1_EPDM

#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk

Endpoint disabled interrupt mask

◆ USB_OTG_DIEPEACHMSK1_EPDM_Msk

#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)

0x00000002

◆ USB_OTG_DIEPEACHMSK1_INEPNEM

#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk

IN endpoint NAK effective mask

◆ USB_OTG_DIEPEACHMSK1_INEPNEM_Msk

#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)

0x00000040

◆ USB_OTG_DIEPEACHMSK1_INEPNMM

#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk

IN token received with EP mismatch mask

◆ USB_OTG_DIEPEACHMSK1_INEPNMM_Msk

#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)

0x00000020

◆ USB_OTG_DIEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk

IN token received when TxFIFO empty mask

◆ USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)

0x00000010

◆ USB_OTG_DIEPEACHMSK1_NAKM

#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk

NAK interrupt mask

◆ USB_OTG_DIEPEACHMSK1_NAKM_Msk

#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)

0x00002000

◆ USB_OTG_DIEPEACHMSK1_TOM

#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk

Timeout condition mask (nonisochronous endpoints)

◆ USB_OTG_DIEPEACHMSK1_TOM_Msk

#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)

0x00000008

◆ USB_OTG_DIEPEACHMSK1_TXFURM

#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk

FIFO underrun mask

◆ USB_OTG_DIEPEACHMSK1_TXFURM_Msk

#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)

0x00000100

◆ USB_OTG_DIEPEACHMSK1_XFRCM

#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk

Transfer completed interrupt mask

◆ USB_OTG_DIEPEACHMSK1_XFRCM_Msk

#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)

0x00000001

◆ USB_OTG_DIEPEMPMSK_INEPTXFEM

#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk

IN EP Tx FIFO empty interrupt mask bits

◆ USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk

#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)

0x0000FFFF

◆ USB_OTG_DIEPINT_AHBERR

#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk

AHB Error (AHBErr) during an IN transaction

◆ USB_OTG_DIEPINT_AHBERR_Msk

#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)

0x00000004

◆ USB_OTG_DIEPINT_BERR

#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk

Babble error interrupt

◆ USB_OTG_DIEPINT_BERR_Msk

#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)

0x00001000

◆ USB_OTG_DIEPINT_BNA

#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk

Buffer not available interrupt

◆ USB_OTG_DIEPINT_BNA_Msk

#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)

0x00000200

◆ USB_OTG_DIEPINT_EPDISD

#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk

Endpoint disabled interrupt

◆ USB_OTG_DIEPINT_EPDISD_Msk

#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)

0x00000002

◆ USB_OTG_DIEPINT_INEPNE

#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk

IN endpoint NAK effective

◆ USB_OTG_DIEPINT_INEPNE_Msk

#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)

0x00000040

◆ USB_OTG_DIEPINT_INEPNM

#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk

IN token received with EP mismatch

◆ USB_OTG_DIEPINT_INEPNM_Msk

#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)

0x00000004

◆ USB_OTG_DIEPINT_ITTXFE

#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk

IN token received when TxFIFO is empty

◆ USB_OTG_DIEPINT_ITTXFE_Msk

#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)

0x00000010

◆ USB_OTG_DIEPINT_NAK

#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk

NAK interrupt

◆ USB_OTG_DIEPINT_NAK_Msk

#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)

0x00002000

◆ USB_OTG_DIEPINT_PKTDRPSTS

#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk

Packet dropped status

◆ USB_OTG_DIEPINT_PKTDRPSTS_Msk

#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)

0x00000800

◆ USB_OTG_DIEPINT_TOC

#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk

Timeout condition

◆ USB_OTG_DIEPINT_TOC_Msk

#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)

0x00000008

◆ USB_OTG_DIEPINT_TXFE

#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk

Transmit FIFO empty

◆ USB_OTG_DIEPINT_TXFE_Msk

#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)

0x00000080

◆ USB_OTG_DIEPINT_TXFIFOUDRN

#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk

Transmit Fifo Underrun

◆ USB_OTG_DIEPINT_TXFIFOUDRN_Msk

#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)

0x00000100

◆ USB_OTG_DIEPINT_XFRC

#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk

Transfer completed interrupt

◆ USB_OTG_DIEPINT_XFRC_Msk

#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)

0x00000001

◆ USB_OTG_DIEPMSK_EPDM

#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk

Endpoint disabled interrupt mask

◆ USB_OTG_DIEPMSK_EPDM_Msk

#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)

0x00000002

◆ USB_OTG_DIEPMSK_INEPNEM

#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk

IN endpoint NAK effective mask

◆ USB_OTG_DIEPMSK_INEPNEM_Msk

#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)

0x00000040

◆ USB_OTG_DIEPMSK_INEPNMM

#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk

IN token received with EP mismatch mask

◆ USB_OTG_DIEPMSK_INEPNMM_Msk

#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)

0x00000020

◆ USB_OTG_DIEPMSK_ITTXFEMSK

#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk

IN token received when TxFIFO empty mask

◆ USB_OTG_DIEPMSK_ITTXFEMSK_Msk

#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)

0x00000010

◆ USB_OTG_DIEPMSK_NAKM

#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk

NAK interrupt mask

◆ USB_OTG_DIEPMSK_NAKM_Msk

#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)

0x00002000

◆ USB_OTG_DIEPMSK_TOM

#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk

Timeout condition mask (nonisochronous endpoints)

◆ USB_OTG_DIEPMSK_TOM_Msk

#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)

0x00000008

◆ USB_OTG_DIEPMSK_TXFURM

#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk

FIFO underrun mask

◆ USB_OTG_DIEPMSK_TXFURM_Msk

#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)

0x00000100

◆ USB_OTG_DIEPMSK_XFRCM

#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk

Transfer completed interrupt mask

◆ USB_OTG_DIEPMSK_XFRCM_Msk

#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)

0x00000001

◆ USB_OTG_DIEPTSIZ_MULCNT

#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk

Packet count

◆ USB_OTG_DIEPTSIZ_MULCNT_Msk

#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)

0x60000000

◆ USB_OTG_DIEPTSIZ_PKTCNT

#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk

Packet count

◆ USB_OTG_DIEPTSIZ_PKTCNT_Msk

#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)

0x1FF80000

◆ USB_OTG_DIEPTSIZ_XFRSIZ

#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk

Transfer size

◆ USB_OTG_DIEPTSIZ_XFRSIZ_Msk

#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)

0x0007FFFF

◆ USB_OTG_DIEPTXF_INEPTXFD

#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk

IN endpoint TxFIFO depth

◆ USB_OTG_DIEPTXF_INEPTXFD_Msk

#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)

0xFFFF0000

◆ USB_OTG_DIEPTXF_INEPTXSA

#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk

IN endpoint FIFOx transmit RAM start address

◆ USB_OTG_DIEPTXF_INEPTXSA_Msk

#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)

0x0000FFFF

◆ USB_OTG_DOEPCTL_CNAK

#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk

Clear NAK

◆ USB_OTG_DOEPCTL_CNAK_Msk

#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)

0x04000000

◆ USB_OTG_DOEPCTL_EPDIS

#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk

Endpoint disable

◆ USB_OTG_DOEPCTL_EPDIS_Msk

#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)

0x40000000

◆ USB_OTG_DOEPCTL_EPENA

#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk

Endpoint enable

◆ USB_OTG_DOEPCTL_EPENA_Msk

#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)

0x80000000

◆ USB_OTG_DOEPCTL_EPTYP

#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk

Endpoint type

◆ USB_OTG_DOEPCTL_EPTYP_0

#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)

0x00040000

◆ USB_OTG_DOEPCTL_EPTYP_1

#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)

0x00080000

◆ USB_OTG_DOEPCTL_EPTYP_Msk

#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)

0x000C0000

◆ USB_OTG_DOEPCTL_MPSIZ

#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */

Bit 1

◆ USB_OTG_DOEPCTL_MPSIZ_Msk

#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)

0x000007FF

◆ USB_OTG_DOEPCTL_NAKSTS

#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk

NAK status

◆ USB_OTG_DOEPCTL_NAKSTS_Msk

#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)

0x00020000

◆ USB_OTG_DOEPCTL_SD0PID_SEVNFRM

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk

Set DATA0 PID

◆ USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)

0x10000000

◆ USB_OTG_DOEPCTL_SNAK

#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk

Set NAK

◆ USB_OTG_DOEPCTL_SNAK_Msk

#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)

0x08000000

◆ USB_OTG_DOEPCTL_SNPM

#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk

Snoop mode

◆ USB_OTG_DOEPCTL_SNPM_Msk

#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)

0x00100000

◆ USB_OTG_DOEPCTL_SODDFRM

#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk

Set odd frame

◆ USB_OTG_DOEPCTL_SODDFRM_Msk

#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)

0x20000000

◆ USB_OTG_DOEPCTL_STALL

#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk

STALL handshake

◆ USB_OTG_DOEPCTL_STALL_Msk

#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)

0x00200000

◆ USB_OTG_DOEPCTL_USBAEP

#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk

USB active endpoint

◆ USB_OTG_DOEPCTL_USBAEP_Msk

#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)

0x00008000

◆ USB_OTG_DOEPEACHMSK1_BERRM

#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk

Bubble error interrupt mask

◆ USB_OTG_DOEPEACHMSK1_BERRM_Msk

#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)

0x00001000

◆ USB_OTG_DOEPEACHMSK1_BIM

#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk

BNA interrupt mask

◆ USB_OTG_DOEPEACHMSK1_BIM_Msk

#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)

0x00000200

◆ USB_OTG_DOEPEACHMSK1_EPDM

#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk

Endpoint disabled interrupt mask

◆ USB_OTG_DOEPEACHMSK1_EPDM_Msk

#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)

0x00000002

◆ USB_OTG_DOEPEACHMSK1_INEPNEM

#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk

IN endpoint NAK effective mask

◆ USB_OTG_DOEPEACHMSK1_INEPNEM_Msk

#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)

0x00000040

◆ USB_OTG_DOEPEACHMSK1_INEPNMM

#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk

IN token received with EP mismatch mask

◆ USB_OTG_DOEPEACHMSK1_INEPNMM_Msk

#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)

0x00000020

◆ USB_OTG_DOEPEACHMSK1_ITTXFEMSK

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk

IN token received when TxFIFO empty mask

◆ USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)

0x00000010

◆ USB_OTG_DOEPEACHMSK1_NAKM

#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk

NAK interrupt mask

◆ USB_OTG_DOEPEACHMSK1_NAKM_Msk

#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)

0x00002000

◆ USB_OTG_DOEPEACHMSK1_NYETM

#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk

NYET interrupt mask

◆ USB_OTG_DOEPEACHMSK1_NYETM_Msk

#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)

0x00004000

◆ USB_OTG_DOEPEACHMSK1_TOM

#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk

Timeout condition mask

◆ USB_OTG_DOEPEACHMSK1_TOM_Msk

#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)

0x00000008

◆ USB_OTG_DOEPEACHMSK1_TXFURM

#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk

OUT packet error mask

◆ USB_OTG_DOEPEACHMSK1_TXFURM_Msk

#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)

0x00000100

◆ USB_OTG_DOEPEACHMSK1_XFRCM

#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk

Transfer completed interrupt mask

◆ USB_OTG_DOEPEACHMSK1_XFRCM_Msk

#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)

0x00000001

◆ USB_OTG_DOEPINT_AHBERR

#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk

AHB Error (AHBErr) during an OUT transaction

◆ USB_OTG_DOEPINT_AHBERR_Msk

#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)

0x00000004

◆ USB_OTG_DOEPINT_B2BSTUP

#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk

Back-to-back SETUP packets received

◆ USB_OTG_DOEPINT_B2BSTUP_Msk

#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)

0x00000040

◆ USB_OTG_DOEPINT_EPDISD

#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk

Endpoint disabled interrupt

◆ USB_OTG_DOEPINT_EPDISD_Msk

#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)

0x00000002

◆ USB_OTG_DOEPINT_NAK

#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk

NAK Packet is transmitted by the device

◆ USB_OTG_DOEPINT_NAK_Msk

#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)

0x00002000

◆ USB_OTG_DOEPINT_NYET

#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk

NYET interrupt

◆ USB_OTG_DOEPINT_NYET_Msk

#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)

0x00004000

◆ USB_OTG_DOEPINT_OTEPDIS

#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk

OUT token received when endpoint disabled

◆ USB_OTG_DOEPINT_OTEPDIS_Msk

#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)

0x00000010

◆ USB_OTG_DOEPINT_OTEPSPR

#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk

Status Phase Received For Control Write

◆ USB_OTG_DOEPINT_OTEPSPR_Msk

#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)

0x00000020

◆ USB_OTG_DOEPINT_OUTPKTERR

#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk

OUT packet error

◆ USB_OTG_DOEPINT_OUTPKTERR_Msk

#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)

0x00000100

◆ USB_OTG_DOEPINT_STPKTRX

#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk

Setup Packet Received

◆ USB_OTG_DOEPINT_STPKTRX_Msk

#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)

0x00008000

◆ USB_OTG_DOEPINT_STUP

#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk

SETUP phase done

◆ USB_OTG_DOEPINT_STUP_Msk

#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)

0x00000008

◆ USB_OTG_DOEPINT_XFRC

#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk

Transfer completed interrupt

◆ USB_OTG_DOEPINT_XFRC_Msk

#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)

0x00000001

◆ USB_OTG_DOEPMSK_AHBERRM

#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk

OUT transaction AHB Error interrupt mask

◆ USB_OTG_DOEPMSK_AHBERRM_Msk

#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)

0x00000004

◆ USB_OTG_DOEPMSK_B2BSTUP

#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk

Back-to-back SETUP packets received mask

◆ USB_OTG_DOEPMSK_B2BSTUP_Msk

#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)

0x00000040

◆ USB_OTG_DOEPMSK_BERRM

#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk

Babble error interrupt mask

◆ USB_OTG_DOEPMSK_BERRM_Msk

#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)

0x00001000

◆ USB_OTG_DOEPMSK_BOIM

#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk

BNA interrupt mask

◆ USB_OTG_DOEPMSK_BOIM_Msk

#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)

0x00000200

◆ USB_OTG_DOEPMSK_EPDM

#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk

Endpoint disabled interrupt mask

◆ USB_OTG_DOEPMSK_EPDM_Msk

#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)

0x00000002

◆ USB_OTG_DOEPMSK_NAKM

#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk

OUT Packet NAK interrupt mask

◆ USB_OTG_DOEPMSK_NAKM_Msk

#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)

0x00002000

◆ USB_OTG_DOEPMSK_NYETM

#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk

NYET interrupt mask

◆ USB_OTG_DOEPMSK_NYETM_Msk

#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)

0x00004000

◆ USB_OTG_DOEPMSK_OPEM

#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk

OUT packet error mask

◆ USB_OTG_DOEPMSK_OPEM_Msk

#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)

0x00000100

◆ USB_OTG_DOEPMSK_OTEPDM

#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk

OUT token received when endpoint disabled mask

◆ USB_OTG_DOEPMSK_OTEPDM_Msk

#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)

0x00000010

◆ USB_OTG_DOEPMSK_OTEPSPRM

#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk

Status Phase Received mask

◆ USB_OTG_DOEPMSK_OTEPSPRM_Msk

#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)

0x00000020

◆ USB_OTG_DOEPMSK_STUPM

#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk

SETUP phase done mask

◆ USB_OTG_DOEPMSK_STUPM_Msk

#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)

0x00000008

◆ USB_OTG_DOEPMSK_XFRCM

#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk

Transfer completed interrupt mask

◆ USB_OTG_DOEPMSK_XFRCM_Msk

#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)

0x00000001

◆ USB_OTG_DOEPTSIZ_PKTCNT

#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk

Packet count

◆ USB_OTG_DOEPTSIZ_PKTCNT_Msk

#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)

0x1FF80000

◆ USB_OTG_DOEPTSIZ_STUPCNT

#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk

SETUP packet count

◆ USB_OTG_DOEPTSIZ_STUPCNT_0

#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

0x20000000

◆ USB_OTG_DOEPTSIZ_STUPCNT_1

#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

0x40000000

◆ USB_OTG_DOEPTSIZ_STUPCNT_Msk

#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

0x60000000

◆ USB_OTG_DOEPTSIZ_XFRSIZ

#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk

Transfer size

◆ USB_OTG_DOEPTSIZ_XFRSIZ_Msk

#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)

0x0007FFFF

◆ USB_OTG_DPID

#define USB_OTG_DPID USB_OTG_DPID_Msk

Data PID

◆ USB_OTG_DPID_0

#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)

0x00008000

◆ USB_OTG_DPID_1

#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)

0x00010000

◆ USB_OTG_DPID_Msk

#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)

0x00018000

◆ USB_OTG_DSTS_EERR

#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk

Erratic error

◆ USB_OTG_DSTS_EERR_Msk

#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)

0x00000008

◆ USB_OTG_DSTS_ENUMSPD

#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk

Enumerated speed

◆ USB_OTG_DSTS_ENUMSPD_0

#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)

0x00000002

◆ USB_OTG_DSTS_ENUMSPD_1

#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)

0x00000004

◆ USB_OTG_DSTS_ENUMSPD_Msk

#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)

0x00000006

◆ USB_OTG_DSTS_FNSOF

#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk

Frame number of the received SOF

◆ USB_OTG_DSTS_FNSOF_Msk

#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)

0x003FFF00

◆ USB_OTG_DSTS_SUSPSTS

#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk

Suspend status

◆ USB_OTG_DSTS_SUSPSTS_Msk

#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)

0x00000001

◆ USB_OTG_DTHRCTL_ARPEN

#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk

Arbiter parking enable

◆ USB_OTG_DTHRCTL_ARPEN_Msk

#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)

0x08000000

◆ USB_OTG_DTHRCTL_ISOTHREN

#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk

ISO IN endpoint threshold enable

◆ USB_OTG_DTHRCTL_ISOTHREN_Msk

#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)

0x00000002

◆ USB_OTG_DTHRCTL_NONISOTHREN

#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk

Nonisochronous IN endpoints threshold enable

◆ USB_OTG_DTHRCTL_NONISOTHREN_Msk

#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)

0x00000001

◆ USB_OTG_DTHRCTL_RXTHREN

#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk

Receive threshold enable

◆ USB_OTG_DTHRCTL_RXTHREN_Msk

#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)

0x00010000

◆ USB_OTG_DTHRCTL_RXTHRLEN

#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk

Receive threshold length

◆ USB_OTG_DTHRCTL_RXTHRLEN_0

#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00020000

◆ USB_OTG_DTHRCTL_RXTHRLEN_1

#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00040000

◆ USB_OTG_DTHRCTL_RXTHRLEN_2

#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00080000

◆ USB_OTG_DTHRCTL_RXTHRLEN_3

#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00100000

◆ USB_OTG_DTHRCTL_RXTHRLEN_4

#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00200000

◆ USB_OTG_DTHRCTL_RXTHRLEN_5

#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00400000

◆ USB_OTG_DTHRCTL_RXTHRLEN_6

#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x00800000

◆ USB_OTG_DTHRCTL_RXTHRLEN_7

#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x01000000

◆ USB_OTG_DTHRCTL_RXTHRLEN_8

#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x02000000

◆ USB_OTG_DTHRCTL_RXTHRLEN_Msk

#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

0x03FE0000

◆ USB_OTG_DTHRCTL_TXTHRLEN

#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk

Transmit threshold length

◆ USB_OTG_DTHRCTL_TXTHRLEN_0

#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000004

◆ USB_OTG_DTHRCTL_TXTHRLEN_1

#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000008

◆ USB_OTG_DTHRCTL_TXTHRLEN_2

#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000010

◆ USB_OTG_DTHRCTL_TXTHRLEN_3

#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000020

◆ USB_OTG_DTHRCTL_TXTHRLEN_4

#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000040

◆ USB_OTG_DTHRCTL_TXTHRLEN_5

#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000080

◆ USB_OTG_DTHRCTL_TXTHRLEN_6

#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000100

◆ USB_OTG_DTHRCTL_TXTHRLEN_7

#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000200

◆ USB_OTG_DTHRCTL_TXTHRLEN_8

#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x00000400

◆ USB_OTG_DTHRCTL_TXTHRLEN_Msk

#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

0x000007FC

◆ USB_OTG_DTXFSTS_INEPTFSAV

#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk

IN endpoint TxFIFO space available

◆ USB_OTG_DTXFSTS_INEPTFSAV_Msk

#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)

0x0000FFFF

◆ USB_OTG_DVBUSDIS_VBUSDT

#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk

Device VBUS discharge time

◆ USB_OTG_DVBUSDIS_VBUSDT_Msk

#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)

0x0000FFFF

◆ USB_OTG_DVBUSPULSE_DVBUSP

#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk

Device VBUS pulsing time

◆ USB_OTG_DVBUSPULSE_DVBUSP_Msk

#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)

0x00000FFF

◆ USB_OTG_EPNUM

#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk

Endpoint number

◆ USB_OTG_EPNUM_0

#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)

0x00000001

◆ USB_OTG_EPNUM_1

#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)

0x00000002

◆ USB_OTG_EPNUM_2

#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)

0x00000004

◆ USB_OTG_EPNUM_3

#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)

0x00000008

◆ USB_OTG_EPNUM_Msk

#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)

0x0000000F

◆ USB_OTG_FRMNUM

#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk

Frame number

◆ USB_OTG_FRMNUM_0

#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)

0x00200000

◆ USB_OTG_FRMNUM_1

#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)

0x00400000

◆ USB_OTG_FRMNUM_2

#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)

0x00800000

◆ USB_OTG_FRMNUM_3

#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)

0x01000000

◆ USB_OTG_FRMNUM_Msk

#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)

0x01E00000

◆ USB_OTG_GAHBCFG_DMAEN

#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk

DMA enable

◆ USB_OTG_GAHBCFG_DMAEN_Msk

#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)

0x00000020

◆ USB_OTG_GAHBCFG_GINT

#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk

Global interrupt mask

◆ USB_OTG_GAHBCFG_GINT_Msk

#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)

0x00000001

◆ USB_OTG_GAHBCFG_HBSTLEN

#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk

Burst length/type

◆ USB_OTG_GAHBCFG_HBSTLEN_0

#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

Single

◆ USB_OTG_GAHBCFG_HBSTLEN_1

#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

INCR

◆ USB_OTG_GAHBCFG_HBSTLEN_2

#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

INCR4

◆ USB_OTG_GAHBCFG_HBSTLEN_3

#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

INCR8

◆ USB_OTG_GAHBCFG_HBSTLEN_4

#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

INCR16

◆ USB_OTG_GAHBCFG_HBSTLEN_Msk

#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

0x0000001E

◆ USB_OTG_GAHBCFG_PTXFELVL

#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk

Periodic TxFIFO empty level

◆ USB_OTG_GAHBCFG_PTXFELVL_Msk

#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)

0x00000100

◆ USB_OTG_GAHBCFG_TXFELVL

#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk

TxFIFO empty level

◆ USB_OTG_GAHBCFG_TXFELVL_Msk

#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)

0x00000080

◆ USB_OTG_GCCFG_I2CPADEN

#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk

Enable I2C bus connection for the external I2C PHY interface

◆ USB_OTG_GCCFG_I2CPADEN_Msk

#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)

0x00020000

◆ USB_OTG_GCCFG_NOVBUSSENS

#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk

VBUS sensing disable option

◆ USB_OTG_GCCFG_NOVBUSSENS_Msk

#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)

0x00200000

◆ USB_OTG_GCCFG_PWRDWN

#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk

Power down

◆ USB_OTG_GCCFG_PWRDWN_Msk

#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)

0x00010000

◆ USB_OTG_GCCFG_SOFOUTEN

#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk

SOF output enable

◆ USB_OTG_GCCFG_SOFOUTEN_Msk

#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)

0x00100000

◆ USB_OTG_GCCFG_VBUSASEN

#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk

Enable the VBUS sensing device

◆ USB_OTG_GCCFG_VBUSASEN_Msk

#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)

0x00040000

◆ USB_OTG_GCCFG_VBUSBSEN

#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk

Enable the VBUS sensing device

◆ USB_OTG_GCCFG_VBUSBSEN_Msk

#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)

0x00080000

◆ USB_OTG_GINTMSK_CIDSCHGM

#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk

Connector ID status change mask

◆ USB_OTG_GINTMSK_CIDSCHGM_Msk

#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)

0x10000000

◆ USB_OTG_GINTMSK_DISCINT

#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk

Disconnect detected interrupt mask

◆ USB_OTG_GINTMSK_DISCINT_Msk

#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)

0x20000000

◆ USB_OTG_GINTMSK_ENUMDNEM

#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk

Enumeration done mask

◆ USB_OTG_GINTMSK_ENUMDNEM_Msk

#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)

0x00002000

◆ USB_OTG_GINTMSK_EOPFM

#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk

End of periodic frame interrupt mask

◆ USB_OTG_GINTMSK_EOPFM_Msk

#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)

0x00008000

◆ USB_OTG_GINTMSK_EPMISM

#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk

Endpoint mismatch interrupt mask

◆ USB_OTG_GINTMSK_EPMISM_Msk

#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)

0x00020000

◆ USB_OTG_GINTMSK_ESUSPM

#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk

Early suspend mask

◆ USB_OTG_GINTMSK_ESUSPM_Msk

#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)

0x00000400

◆ USB_OTG_GINTMSK_FSUSPM

#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk

Data fetch suspended mask

◆ USB_OTG_GINTMSK_FSUSPM_Msk

#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)

0x00400000

◆ USB_OTG_GINTMSK_GINAKEFFM

#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk

Global nonperiodic IN NAK effective mask

◆ USB_OTG_GINTMSK_GINAKEFFM_Msk

#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)

0x00000040

◆ USB_OTG_GINTMSK_GONAKEFFM

#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk

Global OUT NAK effective mask

◆ USB_OTG_GINTMSK_GONAKEFFM_Msk

#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)

0x00000080

◆ USB_OTG_GINTMSK_HCIM

#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk

Host channels interrupt mask

◆ USB_OTG_GINTMSK_HCIM_Msk

#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)

0x02000000

◆ USB_OTG_GINTMSK_IEPINT

#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk

IN endpoints interrupt mask

◆ USB_OTG_GINTMSK_IEPINT_Msk

#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)

0x00040000

◆ USB_OTG_GINTMSK_IISOIXFRM

#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk

Incomplete isochronous IN transfer mask

◆ USB_OTG_GINTMSK_IISOIXFRM_Msk

#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)

0x00100000

◆ USB_OTG_GINTMSK_ISOODRPM

#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk

Isochronous OUT packet dropped interrupt mask

◆ USB_OTG_GINTMSK_ISOODRPM_Msk

#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)

0x00004000

◆ USB_OTG_GINTMSK_MMISM

#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk

Mode mismatch interrupt mask

◆ USB_OTG_GINTMSK_MMISM_Msk

#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)

0x00000002

◆ USB_OTG_GINTMSK_NPTXFEM

#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk

Nonperiodic TxFIFO empty mask

◆ USB_OTG_GINTMSK_NPTXFEM_Msk

#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)

0x00000020

◆ USB_OTG_GINTMSK_OEPINT

#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk

OUT endpoints interrupt mask

◆ USB_OTG_GINTMSK_OEPINT_Msk

#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)

0x00080000

◆ USB_OTG_GINTMSK_OTGINT

#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk

OTG interrupt mask

◆ USB_OTG_GINTMSK_OTGINT_Msk

#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)

0x00000004

◆ USB_OTG_GINTMSK_PRTIM

#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk

Host port interrupt mask

◆ USB_OTG_GINTMSK_PRTIM_Msk

#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)

0x01000000

◆ USB_OTG_GINTMSK_PTXFEM

#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk

Periodic TxFIFO empty mask

◆ USB_OTG_GINTMSK_PTXFEM_Msk

#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)

0x04000000

◆ USB_OTG_GINTMSK_PXFRM_IISOOXFRM

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk

Incomplete periodic transfer mask

◆ USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)

0x00200000

◆ USB_OTG_GINTMSK_RXFLVLM

#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk

Receive FIFO nonempty mask

◆ USB_OTG_GINTMSK_RXFLVLM_Msk

#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)

0x00000010

◆ USB_OTG_GINTMSK_SOFM

#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk

Start of frame mask

◆ USB_OTG_GINTMSK_SOFM_Msk

#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)

0x00000008

◆ USB_OTG_GINTMSK_SRQIM

#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk

Session request/new session detected interrupt mask

◆ USB_OTG_GINTMSK_SRQIM_Msk

#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)

0x40000000

◆ USB_OTG_GINTMSK_USBRST

#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk

USB reset mask

◆ USB_OTG_GINTMSK_USBRST_Msk

#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)

0x00001000

◆ USB_OTG_GINTMSK_USBSUSPM

#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk

USB suspend mask

◆ USB_OTG_GINTMSK_USBSUSPM_Msk

#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)

0x00000800

◆ USB_OTG_GINTMSK_WUIM

#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk

Resume/remote wakeup detected interrupt mask

◆ USB_OTG_GINTMSK_WUIM_Msk

#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)

0x80000000

◆ USB_OTG_GINTSTS_BOUTNAKEFF

#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk

Global OUT NAK effective

◆ USB_OTG_GINTSTS_BOUTNAKEFF_Msk

#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)

0x00000080

◆ USB_OTG_GINTSTS_CIDSCHG

#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk

Connector ID status change

◆ USB_OTG_GINTSTS_CIDSCHG_Msk

#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)

0x10000000

◆ USB_OTG_GINTSTS_CMOD

#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk

Current mode of operation

◆ USB_OTG_GINTSTS_CMOD_Msk

#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)

0x00000001

◆ USB_OTG_GINTSTS_DATAFSUSP

#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk

Data fetch suspended

◆ USB_OTG_GINTSTS_DATAFSUSP_Msk

#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)

0x00400000

◆ USB_OTG_GINTSTS_DISCINT

#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk

Disconnect detected interrupt

◆ USB_OTG_GINTSTS_DISCINT_Msk

#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)

0x20000000

◆ USB_OTG_GINTSTS_ENUMDNE

#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk

Enumeration done

◆ USB_OTG_GINTSTS_ENUMDNE_Msk

#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)

0x00002000

◆ USB_OTG_GINTSTS_EOPF

#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk

End of periodic frame interrupt

◆ USB_OTG_GINTSTS_EOPF_Msk

#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)

0x00008000

◆ USB_OTG_GINTSTS_ESUSP

#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk

Early suspend

◆ USB_OTG_GINTSTS_ESUSP_Msk

#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)

0x00000400

◆ USB_OTG_GINTSTS_GINAKEFF

#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk

Global IN nonperiodic NAK effective

◆ USB_OTG_GINTSTS_GINAKEFF_Msk

#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)

0x00000040

◆ USB_OTG_GINTSTS_HCINT

#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk

Host channels interrupt

◆ USB_OTG_GINTSTS_HCINT_Msk

#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)

0x02000000

◆ USB_OTG_GINTSTS_HPRTINT

#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk

Host port interrupt

◆ USB_OTG_GINTSTS_HPRTINT_Msk

#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)

0x01000000

◆ USB_OTG_GINTSTS_IEPINT

#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk

IN endpoint interrupt

◆ USB_OTG_GINTSTS_IEPINT_Msk

#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)

0x00040000

◆ USB_OTG_GINTSTS_IISOIXFR

#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk

Incomplete isochronous IN transfer

◆ USB_OTG_GINTSTS_IISOIXFR_Msk

#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)

0x00100000

◆ USB_OTG_GINTSTS_ISOODRP

#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk

Isochronous OUT packet dropped interrupt

◆ USB_OTG_GINTSTS_ISOODRP_Msk

#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)

0x00004000

◆ USB_OTG_GINTSTS_MMIS

#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk

Mode mismatch interrupt

◆ USB_OTG_GINTSTS_MMIS_Msk

#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)

0x00000002

◆ USB_OTG_GINTSTS_NPTXFE

#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk

Nonperiodic TxFIFO empty

◆ USB_OTG_GINTSTS_NPTXFE_Msk

#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)

0x00000020

◆ USB_OTG_GINTSTS_OEPINT

#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk

OUT endpoint interrupt

◆ USB_OTG_GINTSTS_OEPINT_Msk

#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)

0x00080000

◆ USB_OTG_GINTSTS_OTGINT

#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk

OTG interrupt

◆ USB_OTG_GINTSTS_OTGINT_Msk

#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)

0x00000004

◆ USB_OTG_GINTSTS_PTXFE

#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk

Periodic TxFIFO empty

◆ USB_OTG_GINTSTS_PTXFE_Msk

#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)

0x04000000

◆ USB_OTG_GINTSTS_PXFR_INCOMPISOOUT

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk

Incomplete periodic transfer

◆ USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)

0x00200000

◆ USB_OTG_GINTSTS_RXFLVL

#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk

RxFIFO nonempty

◆ USB_OTG_GINTSTS_RXFLVL_Msk

#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)

0x00000010

◆ USB_OTG_GINTSTS_SOF

#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk

Start of frame

◆ USB_OTG_GINTSTS_SOF_Msk

#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)

0x00000008

◆ USB_OTG_GINTSTS_SRQINT

#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk

Session request/new session detected interrupt

◆ USB_OTG_GINTSTS_SRQINT_Msk

#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)

0x40000000

◆ USB_OTG_GINTSTS_USBRST

#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk

USB reset

◆ USB_OTG_GINTSTS_USBRST_Msk

#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)

0x00001000

◆ USB_OTG_GINTSTS_USBSUSP

#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk

USB suspend

◆ USB_OTG_GINTSTS_USBSUSP_Msk

#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)

0x00000800

◆ USB_OTG_GINTSTS_WKUINT

#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk

Resume/remote wakeup detected interrupt

◆ USB_OTG_GINTSTS_WKUINT_Msk

#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)

0x80000000

◆ USB_OTG_GNPTXSTS_NPTQXSAV

#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk

Nonperiodic transmit request queue space available

◆ USB_OTG_GNPTXSTS_NPTQXSAV_0

#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00010000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_1

#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00020000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_2

#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00040000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_3

#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00080000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_4

#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00100000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_5

#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00200000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_6

#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00400000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_7

#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00800000

◆ USB_OTG_GNPTXSTS_NPTQXSAV_Msk

#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

0x00FF0000

◆ USB_OTG_GNPTXSTS_NPTXFSAV

#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk

Nonperiodic TxFIFO space available

◆ USB_OTG_GNPTXSTS_NPTXFSAV_Msk

#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)

0x0000FFFF

◆ USB_OTG_GNPTXSTS_NPTXQTOP

#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk

Top of the nonperiodic transmit request queue

◆ USB_OTG_GNPTXSTS_NPTXQTOP_0

#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x01000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_1

#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x02000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_2

#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x04000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_3

#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x08000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_4

#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x10000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_5

#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x20000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_6

#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x40000000

◆ USB_OTG_GNPTXSTS_NPTXQTOP_Msk

#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

0x7F000000

◆ USB_OTG_GOTGCTL_ASVLD

#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk

A-session valid

◆ USB_OTG_GOTGCTL_ASVLD_Msk

#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)

0x00040000

◆ USB_OTG_GOTGCTL_BSVLD

#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk

B-session valid

◆ USB_OTG_GOTGCTL_BSVLD_Msk

#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)

0x00080000

◆ USB_OTG_GOTGCTL_CIDSTS

#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk

Connector ID status

◆ USB_OTG_GOTGCTL_CIDSTS_Msk

#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)

0x00010000

◆ USB_OTG_GOTGCTL_DBCT

#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk

Long/short debounce time

◆ USB_OTG_GOTGCTL_DBCT_Msk

#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)

0x00020000

◆ USB_OTG_GOTGCTL_DHNPEN

#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk

Device HNP enabled

◆ USB_OTG_GOTGCTL_DHNPEN_Msk

#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)

0x00000800

◆ USB_OTG_GOTGCTL_HNGSCS

#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk

Host set HNP enable

◆ USB_OTG_GOTGCTL_HNGSCS_Msk

#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)

0x00000100

◆ USB_OTG_GOTGCTL_HNPRQ

#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk

HNP request

◆ USB_OTG_GOTGCTL_HNPRQ_Msk

#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)

0x00000200

◆ USB_OTG_GOTGCTL_HSHNPEN

#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk

Host set HNP enable

◆ USB_OTG_GOTGCTL_HSHNPEN_Msk

#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)

0x00000400

◆ USB_OTG_GOTGCTL_SRQ

#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk

Session request

◆ USB_OTG_GOTGCTL_SRQ_Msk

#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)

0x00000002

◆ USB_OTG_GOTGCTL_SRQSCS

#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk

Session request success

◆ USB_OTG_GOTGCTL_SRQSCS_Msk

#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)

0x00000001

◆ USB_OTG_GOTGINT_ADTOCHG

#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk

A-device timeout change

◆ USB_OTG_GOTGINT_ADTOCHG_Msk

#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)

0x00040000

◆ USB_OTG_GOTGINT_DBCDNE

#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk

Debounce done

◆ USB_OTG_GOTGINT_DBCDNE_Msk

#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)

0x00080000

◆ USB_OTG_GOTGINT_HNGDET

#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk

Host negotiation detected

◆ USB_OTG_GOTGINT_HNGDET_Msk

#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)

0x00020000

◆ USB_OTG_GOTGINT_HNSSCHG

#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk

Host negotiation success status change

◆ USB_OTG_GOTGINT_HNSSCHG_Msk

#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)

0x00000200

◆ USB_OTG_GOTGINT_SEDET

#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk

Session end detected

◆ USB_OTG_GOTGINT_SEDET_Msk

#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)

0x00000004

◆ USB_OTG_GOTGINT_SRSSCHG

#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk

Session request success status change

◆ USB_OTG_GOTGINT_SRSSCHG_Msk

#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)

0x00000100

◆ USB_OTG_GRSTCTL_AHBIDL

#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk

AHB master idle

◆ USB_OTG_GRSTCTL_AHBIDL_Msk

#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)

0x80000000

◆ USB_OTG_GRSTCTL_CSRST

#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk

Core soft reset

◆ USB_OTG_GRSTCTL_CSRST_Msk

#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)

0x00000001

◆ USB_OTG_GRSTCTL_DMAREQ

#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk

DMA request signal

◆ USB_OTG_GRSTCTL_DMAREQ_Msk

#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)

0x40000000

◆ USB_OTG_GRSTCTL_FCRST

#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk

Host frame counter reset

◆ USB_OTG_GRSTCTL_FCRST_Msk

#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)

0x00000004

◆ USB_OTG_GRSTCTL_HSRST

#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk

HCLK soft reset

◆ USB_OTG_GRSTCTL_HSRST_Msk

#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)

0x00000002

◆ USB_OTG_GRSTCTL_RXFFLSH

#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk

RxFIFO flush

◆ USB_OTG_GRSTCTL_RXFFLSH_Msk

#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)

0x00000010

◆ USB_OTG_GRSTCTL_TXFFLSH

#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk

TxFIFO flush

◆ USB_OTG_GRSTCTL_TXFFLSH_Msk

#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)

0x00000020

◆ USB_OTG_GRSTCTL_TXFNUM

#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk

TxFIFO number

◆ USB_OTG_GRSTCTL_TXFNUM_0

#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x00000040

◆ USB_OTG_GRSTCTL_TXFNUM_1

#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x00000080

◆ USB_OTG_GRSTCTL_TXFNUM_2

#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x00000100

◆ USB_OTG_GRSTCTL_TXFNUM_3

#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x00000200

◆ USB_OTG_GRSTCTL_TXFNUM_4

#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x00000400

◆ USB_OTG_GRSTCTL_TXFNUM_Msk

#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)

0x000007C0

◆ USB_OTG_GRXFSIZ_RXFD

#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk

RxFIFO depth

◆ USB_OTG_GRXFSIZ_RXFD_Msk

#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)

0x0000FFFF

◆ USB_OTG_GRXSTSP_BCNT

#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk

OUT EP interrupt mask bits

◆ USB_OTG_GRXSTSP_BCNT_Msk

#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)

0x00007FF0

◆ USB_OTG_GRXSTSP_DPID

#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk

OUT EP interrupt mask bits

◆ USB_OTG_GRXSTSP_DPID_Msk

#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)

0x00018000

◆ USB_OTG_GRXSTSP_EPNUM

#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk

IN EP interrupt mask bits

◆ USB_OTG_GRXSTSP_EPNUM_Msk

#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)

0x0000000F

◆ USB_OTG_GRXSTSP_PKTSTS

#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk

OUT EP interrupt mask bits

◆ USB_OTG_GRXSTSP_PKTSTS_Msk

#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)

0x001E0000

◆ USB_OTG_GUSBCFG_CTXPKT

#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk

Corrupt Tx packet

◆ USB_OTG_GUSBCFG_CTXPKT_Msk

#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)

0x80000000

◆ USB_OTG_GUSBCFG_FDMOD

#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk

Forced peripheral mode

◆ USB_OTG_GUSBCFG_FDMOD_Msk

#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)

0x40000000

◆ USB_OTG_GUSBCFG_FHMOD

#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk

Forced host mode

◆ USB_OTG_GUSBCFG_FHMOD_Msk

#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)

0x20000000

◆ USB_OTG_GUSBCFG_HNPCAP

#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk

HNP-capable

◆ USB_OTG_GUSBCFG_HNPCAP_Msk

#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)

0x00000200

◆ USB_OTG_GUSBCFG_PCCI

#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk

Indicator complement

◆ USB_OTG_GUSBCFG_PCCI_Msk

#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)

0x00800000

◆ USB_OTG_GUSBCFG_PHYLPCS

#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk

PHY Low-power clock select

◆ USB_OTG_GUSBCFG_PHYLPCS_Msk

#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)

0x00008000

◆ USB_OTG_GUSBCFG_PHYSEL

#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk

USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

◆ USB_OTG_GUSBCFG_PHYSEL_Msk

#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)

0x00000040

◆ USB_OTG_GUSBCFG_PTCI

#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk

Indicator pass through

◆ USB_OTG_GUSBCFG_PTCI_Msk

#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)

0x01000000

◆ USB_OTG_GUSBCFG_SRPCAP

#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk

SRP-capable

◆ USB_OTG_GUSBCFG_SRPCAP_Msk

#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)

0x00000100

◆ USB_OTG_GUSBCFG_TOCAL

#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk

FS timeout calibration

◆ USB_OTG_GUSBCFG_TOCAL_0

#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)

0x00000001

◆ USB_OTG_GUSBCFG_TOCAL_1

#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)

0x00000002

◆ USB_OTG_GUSBCFG_TOCAL_2

#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)

0x00000004

◆ USB_OTG_GUSBCFG_TOCAL_Msk

#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)

0x00000007

◆ USB_OTG_GUSBCFG_TRDT

#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk

USB turnaround time

◆ USB_OTG_GUSBCFG_TRDT_0

#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)

0x00000400

◆ USB_OTG_GUSBCFG_TRDT_1

#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)

0x00000800

◆ USB_OTG_GUSBCFG_TRDT_2

#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)

0x00001000

◆ USB_OTG_GUSBCFG_TRDT_3

#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)

0x00002000

◆ USB_OTG_GUSBCFG_TRDT_Msk

#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)

0x00003C00

◆ USB_OTG_GUSBCFG_TSDPS

#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk

TermSel DLine pulsing selection

◆ USB_OTG_GUSBCFG_TSDPS_Msk

#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)

0x00400000

◆ USB_OTG_GUSBCFG_ULPIAR

#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk

ULPI Auto-resume

◆ USB_OTG_GUSBCFG_ULPIAR_Msk

#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)

0x00040000

◆ USB_OTG_GUSBCFG_ULPICSM

#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk

ULPI Clock SuspendM

◆ USB_OTG_GUSBCFG_ULPICSM_Msk

#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)

0x00080000

◆ USB_OTG_GUSBCFG_ULPIEVBUSD

#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk

ULPI External VBUS Drive

◆ USB_OTG_GUSBCFG_ULPIEVBUSD_Msk

#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)

0x00100000

◆ USB_OTG_GUSBCFG_ULPIEVBUSI

#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk

ULPI external VBUS indicator

◆ USB_OTG_GUSBCFG_ULPIEVBUSI_Msk

#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)

0x00200000

◆ USB_OTG_GUSBCFG_ULPIFSLS

#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk

ULPI FS/LS select

◆ USB_OTG_GUSBCFG_ULPIFSLS_Msk

#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)

0x00020000

◆ USB_OTG_GUSBCFG_ULPIIPD

#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk

ULPI interface protect disable

◆ USB_OTG_GUSBCFG_ULPIIPD_Msk

#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)

0x02000000

◆ USB_OTG_HAINT_HAINT

#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk

Channel interrupts

◆ USB_OTG_HAINT_HAINT_Msk

#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)

0x0000FFFF

◆ USB_OTG_HAINTMSK_HAINTM

#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk

Channel interrupt mask

◆ USB_OTG_HAINTMSK_HAINTM_Msk

#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)

0x0000FFFF

◆ USB_OTG_HCCHAR_CHDIS

#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk

Channel disable

◆ USB_OTG_HCCHAR_CHDIS_Msk

#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)

0x40000000

◆ USB_OTG_HCCHAR_CHENA

#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk

Channel enable

◆ USB_OTG_HCCHAR_CHENA_Msk

#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)

0x80000000

◆ USB_OTG_HCCHAR_DAD

#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk

Device address

◆ USB_OTG_HCCHAR_DAD_0

#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)

0x00400000

◆ USB_OTG_HCCHAR_DAD_1

#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)

0x00800000

◆ USB_OTG_HCCHAR_DAD_2

#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)

0x01000000

◆ USB_OTG_HCCHAR_DAD_3

#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)

0x02000000

◆ USB_OTG_HCCHAR_DAD_4

#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)

0x04000000

◆ USB_OTG_HCCHAR_DAD_5

#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)

0x08000000

◆ USB_OTG_HCCHAR_DAD_6

#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)

0x10000000

◆ USB_OTG_HCCHAR_DAD_Msk

#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)

0x1FC00000

◆ USB_OTG_HCCHAR_EPDIR

#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk

Endpoint direction

◆ USB_OTG_HCCHAR_EPDIR_Msk

#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)

0x00008000

◆ USB_OTG_HCCHAR_EPNUM

#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk

Endpoint number

◆ USB_OTG_HCCHAR_EPNUM_0

#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)

0x00000800

◆ USB_OTG_HCCHAR_EPNUM_1

#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)

0x00001000

◆ USB_OTG_HCCHAR_EPNUM_2

#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)

0x00002000

◆ USB_OTG_HCCHAR_EPNUM_3

#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)

0x00004000

◆ USB_OTG_HCCHAR_EPNUM_Msk

#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)

0x00007800

◆ USB_OTG_HCCHAR_EPTYP

#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk

Endpoint type

◆ USB_OTG_HCCHAR_EPTYP_0

#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)

0x00040000

◆ USB_OTG_HCCHAR_EPTYP_1

#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)

0x00080000

◆ USB_OTG_HCCHAR_EPTYP_Msk

#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)

0x000C0000

◆ USB_OTG_HCCHAR_LSDEV

#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk

Low-speed device

◆ USB_OTG_HCCHAR_LSDEV_Msk

#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)

0x00020000

◆ USB_OTG_HCCHAR_MC

#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk

Multi Count (MC) / Error Count (EC)

◆ USB_OTG_HCCHAR_MC_0

#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)

0x00100000

◆ USB_OTG_HCCHAR_MC_1

#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)

0x00200000

◆ USB_OTG_HCCHAR_MC_Msk

#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)

0x00300000

◆ USB_OTG_HCCHAR_MPSIZ

#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk

Maximum packet size

◆ USB_OTG_HCCHAR_MPSIZ_Msk

#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)

0x000007FF

◆ USB_OTG_HCCHAR_ODDFRM

#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk

Odd frame

◆ USB_OTG_HCCHAR_ODDFRM_Msk

#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)

0x20000000

◆ USB_OTG_HCDMA_DMAADDR

#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk

DMA address

◆ USB_OTG_HCDMA_DMAADDR_Msk

#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)

0xFFFFFFFF

◆ USB_OTG_HCFG_FSLSPCS

#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk

FS/LS PHY clock select

◆ USB_OTG_HCFG_FSLSPCS_0

#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)

0x00000001

◆ USB_OTG_HCFG_FSLSPCS_1

#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)

0x00000002

◆ USB_OTG_HCFG_FSLSPCS_Msk

#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)

0x00000003

◆ USB_OTG_HCFG_FSLSS

#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk

FS- and LS-only support

◆ USB_OTG_HCFG_FSLSS_Msk

#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)

0x00000004

◆ USB_OTG_HCINT_ACK

#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk

ACK response received/transmitted interrupt

◆ USB_OTG_HCINT_ACK_Msk

#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)

0x00000020

◆ USB_OTG_HCINT_AHBERR

#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk

AHB error

◆ USB_OTG_HCINT_AHBERR_Msk

#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)

0x00000004

◆ USB_OTG_HCINT_BBERR

#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk

Babble error

◆ USB_OTG_HCINT_BBERR_Msk

#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)

0x00000100

◆ USB_OTG_HCINT_CHH

#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk

Channel halted

◆ USB_OTG_HCINT_CHH_Msk

#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)

0x00000002

◆ USB_OTG_HCINT_DTERR

#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk

Data toggle error

◆ USB_OTG_HCINT_DTERR_Msk

#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)

0x00000400

◆ USB_OTG_HCINT_FRMOR

#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk

Frame overrun

◆ USB_OTG_HCINT_FRMOR_Msk

#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)

0x00000200

◆ USB_OTG_HCINT_NAK

#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk

NAK response received interrupt

◆ USB_OTG_HCINT_NAK_Msk

#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)

0x00000010

◆ USB_OTG_HCINT_NYET

#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk

Response received interrupt

◆ USB_OTG_HCINT_NYET_Msk

#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)

0x00000040

◆ USB_OTG_HCINT_STALL

#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk

STALL response received interrupt

◆ USB_OTG_HCINT_STALL_Msk

#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)

0x00000008

◆ USB_OTG_HCINT_TXERR

#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk

Transaction error

◆ USB_OTG_HCINT_TXERR_Msk

#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)

0x00000080

◆ USB_OTG_HCINT_XFRC

#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk

Transfer completed

◆ USB_OTG_HCINT_XFRC_Msk

#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)

0x00000001

◆ USB_OTG_HCINTMSK_ACKM

#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk

ACK response received/transmitted interrupt mask

◆ USB_OTG_HCINTMSK_ACKM_Msk

#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)

0x00000020

◆ USB_OTG_HCINTMSK_AHBERR

#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk

AHB error

◆ USB_OTG_HCINTMSK_AHBERR_Msk

#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)

0x00000004

◆ USB_OTG_HCINTMSK_BBERRM

#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk

Babble error mask

◆ USB_OTG_HCINTMSK_BBERRM_Msk

#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)

0x00000100

◆ USB_OTG_HCINTMSK_CHHM

#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk

Channel halted mask

◆ USB_OTG_HCINTMSK_CHHM_Msk

#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)

0x00000002

◆ USB_OTG_HCINTMSK_DTERRM

#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk

Data toggle error mask

◆ USB_OTG_HCINTMSK_DTERRM_Msk

#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)

0x00000400

◆ USB_OTG_HCINTMSK_FRMORM

#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk

Frame overrun mask

◆ USB_OTG_HCINTMSK_FRMORM_Msk

#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)

0x00000200

◆ USB_OTG_HCINTMSK_NAKM

#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk

NAK response received interrupt mask

◆ USB_OTG_HCINTMSK_NAKM_Msk

#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)

0x00000010

◆ USB_OTG_HCINTMSK_NYET

#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk

response received interrupt mask

◆ USB_OTG_HCINTMSK_NYET_Msk

#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)

0x00000040

◆ USB_OTG_HCINTMSK_STALLM

#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk

STALL response received interrupt mask

◆ USB_OTG_HCINTMSK_STALLM_Msk

#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)

0x00000008

◆ USB_OTG_HCINTMSK_TXERRM

#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk

Transaction error mask

◆ USB_OTG_HCINTMSK_TXERRM_Msk

#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)

0x00000080

◆ USB_OTG_HCINTMSK_XFRCM

#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk

Transfer completed mask

◆ USB_OTG_HCINTMSK_XFRCM_Msk

#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)

0x00000001

◆ USB_OTG_HCSPLT_COMPLSPLT

#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk

Do complete split

◆ USB_OTG_HCSPLT_COMPLSPLT_Msk

#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)

0x00010000

◆ USB_OTG_HCSPLT_HUBADDR

#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk

Hub address

◆ USB_OTG_HCSPLT_HUBADDR_0

#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00000080

◆ USB_OTG_HCSPLT_HUBADDR_1

#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00000100

◆ USB_OTG_HCSPLT_HUBADDR_2

#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00000200

◆ USB_OTG_HCSPLT_HUBADDR_3

#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00000400

◆ USB_OTG_HCSPLT_HUBADDR_4

#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00000800

◆ USB_OTG_HCSPLT_HUBADDR_5

#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00001000

◆ USB_OTG_HCSPLT_HUBADDR_6

#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00002000

◆ USB_OTG_HCSPLT_HUBADDR_Msk

#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)

0x00003F80

◆ USB_OTG_HCSPLT_PRTADDR

#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk

Port address

◆ USB_OTG_HCSPLT_PRTADDR_0

#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000001

◆ USB_OTG_HCSPLT_PRTADDR_1

#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000002

◆ USB_OTG_HCSPLT_PRTADDR_2

#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000004

◆ USB_OTG_HCSPLT_PRTADDR_3

#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000008

◆ USB_OTG_HCSPLT_PRTADDR_4

#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000010

◆ USB_OTG_HCSPLT_PRTADDR_5

#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000020

◆ USB_OTG_HCSPLT_PRTADDR_6

#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x00000040

◆ USB_OTG_HCSPLT_PRTADDR_Msk

#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)

0x0000007F

◆ USB_OTG_HCSPLT_SPLITEN

#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk

Split enable

◆ USB_OTG_HCSPLT_SPLITEN_Msk

#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)

0x80000000

◆ USB_OTG_HCSPLT_XACTPOS

#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk

XACTPOS

◆ USB_OTG_HCSPLT_XACTPOS_0

#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)

0x00004000

◆ USB_OTG_HCSPLT_XACTPOS_1

#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)

0x00008000

◆ USB_OTG_HCSPLT_XACTPOS_Msk

#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)

0x0000C000

◆ USB_OTG_HCTSIZ_DOPING

#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk

Do PING

◆ USB_OTG_HCTSIZ_DOPING_Msk

#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)

0x80000000

◆ USB_OTG_HCTSIZ_DPID

#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk

Data PID

◆ USB_OTG_HCTSIZ_DPID_0

#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)

0x20000000

◆ USB_OTG_HCTSIZ_DPID_1

#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)

0x40000000

◆ USB_OTG_HCTSIZ_DPID_Msk

#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)

0x60000000

◆ USB_OTG_HCTSIZ_PKTCNT

#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk

Packet count

◆ USB_OTG_HCTSIZ_PKTCNT_Msk

#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)

0x1FF80000

◆ USB_OTG_HCTSIZ_XFRSIZ

#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk

Transfer size

◆ USB_OTG_HCTSIZ_XFRSIZ_Msk

#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)

0x0007FFFF

◆ USB_OTG_HFIR_FRIVL

#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk

Frame interval

◆ USB_OTG_HFIR_FRIVL_Msk

#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)

0x0000FFFF

◆ USB_OTG_HFNUM_FRNUM

#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk

Frame number

◆ USB_OTG_HFNUM_FRNUM_Msk

#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)

0x0000FFFF

◆ USB_OTG_HFNUM_FTREM

#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk

Frame time remaining

◆ USB_OTG_HFNUM_FTREM_Msk

#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)

0xFFFF0000

◆ USB_OTG_HPRT_PCDET

#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk

Port connect detected

◆ USB_OTG_HPRT_PCDET_Msk

#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)

0x00000002

◆ USB_OTG_HPRT_PCSTS

#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk

Port connect status

◆ USB_OTG_HPRT_PCSTS_Msk

#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)

0x00000001

◆ USB_OTG_HPRT_PENA

#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk

Port enable

◆ USB_OTG_HPRT_PENA_Msk

#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)

0x00000004

◆ USB_OTG_HPRT_PENCHNG

#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk

Port enable/disable change

◆ USB_OTG_HPRT_PENCHNG_Msk

#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)

0x00000008

◆ USB_OTG_HPRT_PLSTS

#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk

Port line status

◆ USB_OTG_HPRT_PLSTS_0

#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)

0x00000400

◆ USB_OTG_HPRT_PLSTS_1

#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)

0x00000800

◆ USB_OTG_HPRT_PLSTS_Msk

#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)

0x00000C00

◆ USB_OTG_HPRT_POCA

#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk

Port overcurrent active

◆ USB_OTG_HPRT_POCA_Msk

#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)

0x00000010

◆ USB_OTG_HPRT_POCCHNG

#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk

Port overcurrent change

◆ USB_OTG_HPRT_POCCHNG_Msk

#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)

0x00000020

◆ USB_OTG_HPRT_PPWR

#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk

Port power

◆ USB_OTG_HPRT_PPWR_Msk

#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)

0x00001000

◆ USB_OTG_HPRT_PRES

#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk

Port resume

◆ USB_OTG_HPRT_PRES_Msk

#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)

0x00000040

◆ USB_OTG_HPRT_PRST

#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk

Port reset

◆ USB_OTG_HPRT_PRST_Msk

#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)

0x00000100

◆ USB_OTG_HPRT_PSPD

#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk

Port speed

◆ USB_OTG_HPRT_PSPD_0

#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)

0x00020000

◆ USB_OTG_HPRT_PSPD_1

#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)

0x00040000

◆ USB_OTG_HPRT_PSPD_Msk

#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)

0x00060000

◆ USB_OTG_HPRT_PSUSP

#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk

Port suspend

◆ USB_OTG_HPRT_PSUSP_Msk

#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)

0x00000080

◆ USB_OTG_HPRT_PTCTL

#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk

Port test control

◆ USB_OTG_HPRT_PTCTL_0

#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)

0x00002000

◆ USB_OTG_HPRT_PTCTL_1

#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)

0x00004000

◆ USB_OTG_HPRT_PTCTL_2

#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)

0x00008000

◆ USB_OTG_HPRT_PTCTL_3

#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)

0x00010000

◆ USB_OTG_HPRT_PTCTL_Msk

#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)

0x0001E000

◆ USB_OTG_HPTXFSIZ_PTXFD

#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk

Host periodic TxFIFO depth

◆ USB_OTG_HPTXFSIZ_PTXFD_Msk

#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)

0xFFFF0000

◆ USB_OTG_HPTXFSIZ_PTXSA

#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk

Host periodic TxFIFO start address

◆ USB_OTG_HPTXFSIZ_PTXSA_Msk

#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)

0x0000FFFF

◆ USB_OTG_HPTXSTS_PTXFSAVL

#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk

Periodic transmit data FIFO space available

◆ USB_OTG_HPTXSTS_PTXFSAVL_Msk

#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)

0x0000FFFF

◆ USB_OTG_HPTXSTS_PTXQSAV

#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk

Periodic transmit request queue space available

◆ USB_OTG_HPTXSTS_PTXQSAV_0

#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00010000

◆ USB_OTG_HPTXSTS_PTXQSAV_1

#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00020000

◆ USB_OTG_HPTXSTS_PTXQSAV_2

#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00040000

◆ USB_OTG_HPTXSTS_PTXQSAV_3

#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00080000

◆ USB_OTG_HPTXSTS_PTXQSAV_4

#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00100000

◆ USB_OTG_HPTXSTS_PTXQSAV_5

#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00200000

◆ USB_OTG_HPTXSTS_PTXQSAV_6

#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00400000

◆ USB_OTG_HPTXSTS_PTXQSAV_7

#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00800000

◆ USB_OTG_HPTXSTS_PTXQSAV_Msk

#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

0x00FF0000

◆ USB_OTG_HPTXSTS_PTXQTOP

#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk

Top of the periodic transmit request queue

◆ USB_OTG_HPTXSTS_PTXQTOP_0

#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x01000000

◆ USB_OTG_HPTXSTS_PTXQTOP_1

#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x02000000

◆ USB_OTG_HPTXSTS_PTXQTOP_2

#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x04000000

◆ USB_OTG_HPTXSTS_PTXQTOP_3

#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x08000000

◆ USB_OTG_HPTXSTS_PTXQTOP_4

#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x10000000

◆ USB_OTG_HPTXSTS_PTXQTOP_5

#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x20000000

◆ USB_OTG_HPTXSTS_PTXQTOP_6

#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x40000000

◆ USB_OTG_HPTXSTS_PTXQTOP_7

#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0x80000000

◆ USB_OTG_HPTXSTS_PTXQTOP_Msk

#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

0xFF000000

◆ USB_OTG_NPTXFD

#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk

Nonperiodic TxFIFO depth

◆ USB_OTG_NPTXFD_Msk

#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)

0xFFFF0000

◆ USB_OTG_NPTXFSA

#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk

Nonperiodic transmit RAM start address

◆ USB_OTG_NPTXFSA_Msk

#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)

0x0000FFFF

◆ USB_OTG_PCGCCTL_GATECLK

#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk

Bit 0

◆ USB_OTG_PCGCCTL_GATECLK_Msk

#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)

0x00000002

◆ USB_OTG_PCGCCTL_PHYSUSP

#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk

Bit 1

◆ USB_OTG_PCGCCTL_PHYSUSP_Msk

#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)

0x00000010

◆ USB_OTG_PCGCCTL_STOPCLK

#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk

SETUP packet count

◆ USB_OTG_PCGCCTL_STOPCLK_Msk

#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)

0x00000001

◆ USB_OTG_PCGCR_GATEHCLK

#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk

Gate HCLK

◆ USB_OTG_PCGCR_GATEHCLK_Msk

#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)

0x00000002

◆ USB_OTG_PCGCR_PHYSUSP

#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk

PHY suspended

◆ USB_OTG_PCGCR_PHYSUSP_Msk

#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)

0x00000010

◆ USB_OTG_PCGCR_STPPCLK

#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk

Stop PHY clock

◆ USB_OTG_PCGCR_STPPCLK_Msk

#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)

0x00000001

◆ USB_OTG_PKTSTS

#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk

Packet status

◆ USB_OTG_PKTSTS_0

#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)

0x00020000

◆ USB_OTG_PKTSTS_1

#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)

0x00040000

◆ USB_OTG_PKTSTS_2

#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)

0x00080000

◆ USB_OTG_PKTSTS_3

#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)

0x00100000

◆ USB_OTG_PKTSTS_Msk

#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)

0x001E0000

◆ USB_OTG_TX0FD

#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk

Endpoint 0 TxFIFO depth

◆ USB_OTG_TX0FD_Msk

#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)

0xFFFF0000

◆ USB_OTG_TX0FSA

#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk

Endpoint 0 transmit RAM start address

◆ USB_OTG_TX0FSA_Msk

#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)

0x0000FFFF

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk

Early Wakeup Interrupt

◆ WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

0x00000200

◆ WWDG_CFR_W

#define WWDG_CFR_W WWDG_CFR_W_Msk

W[6:0] bits (7-bit window value)

◆ WWDG_CFR_W_0

#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

0x0001

◆ WWDG_CFR_W_1

#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

0x0002

◆ WWDG_CFR_W_2

#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

0x0004

◆ WWDG_CFR_W_3

#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

0x0008

◆ WWDG_CFR_W_4

#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

0x0010

◆ WWDG_CFR_W_5

#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

0x0020

◆ WWDG_CFR_W_6

#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

0x0040

◆ WWDG_CFR_W_Msk

#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

0x0000007F

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

WDGTB[1:0] bits (Timer Base)

◆ WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

0x0080

◆ WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

0x0100

◆ WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)

0x00000180

◆ WWDG_CR_T

#define WWDG_CR_T WWDG_CR_T_Msk

T[6:0] bits (7-Bit counter (MSB to LSB))

◆ WWDG_CR_T_0

#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

0x01

◆ WWDG_CR_T_1

#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

0x02

◆ WWDG_CR_T_2

#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

0x04

◆ WWDG_CR_T_3

#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

0x08

◆ WWDG_CR_T_4

#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

0x10

◆ WWDG_CR_T_5

#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

0x20

◆ WWDG_CR_T_6

#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

0x40

◆ WWDG_CR_T_Msk

#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

0x0000007F

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk

Activation bit

◆ WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

0x00000080

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Early Wakeup Interrupt Flag

◆ WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

0x00000001

Macros

Detailed Description

Macro Definition Documentation

◆ ADC_CCR_ADCPRE

◆ ADC_CCR_ADCPRE_0

◆ ADC_CCR_ADCPRE_1

◆ ADC_CCR_ADCPRE_Msk

◆ ADC_CCR_DDS

◆ ADC_CCR_DDS_Msk

◆ ADC_CCR_DELAY

◆ ADC_CCR_DELAY_0

◆ ADC_CCR_DELAY_1

◆ ADC_CCR_DELAY_2

◆ ADC_CCR_DELAY_3

◆ ADC_CCR_DELAY_Msk

◆ ADC_CCR_DMA

◆ ADC_CCR_DMA_0

◆ ADC_CCR_DMA_1

◆ ADC_CCR_DMA_Msk

◆ ADC_CCR_MULTI

◆ ADC_CCR_MULTI_0

◆ ADC_CCR_MULTI_1

◆ ADC_CCR_MULTI_2

◆ ADC_CCR_MULTI_3

◆ ADC_CCR_MULTI_4

◆ ADC_CCR_MULTI_Msk

◆ ADC_CCR_TSVREFE

◆ ADC_CCR_TSVREFE_Msk

◆ ADC_CCR_VBATE

◆ ADC_CCR_VBATE_Msk

◆ ADC_CDR_DATA1

◆ ADC_CDR_DATA1_Msk

◆ ADC_CDR_DATA2

◆ ADC_CDR_DATA2_Msk

◆ ADC_CR1_AWDCH

◆ ADC_CR1_AWDCH_0

◆ ADC_CR1_AWDCH_1

◆ ADC_CR1_AWDCH_2

◆ ADC_CR1_AWDCH_3

◆ ADC_CR1_AWDCH_4

◆ ADC_CR1_AWDCH_Msk

◆ ADC_CR1_AWDEN

◆ ADC_CR1_AWDEN_Msk

◆ ADC_CR1_AWDIE

◆ ADC_CR1_AWDIE_Msk

◆ ADC_CR1_AWDSGL

◆ ADC_CR1_AWDSGL_Msk

◆ ADC_CR1_DISCEN

◆ ADC_CR1_DISCEN_Msk

◆ ADC_CR1_DISCNUM

◆ ADC_CR1_DISCNUM_0

◆ ADC_CR1_DISCNUM_1

◆ ADC_CR1_DISCNUM_2

◆ ADC_CR1_DISCNUM_Msk

◆ ADC_CR1_EOCIE

◆ ADC_CR1_EOCIE_Msk

◆ ADC_CR1_JAUTO

◆ ADC_CR1_JAUTO_Msk

◆ ADC_CR1_JAWDEN

◆ ADC_CR1_JAWDEN_Msk

◆ ADC_CR1_JDISCEN

◆ ADC_CR1_JDISCEN_Msk

◆ ADC_CR1_JEOCIE

◆ ADC_CR1_JEOCIE_Msk

◆ ADC_CR1_OVRIE

◆ ADC_CR1_OVRIE_Msk

◆ ADC_CR1_RES

◆ ADC_CR1_RES_0

◆ ADC_CR1_RES_1

◆ ADC_CR1_RES_Msk

◆ ADC_CR1_SCAN

◆ ADC_CR1_SCAN_Msk

◆ ADC_CR2_ADON

◆ ADC_CR2_ADON_Msk

◆ ADC_CR2_ALIGN

◆ ADC_CR2_ALIGN_Msk

◆ ADC_CR2_CONT

◆ ADC_CR2_CONT_Msk

◆ ADC_CR2_DDS

◆ ADC_CR2_DDS_Msk